#include "mac.h"
bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
unsigned char byTestBits)
{
void __iomem *io_base = priv->port_offset;
return !(ioread8(io_base + byRegOfs) & byTestBits);
}
bool MACbIsIntDisable(struct vnt_private *priv)
{
void __iomem *io_base = priv->port_offset;
if (ioread32(io_base + MAC_REG_IMR))
return false;
return true;
}
void MACvSetShortRetryLimit(struct vnt_private *priv,
unsigned char byRetryLimit)
{
void __iomem *io_base = priv->port_offset;
iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
}
void MACvSetLongRetryLimit(struct vnt_private *priv,
unsigned char byRetryLimit)
{
void __iomem *io_base = priv->port_offset;
iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
}
void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
{
void __iomem *io_base = priv->port_offset;
byLoopbackMode <<= 6;
iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
io_base + MAC_REG_TEST);
}
void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
{
void __iomem *io_base = priv->port_offset;
memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
MACvSelectPage1(io_base);
memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
MAC_MAX_CONTEXT_SIZE_PAGE1);
MACvSelectPage0(io_base);
}
void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
{
void __iomem *io_base = priv->port_offset;
MACvSelectPage1(io_base);
memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
MAC_MAX_CONTEXT_SIZE_PAGE1);
MACvSelectPage0(io_base);
memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
MAC_REG_ISR - MAC_REG_RCR);
memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
MAC_REG_PAGE1SEL - MAC_REG_LRT);
iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
MAC_REG_BBREGCTL - MAC_REG_PSCFG);
iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
io_base + MAC_REG_TXDMAPTR0);
iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
io_base + MAC_REG_AC0DMAPTR);
iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
io_base + MAC_REG_BCNDMAPTR);
iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
io_base + MAC_REG_RXDMAPTR0);
iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
io_base + MAC_REG_RXDMAPTR1);
}
bool MACbSoftwareReset(struct vnt_private *priv)
{
void __iomem *io_base = priv->port_offset;
unsigned short ww;
iowrite8(0x01, io_base + MAC_REG_HOSTCR);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
break;
}
if (ww == W_MAX_TIMEOUT)
return false;
return true;
}
bool MACbSafeSoftwareReset(struct vnt_private *priv)
{
unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1];
bool bRetVal;
MACvSaveContext(priv, abyTmpRegData);
bRetVal = MACbSoftwareReset(priv);
MACvRestoreContext(priv, abyTmpRegData);
return bRetVal;
}
bool MACbSafeRxOff(struct vnt_private *priv)
{
void __iomem *io_base = priv->port_offset;
unsigned short ww;
iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x10)\n");
return false;
}
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x11)\n");
return false;
}
MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x12)\n");
return false;
}
return true;
}
bool MACbSafeTxOff(struct vnt_private *priv)
{
void __iomem *io_base = priv->port_offset;
unsigned short ww;
iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x20)\n");
return false;
}
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x21)\n");
return false;
}
MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x24)\n");
return false;
}
return true;
}
bool MACbSafeStop(struct vnt_private *priv)
{
void __iomem *io_base = priv->port_offset;
MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
if (!MACbSafeRxOff(priv)) {
pr_debug(" MACbSafeRxOff == false)\n");
MACbSafeSoftwareReset(priv);
return false;
}
if (!MACbSafeTxOff(priv)) {
pr_debug(" MACbSafeTxOff == false)\n");
MACbSafeSoftwareReset(priv);
return false;
}
MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
return true;
}
bool MACbShutdown(struct vnt_private *priv)
{
void __iomem *io_base = priv->port_offset;
MACvIntDisable(io_base);
MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
if (!MACbSafeStop(priv)) {
MACvSetLoopbackMode(priv, MAC_LB_NONE);
return false;
}
MACvSetLoopbackMode(priv, MAC_LB_NONE);
return true;
}
void MACvInitialize(struct vnt_private *priv)
{
void __iomem *io_base = priv->port_offset;
MACvClearStckDS(io_base);
iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
MACbSoftwareReset(priv);
iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
}
void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
{
void __iomem *io_base = priv->port_offset;
unsigned short ww;
unsigned char org_dma_ctl;
org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
if (org_dma_ctl & DMACTL_RUN)
iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
break;
}
iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
if (org_dma_ctl & DMACTL_RUN)
iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
}
void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
{
void __iomem *io_base = priv->port_offset;
unsigned short ww;
unsigned char org_dma_ctl;
org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
if (org_dma_ctl & DMACTL_RUN)
iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
break;
}
iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
if (org_dma_ctl & DMACTL_RUN)
iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
}
void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
u32 curr_desc_addr)
{
void __iomem *io_base = priv->port_offset;
unsigned short ww;
unsigned char org_dma_ctl;
org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
if (org_dma_ctl & DMACTL_RUN)
iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
break;
}
iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
if (org_dma_ctl & DMACTL_RUN)
iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
}
void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
u32 curr_desc_addr)
{
void __iomem *io_base = priv->port_offset;
unsigned short ww;
unsigned char org_dma_ctl;
org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
if (org_dma_ctl & DMACTL_RUN)
iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT)
pr_debug(" DBG_PORT80(0x26)\n");
iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
if (org_dma_ctl & DMACTL_RUN)
iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
}
void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
u32 curr_desc_addr)
{
if (iTxType == TYPE_AC0DMA)
MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
else if (iTxType == TYPE_TXDMA0)
MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
}
void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
{
void __iomem *io_base = priv->port_offset;
unsigned char byValue;
unsigned int uu, ii;
iowrite8(0, io_base + MAC_REG_TMCTL0);
iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
for (ii = 0; ii < 66; ii++) {
for (uu = 0; uu < uDelay; uu++) {
byValue = ioread8(io_base + MAC_REG_TMCTL0);
if ((byValue == 0) ||
(byValue & TMCTL_TSUSP)) {
iowrite8(0, io_base + MAC_REG_TMCTL0);
return;
}
}
}
iowrite8(0, io_base + MAC_REG_TMCTL0);
}
void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
unsigned int uDelayTime)
{
void __iomem *io_base = priv->port_offset;
iowrite8(0, io_base + MAC_REG_TMCTL1);
iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
}
void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
u32 data)
{
void __iomem *io_base = priv->port_offset;
if (offset > 273)
return;
iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
iowrite32(data, io_base + MAC_REG_MISCFFDATA);
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
}
bool MACbPSWakeup(struct vnt_private *priv)
{
void __iomem *io_base = priv->port_offset;
unsigned int ww;
if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
return true;
MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x33)\n");
return false;
}
return true;
}
void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
unsigned int uEntryIdx, unsigned int uKeyIdx,
unsigned char *pbyAddr, u32 *pdwKey,
unsigned char local_id)
{
void __iomem *io_base = priv->port_offset;
unsigned short offset;
u32 data;
int ii;
if (local_id <= 1)
return;
offset = MISCFIFO_KEYETRY0;
offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
data = 0;
data |= wKeyCtl;
data <<= 16;
data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
offset, data, wKeyCtl);
iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
iowrite32(data, io_base + MAC_REG_MISCFFDATA);
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
offset++;
data = 0;
data |= *(pbyAddr + 3);
data <<= 8;
data |= *(pbyAddr + 2);
data <<= 8;
data |= *(pbyAddr + 1);
data <<= 8;
data |= *pbyAddr;
pr_debug("2. offset: %d, Data: %X\n", offset, data);
iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
iowrite32(data, io_base + MAC_REG_MISCFFDATA);
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
offset++;
offset += (uKeyIdx * 4);
for (ii = 0; ii < 4; ii++) {
pr_debug("3.(%d) offset: %d, Data: %X\n",
ii, offset + ii, *pdwKey);
iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
}
}
void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
{
void __iomem *io_base = priv->port_offset;
unsigned short offset;
offset = MISCFIFO_KEYETRY0;
offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
iowrite32(0, io_base + MAC_REG_MISCFFDATA);
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
}