Symbol: dpcd

function parameter

Defined...

• drivers/gpu/drm/amd/amdgpu/atombios_dp.c:253:8-253:34: const u8 dpcd[DP_DPCD_SIZE],
• drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c:1401:10-1401:38: u8 dpcd[DP_RECEIVER_CAP_SIZE])
• drivers/gpu/drm/bridge/ite-it6505.c:626:63-626:67: static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
• drivers/gpu/drm/display/drm_dp_helper.c:284:49-284:83: static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:339:62-339:96: int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:346:58-346:92: int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:374:10-374:44: const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• drivers/gpu/drm/display/drm_dp_helper.c:398:6-398:40: const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• drivers/gpu/drm/display/drm_dp_helper.c:769:32-769:66: bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:786:32-786:66: bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:873:40-873:74: static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• drivers/gpu/drm/display/drm_dp_helper.c:884:8-884:36: u8 dpcd[DP_RECEIVER_CAP_SIZE])
• drivers/gpu/drm/display/drm_dp_helper.c:938:6-938:34: u8 dpcd[DP_RECEIVER_CAP_SIZE])
• drivers/gpu/drm/display/drm_dp_helper.c:972:5-972:39: const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1015:36-1015:70: int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1044:38-1044:72: int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1109:38-1109:72: int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1152:31-1152:65: int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1208:40-1208:74: bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1239:46-1239:80: bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1270:48-1270:82: bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1304:10-1304:44: const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1370:9-1370:43: const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1457:26-1457:60: drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:1514:11-1514:21: const u8 *dpcd,
• drivers/gpu/drm/display/drm_dp_helper.c:1540:5-1540:39: const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:2464:7-2464:41: const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
• drivers/gpu/drm/display/drm_dp_helper.c:2500:7-2500:41: const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:2521:11-2521:45: const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_helper.c:2892:32-2892:66: int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/display/drm_dp_mst_topology.c:3577:5-3577:39: const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• drivers/gpu/drm/i915/display/intel_dp_link_training.c:68:7-68:41: const u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/i915/display/intel_dp_link_training.c:84:10-84:44: const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• drivers/gpu/drm/i915/display/intel_dp_link_training.c:117:59-117:93: static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• drivers/gpu/drm/i915/gvt/handlers.c:1122:41-1122:70: static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
• drivers/gpu/drm/nouveau/nvif/outp.c:130:46-130:74: nvif_outp_acquire_dp(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c:149:52-149:80: nvkm_uoutp_mthd_acquire_dp(struct nvkm_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE],
• drivers/gpu/drm/radeon/atombios_dp.c:307:6-307:32: const u8 dpcd[DP_DPCD_SIZE],
• include/drm/display/drm_dp_helper.h:107:22-107:56: drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:113:23-113:57: drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:119:27-119:61: drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:126:26-126:60: drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:133:23-133:57: drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:140:23-140:57: drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:147:23-147:57: drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:154:30-154:64: drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:161:18-161:52: drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:217:33-217:67: drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:223:38-223:72: drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
• include/drm/display/drm_dp_helper.h:231:45-231:79: drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

variable

Defined...

• drivers/gpu/drm/bridge/analogix/analogix-anx6345.c:99:2-99:18: u8 dp_bw, dpcd[2];
• drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c:606:2-606:18: u8 dp_bw, dpcd[2];
• drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c:1426:2-1426:30: u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2];
• drivers/gpu/drm/i915/display/intel_dp.c:4618:2-4618:23: u8 *dpcd = intel_dp->dpcd;
• drivers/gpu/drm/i915/display/intel_dp_link_training.c:194:3-194:31: u8 dpcd[DP_RECEIVER_CAP_SIZE];
• drivers/gpu/drm/i915/gvt/handlers.c:1167:2-1167:38: struct intel_vgpu_dpcd_data *dpcd = NULL;
• drivers/gpu/drm/msm/dp/dp_ctrl.c:126:2-126:32: const u8 *dpcd = ctrl->panel->dpcd;
• drivers/gpu/drm/msm/dp/dp_ctrl.c:1250:2-1250:32: const u8 *dpcd = ctrl->panel->dpcd;
• drivers/gpu/drm/msm/dp/dp_ctrl.c:1347:2-1347:32: const u8 *dpcd = ctrl->panel->dpcd;
• drivers/gpu/drm/msm/dp/dp_ctrl.c:1476:2-1476:32: const u8 *dpcd = ctrl->panel->dpcd;
• drivers/gpu/drm/msm/dp/dp_panel.c:51:2-51:6: u8 *dpcd, major = 0, minor = 0, temp;
• drivers/gpu/drm/nouveau/nouveau_dp.c:54:2-54:22: u8 *dpcd = outp->dp.dpcd;
• drivers/gpu/drm/nouveau/nouveau_dp.c:108:2-108:28: u8 *dpcd = nv_encoder->dp.dpcd;
• drivers/gpu/drm/tegra/dp.c:172:2-172:30: u8 dpcd[DP_RECEIVER_CAP_SIZE], value;