Symbol: REG

enum value global

Defined...

• drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:69:2-69:2: REG,

macro public

Defined...

• drivers/gpio/gpio-it87.c:37:9-37:14: #define REG 0x2e
• drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c:50:9-51:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c:46:9-47:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c:46:9-47:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c:65:9-66:77: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:46:9-47:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:42:9-43:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c:50:9-51:77: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c:38:9-39:77: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:51:9-52:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c:40:9-41:8: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c:38:9-39:77: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c:58:9-59:77: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c:69:9-70:79: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c:37:9-38:79: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c:90:9-91:79: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c:53:9-53:70: #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c:63:9-64:79: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c:53:9-54:79: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c:81:9-82:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c:37:9-38:8: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/dce/dce_abm.c:40:9-41:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dce/dce_audio.c:39:9-40:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce/dce_aux.c:36:9-37:25: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c:40:9-41:21: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c:37:9-38:22: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c:33:9-34:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c:36:9-37:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c:30:9-31:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c:61:9-62:25: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c:32:9-33:16: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce/dce_opp.c:33:9-34:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c:42:9-43:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c:34:9-35:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce/dce_transform.c:32:9-33:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c:46:9-47:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c:409:9-409:24: #define REG(reg) mm ## reg
• drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:87:9-88:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c:457:9-457:24: #define REG(reg) mm ## reg
• drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c:437:9-437:24: #define REG(reg) mm ## reg
• drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c:42:9-43:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c:442:9-442:24: #define REG(reg) mm ## reg
• drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c:449:9-449:24: #define REG(reg) mm ## reg
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c:32:9-32:18: #define REG(reg) reg
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c:41:9-42:16: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c:42:9-43:16: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c:43:9-44:16: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c:35:9-36:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c:31:9-32:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:64:9-65:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c:30:9-31:20: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c:41:9-42:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c:29:9-30:19: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c:30:9-31:20: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c:32:9-33:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c:38:9-39:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c:35:9-36:22: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c:41:9-42:16: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c:36:9-37:16: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c:59:9-60:19: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c:33:9-34:21: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c:36:9-37:21: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c:31:9-32:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c:41:9-42:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c:35:9-36:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c:63:9-64:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c:41:9-42:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c:33:9-34:27: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c:33:9-34:19: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c:30:9-31:20: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c:30:9-31:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c:38:9-39:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c:31:9-32:14: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.c:34:9-35:22: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c:34:9-35:16: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c:30:9-31:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c:43:9-44:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c:32:9-33:22: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c:46:9-47:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c:42:9-43:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c:29:9-30:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c:30:9-31:21: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c:31:9-32:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c:34:9-35:22: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c:31:9-32:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c:42:9-43:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c:36:9-37:21: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c:44:9-45:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c:43:9-44:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c:1360:9-1361:77: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c:35:9-36:19: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c:34:9-34:18: #define REG(reg) reg
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c:33:9-34:22: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c:42:9-43:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c:39:9-40:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c:33:9-34:16: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c:33:9-34:16: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c:33:9-34:21: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c:36:9-37:21: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c:36:9-37:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c:35:9-36:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c:62:9-63:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c:33:9-34:27: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c:33:9-34:19: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c:35:9-36:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c:2235:9-2236:77: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c:34:9-35:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c:33:9-34:22: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c:40:9-41:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c:29:9-30:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c:40:9-41:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.c:35:9-36:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c:35:9-36:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c:41:9-42:27: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c:917:9-918:77: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c:37:9-38:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.c:19:9-20:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c:36:9-37:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c:35:9-36:19: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c:34:9-35:22: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c:47:9-48:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c:34:9-35:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c:34:9-35:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c:37:9-38:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c:32:9-33:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c:58:9-59:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c:33:9-34:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c:35:9-36:19: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c:36:9-37:22: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c:39:9-40:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c:62:9-63:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c:35:9-36:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c:33:9-34:22: #define REG(reg) \
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c:48:9-49:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c:38:9-39:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c:34:9-35:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c:37:9-38:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c:32:9-33:20: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c:58:9-59:13: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c:33:9-34:27: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c:34:9-35:19: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c:35:9-36:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c:193:9-194:71: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c:47:9-48:24: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c:195:9-196:71: #define REG(reg_name) \
• drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c:36:9-37:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c:45:9-46:9: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c:60:9-61:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c:51:9-52:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c:41:9-42:9: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c:41:9-42:9: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c:57:9-58:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c:51:9-52:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c:59:9-60:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c:55:9-56:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c:57:9-58:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c:55:9-56:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c:66:9-67:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c:60:9-61:45: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c:63:9-64:47: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c:55:9-56:47: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c:59:9-60:47: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c:53:9-54:47: #define REG(reg_name)\
• drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c:43:9-44:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c:44:9-45:21: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c:39:9-40:18: #define REG(reg)\
• drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c:42:9-43:17: #define REG(reg)\
• drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h:43:9-43:33: #define REG(reg) (REGS)->offset.reg
• drivers/gpu/drm/i2c/tda998x_drv.c:104:9-104:48: #define REG(page, addr) (((page) << 8) | (addr))
• drivers/gpu/drm/i915/gt/intel_lrc.c:54:9-54:59: #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))
• drivers/gpu/drm/tidss/tidss_dispc_regs.h:55:9-55:47: #define REG(r) (dispc_common_regmap[r ## _OFF])
• drivers/hwmon/smsc47b397.c:41:9-41:13: #define REG 0x2e /* The register to read/write */
• drivers/hwmon/smsc47m1.c:43:9-43:13: #define REG 0x2e /* The register to read/write */
• drivers/media/tuners/tda18250.c:504:10-504:19: #define REG 0
• drivers/mmc/host/vub300.c:221:9-221:39: #define REG(c) (0x01FFFF & (c->arg>>9))
• drivers/net/ipa/reg.h:29:9-30:42: #define REG(__NAME, __reg_id, __offset) \
• drivers/pinctrl/pinctrl-ocelot.c:1240:9-1240:65: #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
• drivers/regulator/rn5t618-regulator.c:25:9-41:2: #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \
• drivers/scsi/sym53c8xx_2/sym_defs.h:372:9-372:28: #define REG(r) REGJ (nc_, r)
• drivers/watchdog/it8712f_wdt.c:56:9-56:14: #define REG 0x2e /* The register to read/write */
• drivers/watchdog/it87_wdt.c:39:9-39:14: #define REG 0x2e
• fs/proc/base.c:143:9-144:45: #define REG(NAME, MODE, fops) \
• include/soc/mscc/ocelot.h:105:9-105:46: #define REG(reg, offset) [reg & REG_MASK] = offset