#if !defined (_vega10_ENUM_HEADER)
#define _vega10_ENUM_HEADER
#ifndef _DRIVER_BUILD
#ifndef GL_ZERO
#define GL__ZERO BLEND_ZERO
#define GL__ONE BLEND_ONE
#define GL__SRC_COLOR BLEND_SRC_COLOR
#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
#define GL__DST_COLOR BLEND_DST_COLOR
#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
#define GL__SRC_ALPHA BLEND_SRC_ALPHA
#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
#define GL__DST_ALPHA BLEND_DST_ALPHA
#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
#endif
#endif
#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
#define ENUMS_GDS_PERFCOUNT_SELECT_H
typedef enum GDS_PERFCOUNT_SELECT {
GDS_PERF_SEL_DS_ADDR_CONFL = 0,
GDS_PERF_SEL_DS_BANK_CONFL = 1,
GDS_PERF_SEL_WBUF_FLUSH = 2,
GDS_PERF_SEL_WR_COMP = 3,
GDS_PERF_SEL_WBUF_WR = 4,
GDS_PERF_SEL_RBUF_HIT = 5,
GDS_PERF_SEL_RBUF_MISS = 6,
GDS_PERF_SEL_SE0_SH0_NORET = 7,
GDS_PERF_SEL_SE0_SH0_RET = 8,
GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
GDS_PERF_SEL_SE0_SH1_NORET = 21,
GDS_PERF_SEL_SE0_SH1_RET = 22,
GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
GDS_PERF_SEL_SE1_SH0_NORET = 35,
GDS_PERF_SEL_SE1_SH0_RET = 36,
GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
GDS_PERF_SEL_SE1_SH1_NORET = 49,
GDS_PERF_SEL_SE1_SH1_RET = 50,
GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
GDS_PERF_SEL_SE2_SH0_NORET = 63,
GDS_PERF_SEL_SE2_SH0_RET = 64,
GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
GDS_PERF_SEL_SE2_SH1_NORET = 77,
GDS_PERF_SEL_SE2_SH1_RET = 78,
GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
GDS_PERF_SEL_SE3_SH0_NORET = 91,
GDS_PERF_SEL_SE3_SH0_RET = 92,
GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
GDS_PERF_SEL_SE3_SH1_NORET = 105,
GDS_PERF_SEL_SE3_SH1_RET = 106,
GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
GDS_PERF_SEL_GWS_RELEASED = 119,
GDS_PERF_SEL_GWS_BYPASS = 120,
} GDS_PERFCOUNT_SELECT;
#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
typedef enum MEM_PWR_FORCE_CTRL {
NO_FORCE_REQUEST = 0x00000000,
FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
FORCE_SHUT_DOWN_REQUEST = 0x00000003,
} MEM_PWR_FORCE_CTRL;
typedef enum MEM_PWR_FORCE_CTRL2 {
NO_FORCE_REQ = 0x00000000,
FORCE_LIGHT_SLEEP_REQ = 0x00000001,
} MEM_PWR_FORCE_CTRL2;
typedef enum MEM_PWR_DIS_CTRL {
ENABLE_MEM_PWR_CTRL = 0x00000000,
DISABLE_MEM_PWR_CTRL = 0x00000001,
} MEM_PWR_DIS_CTRL;
typedef enum MEM_PWR_SEL_CTRL {
DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
} MEM_PWR_SEL_CTRL;
typedef enum MEM_PWR_SEL_CTRL2 {
DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
} MEM_PWR_SEL_CTRL2;
typedef enum RowSize {
ADDR_CONFIG_1KB_ROW = 0x00000000,
ADDR_CONFIG_2KB_ROW = 0x00000001,
ADDR_CONFIG_4KB_ROW = 0x00000002,
} RowSize;
typedef enum SurfaceEndian {
ENDIAN_NONE = 0x00000000,
ENDIAN_8IN16 = 0x00000001,
ENDIAN_8IN32 = 0x00000002,
ENDIAN_8IN64 = 0x00000003,
} SurfaceEndian;
typedef enum ArrayMode {
ARRAY_LINEAR_GENERAL = 0x00000000,
ARRAY_LINEAR_ALIGNED = 0x00000001,
ARRAY_1D_TILED_THIN1 = 0x00000002,
ARRAY_1D_TILED_THICK = 0x00000003,
ARRAY_2D_TILED_THIN1 = 0x00000004,
ARRAY_PRT_TILED_THIN1 = 0x00000005,
ARRAY_PRT_2D_TILED_THIN1 = 0x00000006,
ARRAY_2D_TILED_THICK = 0x00000007,
ARRAY_2D_TILED_XTHICK = 0x00000008,
ARRAY_PRT_TILED_THICK = 0x00000009,
ARRAY_PRT_2D_TILED_THICK = 0x0000000a,
ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b,
ARRAY_3D_TILED_THIN1 = 0x0000000c,
ARRAY_3D_TILED_THICK = 0x0000000d,
ARRAY_3D_TILED_XTHICK = 0x0000000e,
ARRAY_PRT_3D_TILED_THICK = 0x0000000f,
} ArrayMode;
typedef enum NumPipes {
ADDR_CONFIG_1_PIPE = 0x00000000,
ADDR_CONFIG_2_PIPE = 0x00000001,
ADDR_CONFIG_4_PIPE = 0x00000002,
ADDR_CONFIG_8_PIPE = 0x00000003,
ADDR_CONFIG_16_PIPE = 0x00000004,
ADDR_CONFIG_32_PIPE = 0x00000005,
} NumPipes;
typedef enum NumBanksConfig {
ADDR_CONFIG_1_BANK = 0x00000000,
ADDR_CONFIG_2_BANK = 0x00000001,
ADDR_CONFIG_4_BANK = 0x00000002,
ADDR_CONFIG_8_BANK = 0x00000003,
ADDR_CONFIG_16_BANK = 0x00000004,
} NumBanksConfig;
typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,
ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,
} PipeInterleaveSize;
typedef enum BankInterleaveSize {
ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,
ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,
ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,
ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,
} BankInterleaveSize;
typedef enum NumShaderEngines {
ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,
ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,
ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,
ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,
} NumShaderEngines;
typedef enum NumRbPerShaderEngine {
ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,
ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,
ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,
} NumRbPerShaderEngine;
typedef enum NumGPUs {
ADDR_CONFIG_1_GPU = 0x00000000,
ADDR_CONFIG_2_GPU = 0x00000001,
ADDR_CONFIG_4_GPU = 0x00000002,
ADDR_CONFIG_8_GPU = 0x00000003,
} NumGPUs;
typedef enum NumMaxCompressedFragments {
ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,
ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,
ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,
ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,
} NumMaxCompressedFragments;
typedef enum ShaderEngineTileSize {
ADDR_CONFIG_SE_TILE_16 = 0x00000000,
ADDR_CONFIG_SE_TILE_32 = 0x00000001,
} ShaderEngineTileSize;
typedef enum MultiGPUTileSize {
ADDR_CONFIG_GPU_TILE_16 = 0x00000000,
ADDR_CONFIG_GPU_TILE_32 = 0x00000001,
ADDR_CONFIG_GPU_TILE_64 = 0x00000002,
ADDR_CONFIG_GPU_TILE_128 = 0x00000003,
} MultiGPUTileSize;
typedef enum NumLowerPipes {
ADDR_CONFIG_1_LOWER_PIPES = 0x00000000,
ADDR_CONFIG_2_LOWER_PIPES = 0x00000001,
} NumLowerPipes;
typedef enum ColorTransform {
DCC_CT_AUTO = 0x00000000,
DCC_CT_NONE = 0x00000001,
ABGR_TO_A_BG_G_RB = 0x00000002,
BGRA_TO_BG_G_RB_A = 0x00000003,
} ColorTransform;
typedef enum CompareRef {
REF_NEVER = 0x00000000,
REF_LESS = 0x00000001,
REF_EQUAL = 0x00000002,
REF_LEQUAL = 0x00000003,
REF_GREATER = 0x00000004,
REF_NOTEQUAL = 0x00000005,
REF_GEQUAL = 0x00000006,
REF_ALWAYS = 0x00000007,
} CompareRef;
typedef enum ReadSize {
READ_256_BITS = 0x00000000,
READ_512_BITS = 0x00000001,
} ReadSize;
typedef enum DepthFormat {
DEPTH_INVALID = 0x00000000,
DEPTH_16 = 0x00000001,
DEPTH_X8_24 = 0x00000002,
DEPTH_8_24 = 0x00000003,
DEPTH_X8_24_FLOAT = 0x00000004,
DEPTH_8_24_FLOAT = 0x00000005,
DEPTH_32_FLOAT = 0x00000006,
DEPTH_X24_8_32_FLOAT = 0x00000007,
} DepthFormat;
typedef enum ZFormat {
Z_INVALID = 0x00000000,
Z_16 = 0x00000001,
Z_24 = 0x00000002,
Z_32_FLOAT = 0x00000003,
} ZFormat;
typedef enum StencilFormat {
STENCIL_INVALID = 0x00000000,
STENCIL_8 = 0x00000001,
} StencilFormat;
typedef enum CmaskMode {
CMASK_CLEAR_NONE = 0x00000000,
CMASK_CLEAR_ONE = 0x00000001,
CMASK_CLEAR_ALL = 0x00000002,
CMASK_ANY_EXPANDED = 0x00000003,
CMASK_ALPHA0_FRAG1 = 0x00000004,
CMASK_ALPHA0_FRAG2 = 0x00000005,
CMASK_ALPHA0_FRAG4 = 0x00000006,
CMASK_ALPHA0_FRAGS = 0x00000007,
CMASK_ALPHA1_FRAG1 = 0x00000008,
CMASK_ALPHA1_FRAG2 = 0x00000009,
CMASK_ALPHA1_FRAG4 = 0x0000000a,
CMASK_ALPHA1_FRAGS = 0x0000000b,
CMASK_ALPHAX_FRAG1 = 0x0000000c,
CMASK_ALPHAX_FRAG2 = 0x0000000d,
CMASK_ALPHAX_FRAG4 = 0x0000000e,
CMASK_ALPHAX_FRAGS = 0x0000000f,
} CmaskMode;
typedef enum QuadExportFormat {
EXPORT_UNUSED = 0x00000000,
EXPORT_32_R = 0x00000001,
EXPORT_32_GR = 0x00000002,
EXPORT_32_AR = 0x00000003,
EXPORT_FP16_ABGR = 0x00000004,
EXPORT_UNSIGNED16_ABGR = 0x00000005,
EXPORT_SIGNED16_ABGR = 0x00000006,
EXPORT_32_ABGR = 0x00000007,
EXPORT_32BPP_8PIX = 0x00000008,
EXPORT_16_16_UNSIGNED_8PIX = 0x00000009,
EXPORT_16_16_SIGNED_8PIX = 0x0000000a,
EXPORT_16_16_FLOAT_8PIX = 0x0000000b,
} QuadExportFormat;
typedef enum QuadExportFormatOld {
EXPORT_4P_32BPC_ABGR = 0x00000000,
EXPORT_4P_16BPC_ABGR = 0x00000001,
EXPORT_4P_32BPC_GR = 0x00000002,
EXPORT_4P_32BPC_AR = 0x00000003,
EXPORT_2P_32BPC_ABGR = 0x00000004,
EXPORT_8P_32BPC_R = 0x00000005,
} QuadExportFormatOld;
typedef enum ColorFormat {
COLOR_INVALID = 0x00000000,
COLOR_8 = 0x00000001,
COLOR_16 = 0x00000002,
COLOR_8_8 = 0x00000003,
COLOR_32 = 0x00000004,
COLOR_16_16 = 0x00000005,
COLOR_10_11_11 = 0x00000006,
COLOR_11_11_10 = 0x00000007,
COLOR_10_10_10_2 = 0x00000008,
COLOR_2_10_10_10 = 0x00000009,
COLOR_8_8_8_8 = 0x0000000a,
COLOR_32_32 = 0x0000000b,
COLOR_16_16_16_16 = 0x0000000c,
COLOR_RESERVED_13 = 0x0000000d,
COLOR_32_32_32_32 = 0x0000000e,
COLOR_RESERVED_15 = 0x0000000f,
COLOR_5_6_5 = 0x00000010,
COLOR_1_5_5_5 = 0x00000011,
COLOR_5_5_5_1 = 0x00000012,
COLOR_4_4_4_4 = 0x00000013,
COLOR_8_24 = 0x00000014,
COLOR_24_8 = 0x00000015,
COLOR_X24_8_32_FLOAT = 0x00000016,
COLOR_RESERVED_23 = 0x00000017,
COLOR_RESERVED_24 = 0x00000018,
COLOR_RESERVED_25 = 0x00000019,
COLOR_RESERVED_26 = 0x0000001a,
COLOR_RESERVED_27 = 0x0000001b,
COLOR_RESERVED_28 = 0x0000001c,
COLOR_RESERVED_29 = 0x0000001d,
COLOR_RESERVED_30 = 0x0000001e,
COLOR_2_10_10_10_6E4 = 0x0000001f,
} ColorFormat;
typedef enum SurfaceFormat {
FMT_INVALID = 0x00000000,
FMT_8 = 0x00000001,
FMT_16 = 0x00000002,
FMT_8_8 = 0x00000003,
FMT_32 = 0x00000004,
FMT_16_16 = 0x00000005,
FMT_10_11_11 = 0x00000006,
FMT_11_11_10 = 0x00000007,
FMT_10_10_10_2 = 0x00000008,
FMT_2_10_10_10 = 0x00000009,
FMT_8_8_8_8 = 0x0000000a,
FMT_32_32 = 0x0000000b,
FMT_16_16_16_16 = 0x0000000c,
FMT_32_32_32 = 0x0000000d,
FMT_32_32_32_32 = 0x0000000e,
FMT_RESERVED_4 = 0x0000000f,
FMT_5_6_5 = 0x00000010,
FMT_1_5_5_5 = 0x00000011,
FMT_5_5_5_1 = 0x00000012,
FMT_4_4_4_4 = 0x00000013,
FMT_8_24 = 0x00000014,
FMT_24_8 = 0x00000015,
FMT_X24_8_32_FLOAT = 0x00000016,
FMT_RESERVED_33 = 0x00000017,
FMT_11_11_10_FLOAT = 0x00000018,
FMT_16_FLOAT = 0x00000019,
FMT_32_FLOAT = 0x0000001a,
FMT_16_16_FLOAT = 0x0000001b,
FMT_8_24_FLOAT = 0x0000001c,
FMT_24_8_FLOAT = 0x0000001d,
FMT_32_32_FLOAT = 0x0000001e,
FMT_10_11_11_FLOAT = 0x0000001f,
FMT_16_16_16_16_FLOAT = 0x00000020,
FMT_3_3_2 = 0x00000021,
FMT_6_5_5 = 0x00000022,
FMT_32_32_32_32_FLOAT = 0x00000023,
FMT_RESERVED_36 = 0x00000024,
FMT_1 = 0x00000025,
FMT_1_REVERSED = 0x00000026,
FMT_GB_GR = 0x00000027,
FMT_BG_RG = 0x00000028,
FMT_32_AS_8 = 0x00000029,
FMT_32_AS_8_8 = 0x0000002a,
FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
FMT_8_8_8 = 0x0000002c,
FMT_16_16_16 = 0x0000002d,
FMT_16_16_16_FLOAT = 0x0000002e,
FMT_4_4 = 0x0000002f,
FMT_32_32_32_FLOAT = 0x00000030,
FMT_BC1 = 0x00000031,
FMT_BC2 = 0x00000032,
FMT_BC3 = 0x00000033,
FMT_BC4 = 0x00000034,
FMT_BC5 = 0x00000035,
FMT_BC6 = 0x00000036,
FMT_BC7 = 0x00000037,
FMT_32_AS_32_32_32_32 = 0x00000038,
FMT_APC3 = 0x00000039,
FMT_APC4 = 0x0000003a,
FMT_APC5 = 0x0000003b,
FMT_APC6 = 0x0000003c,
FMT_APC7 = 0x0000003d,
FMT_CTX1 = 0x0000003e,
FMT_RESERVED_63 = 0x0000003f,
} SurfaceFormat;
typedef enum BUF_DATA_FORMAT {
BUF_DATA_FORMAT_INVALID = 0x00000000,
BUF_DATA_FORMAT_8 = 0x00000001,
BUF_DATA_FORMAT_16 = 0x00000002,
BUF_DATA_FORMAT_8_8 = 0x00000003,
BUF_DATA_FORMAT_32 = 0x00000004,
BUF_DATA_FORMAT_16_16 = 0x00000005,
BUF_DATA_FORMAT_10_11_11 = 0x00000006,
BUF_DATA_FORMAT_11_11_10 = 0x00000007,
BUF_DATA_FORMAT_10_10_10_2 = 0x00000008,
BUF_DATA_FORMAT_2_10_10_10 = 0x00000009,
BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a,
BUF_DATA_FORMAT_32_32 = 0x0000000b,
BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c,
BUF_DATA_FORMAT_32_32_32 = 0x0000000d,
BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e,
BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f,
} BUF_DATA_FORMAT;
typedef enum IMG_DATA_FORMAT {
IMG_DATA_FORMAT_INVALID = 0x00000000,
IMG_DATA_FORMAT_8 = 0x00000001,
IMG_DATA_FORMAT_16 = 0x00000002,
IMG_DATA_FORMAT_8_8 = 0x00000003,
IMG_DATA_FORMAT_32 = 0x00000004,
IMG_DATA_FORMAT_16_16 = 0x00000005,
IMG_DATA_FORMAT_10_11_11 = 0x00000006,
IMG_DATA_FORMAT_11_11_10 = 0x00000007,
IMG_DATA_FORMAT_10_10_10_2 = 0x00000008,
IMG_DATA_FORMAT_2_10_10_10 = 0x00000009,
IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a,
IMG_DATA_FORMAT_32_32 = 0x0000000b,
IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c,
IMG_DATA_FORMAT_32_32_32 = 0x0000000d,
IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e,
IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f,
IMG_DATA_FORMAT_5_6_5 = 0x00000010,
IMG_DATA_FORMAT_1_5_5_5 = 0x00000011,
IMG_DATA_FORMAT_5_5_5_1 = 0x00000012,
IMG_DATA_FORMAT_4_4_4_4 = 0x00000013,
IMG_DATA_FORMAT_8_24 = 0x00000014,
IMG_DATA_FORMAT_24_8 = 0x00000015,
IMG_DATA_FORMAT_X24_8_32 = 0x00000016,
IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x00000017,
IMG_DATA_FORMAT_ETC2_RGB = 0x00000018,
IMG_DATA_FORMAT_ETC2_RGBA = 0x00000019,
IMG_DATA_FORMAT_ETC2_R = 0x0000001a,
IMG_DATA_FORMAT_ETC2_RG = 0x0000001b,
IMG_DATA_FORMAT_ETC2_RGBA1 = 0x0000001c,
IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d,
IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e,
IMG_DATA_FORMAT_6E4 = 0x0000001f,
IMG_DATA_FORMAT_GB_GR = 0x00000020,
IMG_DATA_FORMAT_BG_RG = 0x00000021,
IMG_DATA_FORMAT_5_9_9_9 = 0x00000022,
IMG_DATA_FORMAT_BC1 = 0x00000023,
IMG_DATA_FORMAT_BC2 = 0x00000024,
IMG_DATA_FORMAT_BC3 = 0x00000025,
IMG_DATA_FORMAT_BC4 = 0x00000026,
IMG_DATA_FORMAT_BC5 = 0x00000027,
IMG_DATA_FORMAT_BC6 = 0x00000028,
IMG_DATA_FORMAT_BC7 = 0x00000029,
IMG_DATA_FORMAT_16_AS_32_32 = 0x0000002a,
IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x0000002b,
IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x0000002c,
IMG_DATA_FORMAT_FMASK = 0x0000002d,
IMG_DATA_FORMAT_ASTC_2D_LDR = 0x0000002e,
IMG_DATA_FORMAT_ASTC_2D_HDR = 0x0000002f,
IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 0x00000030,
IMG_DATA_FORMAT_ASTC_3D_LDR = 0x00000031,
IMG_DATA_FORMAT_ASTC_3D_HDR = 0x00000032,
IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 0x00000033,
IMG_DATA_FORMAT_N_IN_16 = 0x00000034,
IMG_DATA_FORMAT_N_IN_16_16 = 0x00000035,
IMG_DATA_FORMAT_N_IN_16_16_16_16 = 0x00000036,
IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 0x00000037,
IMG_DATA_FORMAT_RESERVED_56 = 0x00000038,
IMG_DATA_FORMAT_4_4 = 0x00000039,
IMG_DATA_FORMAT_6_5_5 = 0x0000003a,
IMG_DATA_FORMAT_RESERVED_59 = 0x0000003b,
IMG_DATA_FORMAT_RESERVED_60 = 0x0000003c,
IMG_DATA_FORMAT_8_AS_32 = 0x0000003d,
IMG_DATA_FORMAT_8_AS_32_32 = 0x0000003e,
IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f,
} IMG_DATA_FORMAT;
typedef enum BUF_NUM_FORMAT {
BUF_NUM_FORMAT_UNORM = 0x00000000,
BUF_NUM_FORMAT_SNORM = 0x00000001,
BUF_NUM_FORMAT_USCALED = 0x00000002,
BUF_NUM_FORMAT_SSCALED = 0x00000003,
BUF_NUM_FORMAT_UINT = 0x00000004,
BUF_NUM_FORMAT_SINT = 0x00000005,
BUF_NUM_FORMAT_UNORM_UINT = 0x00000006,
BUF_NUM_FORMAT_FLOAT = 0x00000007,
} BUF_NUM_FORMAT;
typedef enum IMG_NUM_FORMAT {
IMG_NUM_FORMAT_UNORM = 0x00000000,
IMG_NUM_FORMAT_SNORM = 0x00000001,
IMG_NUM_FORMAT_USCALED = 0x00000002,
IMG_NUM_FORMAT_SSCALED = 0x00000003,
IMG_NUM_FORMAT_UINT = 0x00000004,
IMG_NUM_FORMAT_SINT = 0x00000005,
IMG_NUM_FORMAT_UNORM_UINT = 0x00000006,
IMG_NUM_FORMAT_FLOAT = 0x00000007,
IMG_NUM_FORMAT_RESERVED_8 = 0x00000008,
IMG_NUM_FORMAT_SRGB = 0x00000009,
IMG_NUM_FORMAT_RESERVED_10 = 0x0000000a,
IMG_NUM_FORMAT_RESERVED_11 = 0x0000000b,
IMG_NUM_FORMAT_RESERVED_12 = 0x0000000c,
IMG_NUM_FORMAT_RESERVED_13 = 0x0000000d,
IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e,
IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f,
} IMG_NUM_FORMAT;
typedef enum IMG_NUM_FORMAT_FMASK {
IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000,
IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001,
IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002,
IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003,
IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004,
IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005,
IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006,
IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007,
IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008,
IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009,
IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a,
IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b,
IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c,
IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d,
IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e,
IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f,
} IMG_NUM_FORMAT_FMASK;
typedef enum IMG_NUM_FORMAT_N_IN_16 {
IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000,
IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001,
IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002,
IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003,
IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004,
IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005,
IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006,
IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007,
IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008,
IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009,
IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a,
IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b,
IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c,
IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d,
IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e,
IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f,
} IMG_NUM_FORMAT_N_IN_16;
typedef enum IMG_NUM_FORMAT_ASTC_2D {
IMG_NUM_FORMAT_ASTC_2D_4x4 = 0x00000000,
IMG_NUM_FORMAT_ASTC_2D_5x4 = 0x00000001,
IMG_NUM_FORMAT_ASTC_2D_5x5 = 0x00000002,
IMG_NUM_FORMAT_ASTC_2D_6x5 = 0x00000003,
IMG_NUM_FORMAT_ASTC_2D_6x6 = 0x00000004,
IMG_NUM_FORMAT_ASTC_2D_8x5 = 0x00000005,
IMG_NUM_FORMAT_ASTC_2D_8x6 = 0x00000006,
IMG_NUM_FORMAT_ASTC_2D_8x8 = 0x00000007,
IMG_NUM_FORMAT_ASTC_2D_10x5 = 0x00000008,
IMG_NUM_FORMAT_ASTC_2D_10x6 = 0x00000009,
IMG_NUM_FORMAT_ASTC_2D_10x8 = 0x0000000a,
IMG_NUM_FORMAT_ASTC_2D_10x10 = 0x0000000b,
IMG_NUM_FORMAT_ASTC_2D_12x10 = 0x0000000c,
IMG_NUM_FORMAT_ASTC_2D_12x12 = 0x0000000d,
IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 0x0000000e,
IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 0x0000000f,
} IMG_NUM_FORMAT_ASTC_2D;
typedef enum IMG_NUM_FORMAT_ASTC_3D {
IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0x00000000,
IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 0x00000001,
IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 0x00000002,
IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 0x00000003,
IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 0x00000004,
IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 0x00000005,
IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 0x00000006,
IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 0x00000007,
IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 0x00000008,
IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 0x00000009,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 0x0000000a,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 0x0000000b,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 0x0000000c,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 0x0000000d,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 0x0000000e,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 0x0000000f,
} IMG_NUM_FORMAT_ASTC_3D;
typedef enum TileType {
ARRAY_COLOR_TILE = 0x00000000,
ARRAY_DEPTH_TILE = 0x00000001,
} TileType;
typedef enum NonDispTilingOrder {
ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000,
ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001,
} NonDispTilingOrder;
typedef enum MicroTileMode {
ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000,
ADDR_SURF_THIN_MICRO_TILING = 0x00000001,
ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002,
ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003,
ADDR_SURF_THICK_MICRO_TILING = 0x00000004,
} MicroTileMode;
typedef enum TileSplit {
ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
} TileSplit;
typedef enum SampleSplit {
ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000,
ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001,
ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002,
ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003,
} SampleSplit;
typedef enum PipeConfig {
ADDR_SURF_P2 = 0x00000000,
ADDR_SURF_P2_RESERVED0 = 0x00000001,
ADDR_SURF_P2_RESERVED1 = 0x00000002,
ADDR_SURF_P2_RESERVED2 = 0x00000003,
ADDR_SURF_P4_8x16 = 0x00000004,
ADDR_SURF_P4_16x16 = 0x00000005,
ADDR_SURF_P4_16x32 = 0x00000006,
ADDR_SURF_P4_32x32 = 0x00000007,
ADDR_SURF_P8_16x16_8x16 = 0x00000008,
ADDR_SURF_P8_16x32_8x16 = 0x00000009,
ADDR_SURF_P8_32x32_8x16 = 0x0000000a,
ADDR_SURF_P8_16x32_16x16 = 0x0000000b,
ADDR_SURF_P8_32x32_16x16 = 0x0000000c,
ADDR_SURF_P8_32x32_16x32 = 0x0000000d,
ADDR_SURF_P8_32x64_32x32 = 0x0000000e,
ADDR_SURF_P8_RESERVED0 = 0x0000000f,
ADDR_SURF_P16_32x32_8x16 = 0x00000010,
ADDR_SURF_P16_32x32_16x16 = 0x00000011,
} PipeConfig;
typedef enum SeEnable {
ADDR_CONFIG_DISABLE_SE = 0x00000000,
ADDR_CONFIG_ENABLE_SE = 0x00000001,
} SeEnable;
typedef enum NumBanks {
ADDR_SURF_2_BANK = 0x00000000,
ADDR_SURF_4_BANK = 0x00000001,
ADDR_SURF_8_BANK = 0x00000002,
ADDR_SURF_16_BANK = 0x00000003,
} NumBanks;
typedef enum BankWidth {
ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
} BankWidth;
typedef enum BankHeight {
ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
} BankHeight;
typedef enum BankWidthHeight {
ADDR_SURF_BANK_WH_1 = 0x00000000,
ADDR_SURF_BANK_WH_2 = 0x00000001,
ADDR_SURF_BANK_WH_4 = 0x00000002,
ADDR_SURF_BANK_WH_8 = 0x00000003,
} BankWidthHeight;
typedef enum MacroTileAspect {
ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
} MacroTileAspect;
typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL = 0x00000000,
GATCL1_TYPE_SHOOTDOWN = 0x00000001,
GATCL1_TYPE_BYPASS = 0x00000002,
} GATCL1RequestType;
typedef enum UTCL1RequestType {
UTCL1_TYPE_NORMAL = 0x00000000,
UTCL1_TYPE_SHOOTDOWN = 0x00000001,
UTCL1_TYPE_BYPASS = 0x00000002,
} UTCL1RequestType;
typedef enum UTCL1FaultType {
UTCL1_XNACK_SUCCESS = 0x00000000,
UTCL1_XNACK_RETRY = 0x00000001,
UTCL1_XNACK_PRT = 0x00000002,
UTCL1_XNACK_NO_RETRY = 0x00000003,
} UTCL1FaultType;
typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU = 0x00000000,
TCC_CACHE_POLICY_STREAM = 0x00000001,
} TCC_CACHE_POLICIES;
typedef enum MTYPE {
MTYPE_NC = 0x00000000,
MTYPE_WC = 0x00000001,
MTYPE_RW = 0x00000001,
MTYPE_CC = 0x00000002,
MTYPE_UC = 0x00000003,
} MTYPE;
typedef enum RMI_CID {
RMI_CID_CC = 0x00000000,
RMI_CID_FC = 0x00000001,
RMI_CID_CM = 0x00000002,
RMI_CID_DC = 0x00000003,
RMI_CID_Z = 0x00000004,
RMI_CID_S = 0x00000005,
RMI_CID_TILE = 0x00000006,
RMI_CID_ZPCPSD = 0x00000007,
} RMI_CID;
typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
PERFMON_COUNTER_MODE_MAX = 0x00000002,
PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
} PERFMON_COUNTER_MODE;
typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF = 0x00000000,
PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
} PERFMON_SPM_MODE;
typedef enum SurfaceTiling {
ARRAY_LINEAR = 0x00000000,
ARRAY_TILED = 0x00000001,
} SurfaceTiling;
typedef enum SurfaceArray {
ARRAY_1D = 0x00000000,
ARRAY_2D = 0x00000001,
ARRAY_3D = 0x00000002,
ARRAY_3D_SLICE = 0x00000003,
} SurfaceArray;
typedef enum ColorArray {
ARRAY_2D_ALT_COLOR = 0x00000000,
ARRAY_2D_COLOR = 0x00000001,
ARRAY_3D_SLICE_COLOR = 0x00000003,
} ColorArray;
typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH = 0x00000000,
ARRAY_2D_DEPTH = 0x00000001,
} DepthArray;
typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU = 0x00000004,
} ENUM_NUM_SIMD_PER_CU;
typedef enum DSM_ENABLE_ERROR_INJECT {
DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
DSM_ENABLE_ERROR_INJECT_DOUBLE = 0x00000002,
DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 0x00000003,
} DSM_ENABLE_ERROR_INJECT;
typedef enum DSM_SELECT_INJECT_DELAY {
DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
} DSM_SELECT_INJECT_DELAY;
typedef enum SWIZZLE_TYPE_ENUM {
SW_Z = 0x00000000,
SW_S = 0x00000001,
SW_D = 0x00000002,
SW_R = 0x00000003,
SW_L = 0x00000004,
} SWIZZLE_TYPE_ENUM;
typedef enum TC_MICRO_TILE_MODE {
MICRO_TILE_MODE_LINEAR = 0x00000000,
MICRO_TILE_MODE_ROTATED = 0x00000001,
MICRO_TILE_MODE_STD_2D = 0x00000002,
MICRO_TILE_MODE_STD_3D = 0x00000003,
MICRO_TILE_MODE_DISPLAY_2D = 0x00000004,
MICRO_TILE_MODE_DISPLAY_3D = 0x00000005,
MICRO_TILE_MODE_Z_2D = 0x00000006,
MICRO_TILE_MODE_Z_3D = 0x00000007,
} TC_MICRO_TILE_MODE;
typedef enum SWIZZLE_MODE_ENUM {
SW_LINEAR = 0x00000000,
SW_256B_S = 0x00000001,
SW_256B_D = 0x00000002,
SW_256B_R = 0x00000003,
SW_4KB_Z = 0x00000004,
SW_4KB_S = 0x00000005,
SW_4KB_D = 0x00000006,
SW_4KB_R = 0x00000007,
SW_64KB_Z = 0x00000008,
SW_64KB_S = 0x00000009,
SW_64KB_D = 0x0000000a,
SW_64KB_R = 0x0000000b,
SW_VAR_Z = 0x0000000c,
SW_VAR_S = 0x0000000d,
SW_VAR_D = 0x0000000e,
SW_VAR_R = 0x0000000f,
SW_RESERVED_16 = 0x00000010,
SW_RESERVED_17 = 0x00000011,
SW_RESERVED_18 = 0x00000012,
SW_RESERVED_19 = 0x00000013,
SW_4KB_Z_X = 0x00000014,
SW_4KB_S_X = 0x00000015,
SW_4KB_D_X = 0x00000016,
SW_4KB_R_X = 0x00000017,
SW_64KB_Z_X = 0x00000018,
SW_64KB_S_X = 0x00000019,
SW_64KB_D_X = 0x0000001a,
SW_64KB_R_X = 0x0000001b,
SW_VAR_Z_X = 0x0000001c,
SW_VAR_S_X = 0x0000001d,
SW_VAR_D_X = 0x0000001e,
SW_VAR_R_X = 0x0000001f,
SW_RESERVED_12 = 0x00000020,
SW_RESERVED_13 = 0x00000021,
SW_RESERVED_14 = 0x00000022,
SW_RESERVED_15 = 0x00000023,
} SWIZZLE_MODE_ENUM;
typedef enum PipeTiling {
CONFIG_1_PIPE = 0x00000000,
CONFIG_2_PIPE = 0x00000001,
CONFIG_4_PIPE = 0x00000002,
CONFIG_8_PIPE = 0x00000003,
} PipeTiling;
typedef enum BankTiling {
CONFIG_4_BANK = 0x00000000,
CONFIG_8_BANK = 0x00000001,
} BankTiling;
typedef enum GroupInterleave {
CONFIG_256B_GROUP = 0x00000000,
CONFIG_512B_GROUP = 0x00000001,
} GroupInterleave;
typedef enum RowTiling {
CONFIG_1KB_ROW = 0x00000000,
CONFIG_2KB_ROW = 0x00000001,
CONFIG_4KB_ROW = 0x00000002,
CONFIG_8KB_ROW = 0x00000003,
CONFIG_1KB_ROW_OPT = 0x00000004,
CONFIG_2KB_ROW_OPT = 0x00000005,
CONFIG_4KB_ROW_OPT = 0x00000006,
CONFIG_8KB_ROW_OPT = 0x00000007,
} RowTiling;
typedef enum BankSwapBytes {
CONFIG_128B_SWAPS = 0x00000000,
CONFIG_256B_SWAPS = 0x00000001,
CONFIG_512B_SWAPS = 0x00000002,
CONFIG_1KB_SWAPS = 0x00000003,
} BankSwapBytes;
typedef enum SampleSplitBytes {
CONFIG_1KB_SPLIT = 0x00000000,
CONFIG_2KB_SPLIT = 0x00000001,
CONFIG_4KB_SPLIT = 0x00000002,
CONFIG_8KB_SPLIT = 0x00000003,
} SampleSplitBytes;
typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
typedef enum BLNDV_CONTROL_BLND_MODE {
BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001,
BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
} BLNDV_CONTROL_BLND_MODE;
typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003,
} BLNDV_CONTROL_BLND_STEREO_TYPE;
typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000,
BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001,
} BLNDV_CONTROL_BLND_STEREO_POLARITY;
typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000,
BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001,
} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003,
} BLNDV_CONTROL_BLND_ALPHA_MODE;
typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001,
} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
typedef enum BLNDV_SM_CONTROL2_SM_MODE {
BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000,
BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
} BLNDV_SM_CONTROL2_SM_MODE;
typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
typedef enum BLNDV_CONTROL2_PTI_ENABLE {
BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x00000000,
BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x00000001,
} BLNDV_CONTROL2_PTI_ENABLE;
typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000,
BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001,
} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
typedef enum LBV_PIXEL_DEPTH {
PIXEL_DEPTH_30BPP = 0x00000000,
PIXEL_DEPTH_24BPP = 0x00000001,
PIXEL_DEPTH_18BPP = 0x00000002,
PIXEL_DEPTH_38BPP = 0x00000003,
} LBV_PIXEL_DEPTH;
typedef enum LBV_PIXEL_EXPAN_MODE {
PIXEL_EXPAN_MODE_ZERO_EXP = 0x00000000,
PIXEL_EXPAN_MODE_DYN_EXP = 0x00000001,
} LBV_PIXEL_EXPAN_MODE;
typedef enum LBV_INTERLEAVE_EN {
INTERLEAVE_DIS = 0x00000000,
INTERLEAVE_EN = 0x00000001,
} LBV_INTERLEAVE_EN;
typedef enum LBV_PIXEL_REDUCE_MODE {
PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
} LBV_PIXEL_REDUCE_MODE;
typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
} LBV_DYNAMIC_PIXEL_DEPTH;
typedef enum LBV_DITHER_EN {
DITHER_DIS = 0x00000000,
DITHER_EN = 0x00000001,
} LBV_DITHER_EN;
typedef enum LBV_DOWNSCALE_PREFETCH_EN {
DOWNSCALE_PREFETCH_DIS = 0x00000000,
DOWNSCALE_PREFETCH_EN = 0x00000001,
} LBV_DOWNSCALE_PREFETCH_EN;
typedef enum LBV_MEMORY_CONFIG {
MEMORY_CONFIG_0 = 0x00000000,
MEMORY_CONFIG_1 = 0x00000001,
MEMORY_CONFIG_2 = 0x00000002,
MEMORY_CONFIG_3 = 0x00000003,
} LBV_MEMORY_CONFIG;
typedef enum LBV_SYNC_RESET_SEL2 {
SYNC_RESET_SEL2_VBLANK = 0x00000000,
SYNC_RESET_SEL2_VSYNC = 0x00000001,
} LBV_SYNC_RESET_SEL2;
typedef enum LBV_SYNC_DURATION {
SYNC_DURATION_16 = 0x00000000,
SYNC_DURATION_32 = 0x00000001,
SYNC_DURATION_64 = 0x00000002,
SYNC_DURATION_128 = 0x00000003,
} LBV_SYNC_DURATION;
typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x00000001,
} CRTC_CONTROL_CRTC_START_POINT_CNTL;
typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x00000001,
} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x00000002,
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000,
CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001,
} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x00000000,
CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x00000001,
} CRTC_CONTROL_CRTC_SOF_PULL_EN;
typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x00000000,
CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x00000001,
} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001,
} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001,
} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x00000000,
CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x00000001,
} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x00000000,
CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x00000001,
} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 0x00000005,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 0x00000006,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x00000007,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x00000008,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x00000009,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0x0000000a,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 0x0000000d,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 0x0000000e,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x00000010,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x00000011,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x00000012,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x00000013,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 0x00000014,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 0x00000015,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 0x00000005,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x00000006,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 0x00000007,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x00000000,
CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x00000001,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 0x00000005,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 0x00000006,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x00000007,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x00000008,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x00000009,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0x0000000a,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 0x0000000d,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 0x0000000e,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x00000010,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x00000011,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x00000012,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x00000013,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 0x00000014,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 0x00000015,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 0x00000005,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x00000006,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 0x00000007,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x00000000,
CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x00000001,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000001,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000002,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000003,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000004,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x00000005,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x00000006,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x00000007,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x00000008,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 0x00000009,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 0x0000000a,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x0000000b,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x0000000c,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x0000000d,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x0000000e,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x0000000f,
} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x00000000,
CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x00000001,
} CRTC_CONTROL_CRTC_MASTER_EN;
typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x00000000,
CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x00000001,
} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x00000000,
CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x00000001,
} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0x00000000,
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 0x00000001,
} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 0x00000001,
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 0x00000002,
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0x00000000,
CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 0x00000001,
} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0x00000000,
CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 0x00000001,
} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0x00000000,
CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 0x00000001,
} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x00000000,
CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x00000001,
} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000,
CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x00000001,
} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 0x00000001,
} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 0x00000001,
} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0x00000000,
CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 0x00000001,
} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x00000000,
CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x00000001,
} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x00000000,
CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x00000001,
} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0x00000000,
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 0x00000001,
} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0x00000000,
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 0x00000001,
} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE;
typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0x00000000,
CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 0x00000001,
} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0x00000000,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 0x00000001,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0x00000000,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 0x00000001,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 0x00000002,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 0x00000003,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 0x00000004,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 0x00000005,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 0x00000006,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 0x00000007,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0x00000000,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 0x00000001,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0x00000000,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 0x00000001,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 0x00000002,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 0x00000003,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x00000000,
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x00000001,
} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x00000000,
MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x00000001,
MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x00000002,
MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x00000003,
} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 0x00000001,
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 0x00000002,
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0x00000000,
CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 0x00000001,
CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 0x00000002,
} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000,
CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x00000001,
} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 0x00000001,
} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 0x00000001,
} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x00000000,
CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x00000001,
} CRTC_CRC_CNTL_CRTC_CRC_EN;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x00000000,
CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x00000001,
} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x00000000,
CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x00000001,
CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x00000000,
CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x00000000,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x00000001,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x00000002,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x00000003,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x00000004,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x00000005,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x00000006,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x00000007,
} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x00000000,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x00000001,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x00000002,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x00000003,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x00000004,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x00000005,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x00000006,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x00000007,
} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0x00000000,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 0x00000001,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 0x00000002,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 0x00000003,
} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0x00000000,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 0x00000001,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 0x00000002,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 0x00000003,
} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0x00000000,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 0x00000001,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 0x00000002,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 0x00000003,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 0x00000004,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 0x00000005,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 0x00000006,
CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 0x00000007,
} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0x00000000,
CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 0x00000001,
} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0x00000000,
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 0x00000001,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0x00000000,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 0x00000001,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
typedef enum CRTC_V_SYNC_A_POL {
CRTC_V_SYNC_A_POL_HIGH = 0x00000000,
CRTC_V_SYNC_A_POL_LOW = 0x00000001,
} CRTC_V_SYNC_A_POL;
typedef enum CRTC_H_SYNC_A_POL {
CRTC_H_SYNC_A_POL_HIGH = 0x00000000,
CRTC_H_SYNC_A_POL_LOW = 0x00000001,
} CRTC_H_SYNC_A_POL;
typedef enum CRTC_HORZ_REPETITION_COUNT {
CRTC_HORZ_REPETITION_COUNT_0 = 0x00000000,
CRTC_HORZ_REPETITION_COUNT_1 = 0x00000001,
CRTC_HORZ_REPETITION_COUNT_2 = 0x00000002,
CRTC_HORZ_REPETITION_COUNT_3 = 0x00000003,
CRTC_HORZ_REPETITION_COUNT_4 = 0x00000004,
CRTC_HORZ_REPETITION_COUNT_5 = 0x00000005,
CRTC_HORZ_REPETITION_COUNT_6 = 0x00000006,
CRTC_HORZ_REPETITION_COUNT_7 = 0x00000007,
CRTC_HORZ_REPETITION_COUNT_8 = 0x00000008,
CRTC_HORZ_REPETITION_COUNT_9 = 0x00000009,
CRTC_HORZ_REPETITION_COUNT_10 = 0x0000000a,
CRTC_HORZ_REPETITION_COUNT_11 = 0x0000000b,
CRTC_HORZ_REPETITION_COUNT_12 = 0x0000000c,
CRTC_HORZ_REPETITION_COUNT_13 = 0x0000000d,
CRTC_HORZ_REPETITION_COUNT_14 = 0x0000000e,
CRTC_HORZ_REPETITION_COUNT_15 = 0x0000000f,
} CRTC_HORZ_REPETITION_COUNT;
typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0x00000000,
CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 0x00000001,
CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 0x00000002,
CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 0x00000003,
} CRTC_DRR_MODE_DBUF_UPDATE_MODE;
typedef enum FMT_CONTROL_PIXEL_ENCODING {
FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
} FMT_CONTROL_PIXEL_ENCODING;
typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
} FMT_CONTROL_SUBSAMPLING_MODE;
typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
} FMT_CONTROL_SUBSAMPLING_ORDER;
typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0x00000000,
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 0x00000001,
} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
} FMT_CLAMP_CNTL_COLOR_FORMAT;
typedef enum FMT_CRC_CNTL_CONT_EN {
FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x00000000,
FMT_CRC_CNTL_CONT_EN_CONT = 0x00000001,
} FMT_CRC_CNTL_CONT_EN;
typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x00000000,
FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x00000001,
} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x00000000,
FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x00000001,
} FMT_CRC_CNTL_ONLY_BLANKB;
typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x00000000,
FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x00000001,
} FMT_CRC_CNTL_PSR_MODE_ENABLE;
typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x00000000,
FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x00000001,
FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x00000003,
} FMT_CRC_CNTL_INTERLACE_MODE;
typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x00000000,
FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x00000001,
} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x00000000,
FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x00000001,
} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000,
FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001,
FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002,
FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003,
} FMT_DEBUG_CNTL_COLOR_SELECT;
typedef enum FMT_SPATIAL_DITHER_MODE {
FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
} FMT_SPATIAL_DITHER_MODE;
typedef enum FMT_STEREOSYNC_OVR_POL {
FMT_STEREOSYNC_OVR_POL_INVERTED = 0x00000000,
FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x00000001,
} FMT_STEREOSYNC_OVR_POL;
typedef enum FMT_DYNAMIC_EXP_MODE {
FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
} FMT_DYNAMIC_EXP_MODE;
typedef enum HPD_INT_CONTROL_ACK {
HPD_INT_CONTROL_ACK_0 = 0x00000000,
HPD_INT_CONTROL_ACK_1 = 0x00000001,
} HPD_INT_CONTROL_ACK;
typedef enum HPD_INT_CONTROL_POLARITY {
HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000,
HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001,
} HPD_INT_CONTROL_POLARITY;
typedef enum HPD_INT_CONTROL_RX_INT_ACK {
HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000,
HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001,
} HPD_INT_CONTROL_RX_INT_ACK;
typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x00000000,
LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x00000001,
LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x00000002,
LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x00000003,
} LB_DATA_FORMAT_PIXEL_DEPTH;
typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000,
LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001,
} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x00000000,
LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x00000001,
} LB_DATA_FORMAT_INTERLEAVE_EN;
typedef enum LB_DATA_FORMAT_REQUEST_MODE {
LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x00000000,
LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x00000001,
} LB_DATA_FORMAT_REQUEST_MODE;
typedef enum LB_DATA_FORMAT_ALPHA_EN {
LB_DATA_FORMAT_ALPHA_DISABLE = 0x00000000,
LB_DATA_FORMAT_ALPHA_ENABLE = 0x00000001,
} LB_DATA_FORMAT_ALPHA_EN;
typedef enum LB_VLINE_START_END_VLINE_INV {
LB_VLINE_START_END_VLINE_NORMAL = 0x00000000,
LB_VLINE_START_END_VLINE_INVERSE = 0x00000001,
} LB_VLINE_START_END_VLINE_INV;
typedef enum LB_VLINE2_START_END_VLINE2_INV {
LB_VLINE2_START_END_VLINE2_NORMAL = 0x00000000,
LB_VLINE2_START_END_VLINE2_INVERSE = 0x00000001,
} LB_VLINE2_START_END_VLINE2_INV;
typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000,
LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001,
} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000,
LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001,
} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000,
LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001,
} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
typedef enum LB_VLINE_STATUS_VLINE_ACK {
LB_VLINE_STATUS_VLINE_NORMAL = 0x00000000,
LB_VLINE_STATUS_VLINE_CLEAR = 0x00000001,
} LB_VLINE_STATUS_VLINE_ACK;
typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
LB_VLINE2_STATUS_VLINE2_NORMAL = 0x00000000,
LB_VLINE2_STATUS_VLINE2_CLEAR = 0x00000001,
} LB_VLINE2_STATUS_VLINE2_ACK;
typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
LB_VBLANK_STATUS_VBLANK_NORMAL = 0x00000000,
LB_VBLANK_STATUS_VBLANK_CLEAR = 0x00000001,
} LB_VBLANK_STATUS_VBLANK_ACK;
typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x00000000,
LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 0x00000001,
LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 0x00000002,
LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 0x00000003,
} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x00000000,
LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x00000001,
} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000,
LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001,
LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002,
LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003,
} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000,
LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001,
} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000,
LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001,
} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x00000000,
LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x00000001,
} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x00000000,
LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x00000001,
} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x00000002,
LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 0x00000003,
} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000,
LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 0x00000001,
} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000,
LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001,
} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0x00000000,
LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 0x00000001,
LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 0x00000002,
} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0x00000000,
LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x00000001,
} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 0x00000001,
ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 0x00000002,
} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000,
LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001,
} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000,
LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 0x00000001,
} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000,
LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 0x00000001,
} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000,
LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001,
} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
typedef enum HDMI_KEEPOUT_MODE {
HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000,
HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001,
} HDMI_KEEPOUT_MODE;
typedef enum HDMI_DATA_SCRAMBLE_EN {
HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000,
HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001,
} HDMI_DATA_SCRAMBLE_EN;
typedef enum HDMI_CLOCK_CHANNEL_RATE {
HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000,
HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001,
} HDMI_CLOCK_CHANNEL_RATE;
typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000,
HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001,
} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
typedef enum HDMI_PACKET_GEN_VERSION {
HDMI_PACKET_GEN_VERSION_OLD = 0x00000000,
HDMI_PACKET_GEN_VERSION_NEW = 0x00000001,
} HDMI_PACKET_GEN_VERSION;
typedef enum HDMI_ERROR_ACK {
HDMI_ERROR_ACK_INT = 0x00000000,
HDMI_ERROR_NOT_ACK = 0x00000001,
} HDMI_ERROR_ACK;
typedef enum HDMI_ERROR_MASK {
HDMI_ERROR_MASK_INT = 0x00000000,
HDMI_ERROR_NOT_MASK = 0x00000001,
} HDMI_ERROR_MASK;
typedef enum HDMI_DEEP_COLOR_DEPTH {
HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000,
HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001,
HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002,
HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x00000003,
} HDMI_DEEP_COLOR_DEPTH;
typedef enum HDMI_AUDIO_DELAY_EN {
HDMI_AUDIO_DELAY_DISABLE = 0x00000000,
HDMI_AUDIO_DELAY_58CLK = 0x00000001,
HDMI_AUDIO_DELAY_56CLK = 0x00000002,
HDMI_AUDIO_DELAY_RESERVED = 0x00000003,
} HDMI_AUDIO_DELAY_EN;
typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000,
HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001,
} HDMI_AUDIO_SEND_MAX_PACKETS;
typedef enum HDMI_ACR_SEND {
HDMI_ACR_NOT_SEND = 0x00000000,
HDMI_ACR_PKT_SEND = 0x00000001,
} HDMI_ACR_SEND;
typedef enum HDMI_ACR_CONT {
HDMI_ACR_CONT_DISABLE = 0x00000000,
HDMI_ACR_CONT_ENABLE = 0x00000001,
} HDMI_ACR_CONT;
typedef enum HDMI_ACR_SELECT {
HDMI_ACR_SELECT_HW = 0x00000000,
HDMI_ACR_SELECT_32K = 0x00000001,
HDMI_ACR_SELECT_44K = 0x00000002,
HDMI_ACR_SELECT_48K = 0x00000003,
} HDMI_ACR_SELECT;
typedef enum HDMI_ACR_SOURCE {
HDMI_ACR_SOURCE_HW = 0x00000000,
HDMI_ACR_SOURCE_SW = 0x00000001,
} HDMI_ACR_SOURCE;
typedef enum HDMI_ACR_N_MULTIPLE {
HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000,
HDMI_ACR_1_MULTIPLE = 0x00000001,
HDMI_ACR_2_MULTIPLE = 0x00000002,
HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003,
HDMI_ACR_4_MULTIPLE = 0x00000004,
HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005,
HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006,
HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007,
} HDMI_ACR_N_MULTIPLE;
typedef enum HDMI_ACR_AUDIO_PRIORITY {
HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
} HDMI_ACR_AUDIO_PRIORITY;
typedef enum HDMI_NULL_SEND {
HDMI_NULL_NOT_SEND = 0x00000000,
HDMI_NULL_PKT_SEND = 0x00000001,
} HDMI_NULL_SEND;
typedef enum HDMI_GC_SEND {
HDMI_GC_NOT_SEND = 0x00000000,
HDMI_GC_PKT_SEND = 0x00000001,
} HDMI_GC_SEND;
typedef enum HDMI_GC_CONT {
HDMI_GC_CONT_DISABLE = 0x00000000,
HDMI_GC_CONT_ENABLE = 0x00000001,
} HDMI_GC_CONT;
typedef enum HDMI_ISRC_SEND {
HDMI_ISRC_NOT_SEND = 0x00000000,
HDMI_ISRC_PKT_SEND = 0x00000001,
} HDMI_ISRC_SEND;
typedef enum HDMI_ISRC_CONT {
HDMI_ISRC_CONT_DISABLE = 0x00000000,
HDMI_ISRC_CONT_ENABLE = 0x00000001,
} HDMI_ISRC_CONT;
typedef enum HDMI_AVI_INFO_SEND {
HDMI_AVI_INFO_NOT_SEND = 0x00000000,
HDMI_AVI_INFO_PKT_SEND = 0x00000001,
} HDMI_AVI_INFO_SEND;
typedef enum HDMI_AVI_INFO_CONT {
HDMI_AVI_INFO_CONT_DISABLE = 0x00000000,
HDMI_AVI_INFO_CONT_ENABLE = 0x00000001,
} HDMI_AVI_INFO_CONT;
typedef enum HDMI_AUDIO_INFO_SEND {
HDMI_AUDIO_INFO_NOT_SEND = 0x00000000,
HDMI_AUDIO_INFO_PKT_SEND = 0x00000001,
} HDMI_AUDIO_INFO_SEND;
typedef enum HDMI_AUDIO_INFO_CONT {
HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000,
HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001,
} HDMI_AUDIO_INFO_CONT;
typedef enum HDMI_MPEG_INFO_SEND {
HDMI_MPEG_INFO_NOT_SEND = 0x00000000,
HDMI_MPEG_INFO_PKT_SEND = 0x00000001,
} HDMI_MPEG_INFO_SEND;
typedef enum HDMI_MPEG_INFO_CONT {
HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000,
HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001,
} HDMI_MPEG_INFO_CONT;
typedef enum HDMI_GENERIC0_SEND {
HDMI_GENERIC0_NOT_SEND = 0x00000000,
HDMI_GENERIC0_PKT_SEND = 0x00000001,
} HDMI_GENERIC0_SEND;
typedef enum HDMI_GENERIC0_CONT {
HDMI_GENERIC0_CONT_DISABLE = 0x00000000,
HDMI_GENERIC0_CONT_ENABLE = 0x00000001,
} HDMI_GENERIC0_CONT;
typedef enum HDMI_GENERIC1_SEND {
HDMI_GENERIC1_NOT_SEND = 0x00000000,
HDMI_GENERIC1_PKT_SEND = 0x00000001,
} HDMI_GENERIC1_SEND;
typedef enum HDMI_GENERIC1_CONT {
HDMI_GENERIC1_CONT_DISABLE = 0x00000000,
HDMI_GENERIC1_CONT_ENABLE = 0x00000001,
} HDMI_GENERIC1_CONT;
typedef enum HDMI_GC_AVMUTE_CONT {
HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000,
HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001,
} HDMI_GC_AVMUTE_CONT;
typedef enum HDMI_PACKING_PHASE_OVERRIDE {
HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000,
HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001,
} HDMI_PACKING_PHASE_OVERRIDE;
typedef enum HDMI_GENERIC2_SEND {
HDMI_GENERIC2_NOT_SEND = 0x00000000,
HDMI_GENERIC2_PKT_SEND = 0x00000001,
} HDMI_GENERIC2_SEND;
typedef enum HDMI_GENERIC2_CONT {
HDMI_GENERIC2_CONT_DISABLE = 0x00000000,
HDMI_GENERIC2_CONT_ENABLE = 0x00000001,
} HDMI_GENERIC2_CONT;
typedef enum HDMI_GENERIC3_SEND {
HDMI_GENERIC3_NOT_SEND = 0x00000000,
HDMI_GENERIC3_PKT_SEND = 0x00000001,
} HDMI_GENERIC3_SEND;
typedef enum HDMI_GENERIC3_CONT {
HDMI_GENERIC3_CONT_DISABLE = 0x00000000,
HDMI_GENERIC3_CONT_ENABLE = 0x00000001,
} HDMI_GENERIC3_CONT;
typedef enum TMDS_PIXEL_ENCODING {
TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000,
TMDS_PIXEL_ENCODING_422 = 0x00000001,
} TMDS_PIXEL_ENCODING;
typedef enum TMDS_COLOR_FORMAT {
TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000,
TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001,
TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002,
TMDS_COLOR_FORMAT_RESERVED = 0x00000003,
} TMDS_COLOR_FORMAT;
typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
TMDS_STEREOSYNC_CTL0 = 0x00000000,
TMDS_STEREOSYNC_CTL1 = 0x00000001,
TMDS_STEREOSYNC_CTL2 = 0x00000002,
TMDS_STEREOSYNC_CTL3 = 0x00000003,
} TMDS_STEREOSYNC_CTL_SEL_REG;
typedef enum TMDS_CTL0_DATA_SEL {
TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000,
TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002,
TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003,
TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004,
TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005,
TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006,
TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007,
} TMDS_CTL0_DATA_SEL;
typedef enum TMDS_CTL0_DATA_INVERT {
TMDS_CTL0_DATA_NORMAL = 0x00000000,
TMDS_CTL0_DATA_INVERT_EN = 0x00000001,
} TMDS_CTL0_DATA_INVERT;
typedef enum TMDS_CTL0_DATA_MODULATION {
TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000,
TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001,
TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002,
TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003,
} TMDS_CTL0_DATA_MODULATION;
typedef enum TMDS_CTL0_PATTERN_OUT_EN {
TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000,
TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001,
} TMDS_CTL0_PATTERN_OUT_EN;
typedef enum TMDS_CTL1_DATA_SEL {
TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000,
TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002,
TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003,
TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004,
TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005,
TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006,
TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007,
} TMDS_CTL1_DATA_SEL;
typedef enum TMDS_CTL1_DATA_INVERT {
TMDS_CTL1_DATA_NORMAL = 0x00000000,
TMDS_CTL1_DATA_INVERT_EN = 0x00000001,
} TMDS_CTL1_DATA_INVERT;
typedef enum TMDS_CTL1_DATA_MODULATION {
TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000,
TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001,
TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002,
TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003,
} TMDS_CTL1_DATA_MODULATION;
typedef enum TMDS_CTL1_PATTERN_OUT_EN {
TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000,
TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001,
} TMDS_CTL1_PATTERN_OUT_EN;
typedef enum TMDS_CTL2_DATA_SEL {
TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000,
TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002,
TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003,
TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004,
TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005,
TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006,
TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007,
} TMDS_CTL2_DATA_SEL;
typedef enum TMDS_CTL2_DATA_INVERT {
TMDS_CTL2_DATA_NORMAL = 0x00000000,
TMDS_CTL2_DATA_INVERT_EN = 0x00000001,
} TMDS_CTL2_DATA_INVERT;
typedef enum TMDS_CTL2_DATA_MODULATION {
TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000,
TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001,
TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002,
TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003,
} TMDS_CTL2_DATA_MODULATION;
typedef enum TMDS_CTL2_PATTERN_OUT_EN {
TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000,
TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001,
} TMDS_CTL2_PATTERN_OUT_EN;
typedef enum TMDS_CTL3_DATA_INVERT {
TMDS_CTL3_DATA_NORMAL = 0x00000000,
TMDS_CTL3_DATA_INVERT_EN = 0x00000001,
} TMDS_CTL3_DATA_INVERT;
typedef enum TMDS_CTL3_DATA_MODULATION {
TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000,
TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001,
TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002,
TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003,
} TMDS_CTL3_DATA_MODULATION;
typedef enum TMDS_CTL3_PATTERN_OUT_EN {
TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000,
TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001,
} TMDS_CTL3_PATTERN_OUT_EN;
typedef enum TMDS_CTL3_DATA_SEL {
TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000,
TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002,
TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003,
TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004,
TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005,
TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006,
TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007,
} TMDS_CTL3_DATA_SEL;
typedef enum DIG_FE_CNTL_SOURCE_SELECT {
DIG_FE_SOURCE_FROM_FMT0 = 0x00000000,
DIG_FE_SOURCE_FROM_FMT1 = 0x00000001,
DIG_FE_SOURCE_FROM_FMT2 = 0x00000002,
DIG_FE_SOURCE_FROM_FMT3 = 0x00000003,
DIG_FE_SOURCE_FROM_FMT4 = 0x00000004,
DIG_FE_SOURCE_FROM_FMT5 = 0x00000005,
} DIG_FE_CNTL_SOURCE_SELECT;
typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
DIG_FE_STEREOSYNC_FROM_FMT0 = 0x00000000,
DIG_FE_STEREOSYNC_FROM_FMT1 = 0x00000001,
DIG_FE_STEREOSYNC_FROM_FMT2 = 0x00000002,
DIG_FE_STEREOSYNC_FROM_FMT3 = 0x00000003,
DIG_FE_STEREOSYNC_FROM_FMT4 = 0x00000004,
DIG_FE_STEREOSYNC_FROM_FMT5 = 0x00000005,
} DIG_FE_CNTL_STEREOSYNC_SELECT;
typedef enum DIG_FIFO_READ_CLOCK_SRC {
DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000,
DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001,
} DIG_FIFO_READ_CLOCK_SRC;
typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000,
DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001,
} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
typedef enum DIG_OUTPUT_CRC_DATA_SEL {
DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000,
DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001,
DIG_OUTPUT_CRC_FOR_VBI = 0x00000002,
DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003,
} DIG_OUTPUT_CRC_DATA_SEL;
typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
DIG_IN_NORMAL_OPERATION = 0x00000000,
DIG_IN_DEBUG_MODE = 0x00000001,
} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
DIG_10BIT_TEST_PATTERN = 0x00000000,
DIG_ALTERNATING_TEST_PATTERN = 0x00000001,
} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
DIG_TEST_PATTERN_NORMAL = 0x00000000,
DIG_TEST_PATTERN_RANDOM = 0x00000001,
} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
DIG_RANDOM_PATTERN_ENABLED = 0x00000000,
DIG_RANDOM_PATTERN_RESETED = 0x00000001,
} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000,
DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001,
} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000,
DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001,
} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000,
DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001,
} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
typedef enum DIG_FIFO_ERROR_ACK {
DIG_FIFO_ERROR_ACK_INT = 0x00000000,
DIG_FIFO_ERROR_NOT_ACK = 0x00000001,
} DIG_FIFO_ERROR_ACK;
typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000,
DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001,
} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000,
DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001,
} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
AFMT_INTERRUPT_DISABLE = 0x00000000,
AFMT_INTERRUPT_ENABLE = 0x00000001,
} AFMT_INTERRUPT_STATUS_CHG_MASK;
typedef enum HDMI_GC_AVMUTE {
HDMI_GC_AVMUTE_SET = 0x00000000,
HDMI_GC_AVMUTE_UNSET = 0x00000001,
} HDMI_GC_AVMUTE;
typedef enum HDMI_DEFAULT_PAHSE {
HDMI_DEFAULT_PHASE_IS_0 = 0x00000000,
HDMI_DEFAULT_PHASE_IS_1 = 0x00000001,
} HDMI_DEFAULT_PAHSE;
typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000,
AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001,
} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
typedef enum AUDIO_LAYOUT_SELECT {
AUDIO_LAYOUT_0 = 0x00000000,
AUDIO_LAYOUT_1 = 0x00000001,
} AUDIO_LAYOUT_SELECT;
typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
AFMT_AUDIO_CRC_ONESHOT = 0x00000000,
AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001,
} AFMT_AUDIO_CRC_CONTROL_CONT;
typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000,
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001,
} AFMT_AUDIO_CRC_CONTROL_SOURCE;
typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
AFMT_AUDIO_CRC_CH0_SIG = 0x00000000,
AFMT_AUDIO_CRC_CH1_SIG = 0x00000001,
AFMT_AUDIO_CRC_CH2_SIG = 0x00000002,
AFMT_AUDIO_CRC_CH3_SIG = 0x00000003,
AFMT_AUDIO_CRC_CH4_SIG = 0x00000004,
AFMT_AUDIO_CRC_CH5_SIG = 0x00000005,
AFMT_AUDIO_CRC_CH6_SIG = 0x00000006,
AFMT_AUDIO_CRC_CH7_SIG = 0x00000007,
AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008,
AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009,
AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a,
AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b,
AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c,
AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d,
AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e,
AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f,
} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
typedef enum AFMT_RAMP_CONTROL0_SIGN {
AFMT_RAMP_SIGNED = 0x00000000,
AFMT_RAMP_UNSIGNED = 0x00000001,
} AFMT_RAMP_CONTROL0_SIGN;
typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000,
AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001,
} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000,
AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001,
} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000,
AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000,
AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001,
AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002,
AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003,
AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004,
AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005,
AFMT_AUDIO_SRC_RESERVED = 0x00000006,
} AFMT_AUDIO_SRC_CONTROL_SELECT;
typedef enum DIG_BE_CNTL_MODE {
DIG_BE_DP_SST_MODE = 0x00000000,
DIG_BE_RESERVED1 = 0x00000001,
DIG_BE_TMDS_DVI_MODE = 0x00000002,
DIG_BE_TMDS_HDMI_MODE = 0x00000003,
DIG_BE_SDVO_RESERVED = 0x00000004,
DIG_BE_DP_MST_MODE = 0x00000005,
DIG_BE_RESERVED2 = 0x00000006,
DIG_BE_RESERVED3 = 0x00000007,
} DIG_BE_CNTL_MODE;
typedef enum DIG_BE_CNTL_HPD_SELECT {
DIG_BE_CNTL_HPD1 = 0x00000000,
DIG_BE_CNTL_HPD2 = 0x00000001,
DIG_BE_CNTL_HPD3 = 0x00000002,
DIG_BE_CNTL_HPD4 = 0x00000003,
DIG_BE_CNTL_HPD5 = 0x00000004,
DIG_BE_CNTL_HPD6 = 0x00000005,
} DIG_BE_CNTL_HPD_SELECT;
typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000,
LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001,
} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
typedef enum TMDS_SYNC_PHASE {
TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000,
TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001,
} TMDS_SYNC_PHASE;
typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000,
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001,
} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000,
TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001,
} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001,
} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001,
} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000,
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001,
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002,
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003,
} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000,
TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000,
TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000,
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000,
TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000,
TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000,
TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000,
TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000,
TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000,
TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000,
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001,
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002,
TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003,
} TMDS_REG_TEST_OUTPUTA_CNTLA;
typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000,
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001,
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002,
TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003,
} TMDS_REG_TEST_OUTPUTB_CNTLB;
typedef enum DCP_GRPH_ENABLE {
DCP_GRPH_ENABLE_FALSE = 0x00000000,
DCP_GRPH_ENABLE_TRUE = 0x00000001,
} DCP_GRPH_ENABLE;
typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x00000000,
DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x00000001,
} DCP_GRPH_KEYER_ALPHA_SEL;
typedef enum DCP_GRPH_DEPTH {
DCP_GRPH_DEPTH_8BPP = 0x00000000,
DCP_GRPH_DEPTH_16BPP = 0x00000001,
DCP_GRPH_DEPTH_32BPP = 0x00000002,
DCP_GRPH_DEPTH_64BPP = 0x00000003,
} DCP_GRPH_DEPTH;
typedef enum DCP_GRPH_NUM_BANKS {
DCP_GRPH_NUM_BANKS_1BANK = 0x00000000,
DCP_GRPH_NUM_BANKS_2BANK = 0x00000001,
DCP_GRPH_NUM_BANKS_4BANK = 0x00000002,
DCP_GRPH_NUM_BANKS_8BANK = 0x00000003,
DCP_GRPH_NUM_BANKS_16BANK = 0x00000004,
} DCP_GRPH_NUM_BANKS;
typedef enum DCP_GRPH_NUM_PIPES {
DCP_GRPH_NUM_PIPES_1PIPE = 0x00000000,
DCP_GRPH_NUM_PIPES_2PIPE = 0x00000001,
DCP_GRPH_NUM_PIPES_4PIPE = 0x00000002,
DCP_GRPH_NUM_PIPES_8PIPE = 0x00000003,
} DCP_GRPH_NUM_PIPES;
typedef enum DCP_GRPH_FORMAT {
DCP_GRPH_FORMAT_8BPP = 0x00000000,
DCP_GRPH_FORMAT_16BPP = 0x00000001,
DCP_GRPH_FORMAT_32BPP = 0x00000002,
DCP_GRPH_FORMAT_64BPP = 0x00000003,
} DCP_GRPH_FORMAT;
typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x00000000,
DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x00000001,
} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
typedef enum DCP_GRPH_SW_MODE {
DCP_GRPH_SW_MODE_0 = 0x00000000,
DCP_GRPH_SW_MODE_2 = 0x00000002,
DCP_GRPH_SW_MODE_3 = 0x00000003,
DCP_GRPH_SW_MODE_22 = 0x00000016,
DCP_GRPH_SW_MODE_23 = 0x00000017,
DCP_GRPH_SW_MODE_26 = 0x0000001a,
DCP_GRPH_SW_MODE_27 = 0x0000001b,
DCP_GRPH_SW_MODE_30 = 0x0000001e,
DCP_GRPH_SW_MODE_31 = 0x0000001f,
} DCP_GRPH_SW_MODE;
typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x00000000,
DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x00000001,
} DCP_GRPH_COLOR_EXPANSION_MODE;
typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x00000000,
DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x00000001,
} DCP_GRPH_LUT_10BIT_BYPASS_EN;
typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x00000000,
DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x00000001,
} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
typedef enum DCP_GRPH_ENDIAN_SWAP {
DCP_GRPH_ENDIAN_SWAP_NONE = 0x00000000,
DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001,
DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002,
DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x00000003,
} DCP_GRPH_ENDIAN_SWAP;
typedef enum DCP_GRPH_RED_CROSSBAR {
DCP_GRPH_RED_CROSSBAR_FROM_R = 0x00000000,
DCP_GRPH_RED_CROSSBAR_FROM_G = 0x00000001,
DCP_GRPH_RED_CROSSBAR_FROM_B = 0x00000002,
DCP_GRPH_RED_CROSSBAR_FROM_A = 0x00000003,
} DCP_GRPH_RED_CROSSBAR;
typedef enum DCP_GRPH_GREEN_CROSSBAR {
DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x00000000,
DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x00000001,
DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x00000002,
DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x00000003,
} DCP_GRPH_GREEN_CROSSBAR;
typedef enum DCP_GRPH_BLUE_CROSSBAR {
DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x00000000,
DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x00000001,
DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x00000002,
DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x00000003,
} DCP_GRPH_BLUE_CROSSBAR;
typedef enum DCP_GRPH_ALPHA_CROSSBAR {
DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x00000000,
DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x00000001,
DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x00000002,
DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x00000003,
} DCP_GRPH_ALPHA_CROSSBAR;
typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x00000000,
DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x00000001,
} DCP_GRPH_PRIMARY_DFQ_ENABLE;
typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x00000000,
DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x00000001,
} DCP_GRPH_SECONDARY_DFQ_ENABLE;
typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x00000000,
DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x00000001,
} DCP_GRPH_INPUT_GAMMA_MODE;
typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x00000000,
DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x00000001,
} DCP_GRPH_MODE_UPDATE_PENDING;
typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x00000000,
DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x00000001,
} DCP_GRPH_MODE_UPDATE_TAKEN;
typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x00000000,
DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x00000001,
} DCP_GRPH_SURFACE_UPDATE_PENDING;
typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x00000000,
DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x00000001,
} DCP_GRPH_SURFACE_UPDATE_TAKEN;
typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x00000000,
DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x00000001,
} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
typedef enum DCP_GRPH_UPDATE_LOCK {
DCP_GRPH_UPDATE_LOCK_FALSE = 0x00000000,
DCP_GRPH_UPDATE_LOCK_TRUE = 0x00000001,
} DCP_GRPH_UPDATE_LOCK;
typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x00000000,
DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x00000001,
} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x00000000,
DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x00000001,
} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x00000000,
DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x00000001,
} DCP_GRPH_XDMA_SUPER_AA_EN;
typedef enum DCP_GRPH_DFQ_RESET {
DCP_GRPH_DFQ_RESET_FALSE = 0x00000000,
DCP_GRPH_DFQ_RESET_TRUE = 0x00000001,
} DCP_GRPH_DFQ_RESET;
typedef enum DCP_GRPH_DFQ_SIZE {
DCP_GRPH_DFQ_SIZE_DEEP1 = 0x00000000,
DCP_GRPH_DFQ_SIZE_DEEP2 = 0x00000001,
DCP_GRPH_DFQ_SIZE_DEEP3 = 0x00000002,
DCP_GRPH_DFQ_SIZE_DEEP4 = 0x00000003,
DCP_GRPH_DFQ_SIZE_DEEP5 = 0x00000004,
DCP_GRPH_DFQ_SIZE_DEEP6 = 0x00000005,
DCP_GRPH_DFQ_SIZE_DEEP7 = 0x00000006,
DCP_GRPH_DFQ_SIZE_DEEP8 = 0x00000007,
} DCP_GRPH_DFQ_SIZE;
typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x00000000,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x00000001,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x00000002,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x00000003,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x00000004,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x00000005,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x00000006,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x00000007,
} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
typedef enum DCP_GRPH_DFQ_RESET_ACK {
DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x00000000,
DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x00000001,
} DCP_GRPH_DFQ_RESET_ACK;
typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x00000000,
DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x00000001,
} DCP_GRPH_PFLIP_INT_CLEAR;
typedef enum DCP_GRPH_PFLIP_INT_MASK {
DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x00000000,
DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x00000001,
} DCP_GRPH_PFLIP_INT_MASK;
typedef enum DCP_GRPH_PFLIP_INT_TYPE {
DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x00000000,
DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x00000001,
} DCP_GRPH_PFLIP_INT_TYPE;
typedef enum DCP_GRPH_PRESCALE_SELECT {
DCP_GRPH_PRESCALE_SELECT_FIXED = 0x00000000,
DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x00000001,
} DCP_GRPH_PRESCALE_SELECT;
typedef enum DCP_GRPH_PRESCALE_R_SIGN {
DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x00000000,
DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x00000001,
} DCP_GRPH_PRESCALE_R_SIGN;
typedef enum DCP_GRPH_PRESCALE_G_SIGN {
DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x00000000,
DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x00000001,
} DCP_GRPH_PRESCALE_G_SIGN;
typedef enum DCP_GRPH_PRESCALE_B_SIGN {
DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x00000000,
DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x00000001,
} DCP_GRPH_PRESCALE_B_SIGN;
typedef enum DCP_GRPH_PRESCALE_BYPASS {
DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x00000000,
DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x00000001,
} DCP_GRPH_PRESCALE_BYPASS;
typedef enum DCP_INPUT_CSC_GRPH_MODE {
DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x00000000,
DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x00000001,
DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000002,
DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x00000003,
} DCP_INPUT_CSC_GRPH_MODE;
typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x00000000,
DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x00000001,
DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x00000002,
DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x00000003,
DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x00000004,
DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000005,
DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x00000006,
DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x00000007,
} DCP_OUTPUT_CSC_GRPH_MODE;
typedef enum DCP_DENORM_MODE {
DCP_DENORM_MODE_UNITY = 0x00000000,
DCP_DENORM_MODE_6BIT = 0x00000001,
DCP_DENORM_MODE_8BIT = 0x00000002,
DCP_DENORM_MODE_10BIT = 0x00000003,
DCP_DENORM_MODE_11BIT = 0x00000004,
DCP_DENORM_MODE_12BIT = 0x00000005,
DCP_DENORM_MODE_RESERVED0 = 0x00000006,
DCP_DENORM_MODE_RESERVED1 = 0x00000007,
} DCP_DENORM_MODE;
typedef enum DCP_DENORM_14BIT_OUT {
DCP_DENORM_14BIT_OUT_FALSE = 0x00000000,
DCP_DENORM_14BIT_OUT_TRUE = 0x00000001,
} DCP_DENORM_14BIT_OUT;
typedef enum DCP_OUT_ROUND_TRUNC_MODE {
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x00000000,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x00000001,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x00000002,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x00000003,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x00000004,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x00000005,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x00000006,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x00000007,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x00000008,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x00000009,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0x0000000a,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0x0000000b,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0x0000000c,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0x0000000d,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0x0000000e,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0x0000000f,
} DCP_OUT_ROUND_TRUNC_MODE;
typedef enum DCP_KEY_MODE {
DCP_KEY_MODE_ALPHA0 = 0x00000000,
DCP_KEY_MODE_ALPHA1 = 0x00000001,
DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x00000002,
DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x00000003,
} DCP_KEY_MODE;
typedef enum DCP_GRPH_DEGAMMA_MODE {
DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x00000000,
DCP_GRPH_DEGAMMA_MODE_ROMA = 0x00000001,
DCP_GRPH_DEGAMMA_MODE_ROMB = 0x00000002,
DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x00000003,
} DCP_GRPH_DEGAMMA_MODE;
typedef enum DCP_CURSOR_DEGAMMA_MODE {
DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x00000000,
DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x00000001,
DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x00000002,
DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x00000003,
} DCP_CURSOR_DEGAMMA_MODE;
typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x00000000,
DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x00000001,
DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x00000002,
DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x00000003,
} DCP_GRPH_GAMUT_REMAP_MODE;
typedef enum DCP_SPATIAL_DITHER_EN {
DCP_SPATIAL_DITHER_EN_FALSE = 0x00000000,
DCP_SPATIAL_DITHER_EN_TRUE = 0x00000001,
} DCP_SPATIAL_DITHER_EN;
typedef enum DCP_SPATIAL_DITHER_MODE {
DCP_SPATIAL_DITHER_MODE_BYPASS = 0x00000000,
DCP_SPATIAL_DITHER_MODE_ROMA = 0x00000001,
DCP_SPATIAL_DITHER_MODE_ROMB = 0x00000002,
DCP_SPATIAL_DITHER_MODE_RESERVED = 0x00000003,
} DCP_SPATIAL_DITHER_MODE;
typedef enum DCP_SPATIAL_DITHER_DEPTH {
DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x00000000,
DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x00000002,
DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x00000003,
} DCP_SPATIAL_DITHER_DEPTH;
typedef enum DCP_FRAME_RANDOM_ENABLE {
DCP_FRAME_RANDOM_ENABLE_FALSE = 0x00000000,
DCP_FRAME_RANDOM_ENABLE_TRUE = 0x00000001,
} DCP_FRAME_RANDOM_ENABLE;
typedef enum DCP_RGB_RANDOM_ENABLE {
DCP_RGB_RANDOM_ENABLE_FALSE = 0x00000000,
DCP_RGB_RANDOM_ENABLE_TRUE = 0x00000001,
} DCP_RGB_RANDOM_ENABLE;
typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x00000000,
DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x00000001,
} DCP_HIGHPASS_RANDOM_ENABLE;
typedef enum DCP_CURSOR_EN {
DCP_CURSOR_EN_FALSE = 0x00000000,
DCP_CURSOR_EN_TRUE = 0x00000001,
} DCP_CURSOR_EN;
typedef enum DCP_CUR_INV_TRANS_CLAMP {
DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x00000000,
DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x00000001,
} DCP_CUR_INV_TRANS_CLAMP;
typedef enum DCP_CURSOR_MODE {
DCP_CURSOR_MODE_MONO_2BPP = 0x00000000,
DCP_CURSOR_MODE_24BPP_1BIT = 0x00000001,
DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x00000002,
DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x00000003,
} DCP_CURSOR_MODE;
typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE = 0x00000000,
DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO = 0x00000001,
} DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM;
typedef enum DCP_CURSOR_2X_MAGNIFY {
DCP_CURSOR_2X_MAGNIFY_FALSE = 0x00000000,
DCP_CURSOR_2X_MAGNIFY_TRUE = 0x00000001,
} DCP_CURSOR_2X_MAGNIFY;
typedef enum DCP_CURSOR_FORCE_MC_ON {
DCP_CURSOR_FORCE_MC_ON_FALSE = 0x00000000,
DCP_CURSOR_FORCE_MC_ON_TRUE = 0x00000001,
} DCP_CURSOR_FORCE_MC_ON;
typedef enum DCP_CURSOR_URGENT_CONTROL {
DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x00000000,
DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x00000001,
DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x00000002,
DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x00000003,
DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x00000004,
} DCP_CURSOR_URGENT_CONTROL;
typedef enum DCP_CURSOR_UPDATE_PENDING {
DCP_CURSOR_UPDATE_PENDING_FALSE = 0x00000000,
DCP_CURSOR_UPDATE_PENDING_TRUE = 0x00000001,
} DCP_CURSOR_UPDATE_PENDING;
typedef enum DCP_CURSOR_UPDATE_TAKEN {
DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x00000000,
DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x00000001,
} DCP_CURSOR_UPDATE_TAKEN;
typedef enum DCP_CURSOR_UPDATE_LOCK {
DCP_CURSOR_UPDATE_LOCK_FALSE = 0x00000000,
DCP_CURSOR_UPDATE_LOCK_TRUE = 0x00000001,
} DCP_CURSOR_UPDATE_LOCK;
typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x00000000,
DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x00000001,
DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x00000002,
DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x00000003,
} DCP_CURSOR_UPDATE_STEREO_MODE;
typedef enum DCP_CUR2_INV_TRANS_CLAMP {
DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x00000000,
DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x00000001,
} DCP_CUR2_INV_TRANS_CLAMP;
typedef enum DCP_CUR_REQUEST_FILTER_DIS {
DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x00000000,
DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x00000001,
} DCP_CUR_REQUEST_FILTER_DIS;
typedef enum DCP_CURSOR_STEREO_EN {
DCP_CURSOR_STEREO_EN_FALSE = 0x00000000,
DCP_CURSOR_STEREO_EN_TRUE = 0x00000001,
} DCP_CURSOR_STEREO_EN;
typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x00000000,
DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x00000001,
} DCP_CURSOR_STEREO_OFFSET_YNX;
typedef enum DCP_DC_LUT_RW_MODE {
DCP_DC_LUT_RW_MODE_256_ENTRY = 0x00000000,
DCP_DC_LUT_RW_MODE_PWL = 0x00000001,
} DCP_DC_LUT_RW_MODE;
typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x00000000,
DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x00000001,
} DCP_DC_LUT_VGA_ACCESS_ENABLE;
typedef enum DCP_DC_LUT_AUTOFILL {
DCP_DC_LUT_AUTOFILL_FALSE = 0x00000000,
DCP_DC_LUT_AUTOFILL_TRUE = 0x00000001,
} DCP_DC_LUT_AUTOFILL;
typedef enum DCP_DC_LUT_AUTOFILL_DONE {
DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x00000000,
DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x00000001,
} DCP_DC_LUT_AUTOFILL_DONE;
typedef enum DCP_DC_LUT_INC_B {
DCP_DC_LUT_INC_B_NA = 0x00000000,
DCP_DC_LUT_INC_B_2 = 0x00000001,
DCP_DC_LUT_INC_B_4 = 0x00000002,
DCP_DC_LUT_INC_B_8 = 0x00000003,
DCP_DC_LUT_INC_B_16 = 0x00000004,
DCP_DC_LUT_INC_B_32 = 0x00000005,
DCP_DC_LUT_INC_B_64 = 0x00000006,
DCP_DC_LUT_INC_B_128 = 0x00000007,
DCP_DC_LUT_INC_B_256 = 0x00000008,
DCP_DC_LUT_INC_B_512 = 0x00000009,
} DCP_DC_LUT_INC_B;
typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x00000000,
DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x00000001,
} DCP_DC_LUT_DATA_B_SIGNED_EN;
typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x00000000,
DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x00000001,
} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
typedef enum DCP_DC_LUT_DATA_B_FORMAT {
DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x00000000,
DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x00000001,
DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x00000002,
DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x00000003,
} DCP_DC_LUT_DATA_B_FORMAT;
typedef enum DCP_DC_LUT_INC_G {
DCP_DC_LUT_INC_G_NA = 0x00000000,
DCP_DC_LUT_INC_G_2 = 0x00000001,
DCP_DC_LUT_INC_G_4 = 0x00000002,
DCP_DC_LUT_INC_G_8 = 0x00000003,
DCP_DC_LUT_INC_G_16 = 0x00000004,
DCP_DC_LUT_INC_G_32 = 0x00000005,
DCP_DC_LUT_INC_G_64 = 0x00000006,
DCP_DC_LUT_INC_G_128 = 0x00000007,
DCP_DC_LUT_INC_G_256 = 0x00000008,
DCP_DC_LUT_INC_G_512 = 0x00000009,
} DCP_DC_LUT_INC_G;
typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x00000000,
DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x00000001,
} DCP_DC_LUT_DATA_G_SIGNED_EN;
typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x00000000,
DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x00000001,
} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
typedef enum DCP_DC_LUT_DATA_G_FORMAT {
DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x00000000,
DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x00000001,
DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x00000002,
DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x00000003,
} DCP_DC_LUT_DATA_G_FORMAT;
typedef enum DCP_DC_LUT_INC_R {
DCP_DC_LUT_INC_R_NA = 0x00000000,
DCP_DC_LUT_INC_R_2 = 0x00000001,
DCP_DC_LUT_INC_R_4 = 0x00000002,
DCP_DC_LUT_INC_R_8 = 0x00000003,
DCP_DC_LUT_INC_R_16 = 0x00000004,
DCP_DC_LUT_INC_R_32 = 0x00000005,
DCP_DC_LUT_INC_R_64 = 0x00000006,
DCP_DC_LUT_INC_R_128 = 0x00000007,
DCP_DC_LUT_INC_R_256 = 0x00000008,
DCP_DC_LUT_INC_R_512 = 0x00000009,
} DCP_DC_LUT_INC_R;
typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x00000000,
DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x00000001,
} DCP_DC_LUT_DATA_R_SIGNED_EN;
typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x00000000,
DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x00000001,
} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
typedef enum DCP_DC_LUT_DATA_R_FORMAT {
DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x00000000,
DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x00000001,
DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x00000002,
DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x00000003,
} DCP_DC_LUT_DATA_R_FORMAT;
typedef enum DCP_CRC_ENABLE {
DCP_CRC_ENABLE_FALSE = 0x00000000,
DCP_CRC_ENABLE_TRUE = 0x00000001,
} DCP_CRC_ENABLE;
typedef enum DCP_CRC_SOURCE_SEL {
DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x00000000,
DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x00000001,
DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x00000002,
DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x00000004,
} DCP_CRC_SOURCE_SEL;
typedef enum DCP_CRC_LINE_SEL {
DCP_CRC_LINE_SEL_RESERVED = 0x00000000,
DCP_CRC_LINE_SEL_EVEN = 0x00000001,
DCP_CRC_LINE_SEL_ODD = 0x00000002,
DCP_CRC_LINE_SEL_BOTH = 0x00000003,
} DCP_CRC_LINE_SEL;
typedef enum DCP_GRPH_FLIP_RATE {
DCP_GRPH_FLIP_RATE_1FRAME = 0x00000000,
DCP_GRPH_FLIP_RATE_2FRAME = 0x00000001,
DCP_GRPH_FLIP_RATE_3FRAME = 0x00000002,
DCP_GRPH_FLIP_RATE_4FRAME = 0x00000003,
DCP_GRPH_FLIP_RATE_5FRAME = 0x00000004,
DCP_GRPH_FLIP_RATE_6FRAME = 0x00000005,
DCP_GRPH_FLIP_RATE_7FRAME = 0x00000006,
DCP_GRPH_FLIP_RATE_8FRAME = 0x00000007,
} DCP_GRPH_FLIP_RATE;
typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x00000000,
DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x00000001,
} DCP_GRPH_FLIP_RATE_ENABLE;
typedef enum DCP_GSL0_EN {
DCP_GSL0_EN_FALSE = 0x00000000,
DCP_GSL0_EN_TRUE = 0x00000001,
} DCP_GSL0_EN;
typedef enum DCP_GSL1_EN {
DCP_GSL1_EN_FALSE = 0x00000000,
DCP_GSL1_EN_TRUE = 0x00000001,
} DCP_GSL1_EN;
typedef enum DCP_GSL2_EN {
DCP_GSL2_EN_FALSE = 0x00000000,
DCP_GSL2_EN_TRUE = 0x00000001,
} DCP_GSL2_EN;
typedef enum DCP_GSL_MASTER_EN {
DCP_GSL_MASTER_EN_FALSE = 0x00000000,
DCP_GSL_MASTER_EN_TRUE = 0x00000001,
} DCP_GSL_MASTER_EN;
typedef enum DCP_GSL_XDMA_GROUP {
DCP_GSL_XDMA_GROUP_VSYNC = 0x00000000,
DCP_GSL_XDMA_GROUP_HSYNC0 = 0x00000001,
DCP_GSL_XDMA_GROUP_HSYNC1 = 0x00000002,
DCP_GSL_XDMA_GROUP_HSYNC2 = 0x00000003,
} DCP_GSL_XDMA_GROUP;
typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x00000000,
DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x00000001,
} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
typedef enum DCP_GSL_SYNC_SOURCE {
DCP_GSL_SYNC_SOURCE_FLIP = 0x00000000,
DCP_GSL_SYNC_SOURCE_PHASE0 = 0x00000001,
DCP_GSL_SYNC_SOURCE_RESET = 0x00000002,
DCP_GSL_SYNC_SOURCE_PHASE1 = 0x00000003,
} DCP_GSL_SYNC_SOURCE;
typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC {
DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS = 0x00000000,
DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN = 0x00000001,
} DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC;
typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x00000000,
DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x00000001,
} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
typedef enum DCP_TEST_DEBUG_WRITE_EN {
DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
} DCP_TEST_DEBUG_WRITE_EN;
typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x00000000,
DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x00000001,
} DCP_GRPH_STEREOSYNC_FLIP_EN;
typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x00000000,
DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x00000001,
DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x00000002,
DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x00000003,
} DCP_GRPH_STEREOSYNC_FLIP_MODE;
typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x00000000,
DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x00000001,
} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
typedef enum DCP_GRPH_ROTATION_ANGLE {
DCP_GRPH_ROTATION_ANGLE_0 = 0x00000000,
DCP_GRPH_ROTATION_ANGLE_90 = 0x00000001,
DCP_GRPH_ROTATION_ANGLE_180 = 0x00000002,
DCP_GRPH_ROTATION_ANGLE_270 = 0x00000003,
} DCP_GRPH_ROTATION_ANGLE;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x00000000,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x00000001,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x00000000,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE = 0x00000001,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
typedef enum DCP_GRPH_REGAMMA_MODE {
DCP_GRPH_REGAMMA_MODE_BYPASS = 0x00000000,
DCP_GRPH_REGAMMA_MODE_SRGB = 0x00000001,
DCP_GRPH_REGAMMA_MODE_XVYCC = 0x00000002,
DCP_GRPH_REGAMMA_MODE_PROGA = 0x00000003,
DCP_GRPH_REGAMMA_MODE_PROGB = 0x00000004,
} DCP_GRPH_REGAMMA_MODE;
typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x00000000,
DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x00000001,
} DCP_ALPHA_ROUND_TRUNC_MODE;
typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x00000000,
DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x00000001,
} DCP_CURSOR_ALPHA_BLND_ENA;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x00000000,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x00000001,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x00000000,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x00000001,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x00000000,
DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x00000001,
} DCP_GRPH_SURFACE_COUNTER_EN;
typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x00000000,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x00000001,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x00000002,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x00000003,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x00000004,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x00000005,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x00000006,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x00000007,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x00000008,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x00000009,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0x0000000a,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0x0000000b,
} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x00000000,
DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x00000001,
} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR {
DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE = 0x00000000,
DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE = 0x00000001,
} DCP_GRPH_XDMA_FLIP_TYPE_CLEAR;
typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE {
DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE = 0x00000000,
DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE = 0x00000001,
} DCP_GRPH_XDMA_DRR_MODE_ENABLE;
typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE {
DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE = 0x00000000,
DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE = 0x00000001,
} DCP_GRPH_XDMA_MULTIFLIP_ENABLE;
typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK {
DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE = 0x00000000,
DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE = 0x00000001,
} DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK;
typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK {
DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE = 0x00000000,
DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE = 0x00000001,
} DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK;
typedef enum PERFCOUNTER_CVALUE_SEL {
PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
} PERFCOUNTER_CVALUE_SEL;
typedef enum PERFCOUNTER_INC_MODE {
PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
PERFCOUNTER_INC_MODE_LSB = 0x00000002,
PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
} PERFCOUNTER_INC_MODE;
typedef enum PERFCOUNTER_HW_CNTL_SEL {
PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
} PERFCOUNTER_HW_CNTL_SEL;
typedef enum PERFCOUNTER_RUNEN_MODE {
PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
} PERFCOUNTER_RUNEN_MODE;
typedef enum PERFCOUNTER_CNTOFF_START_DIS {
PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
} PERFCOUNTER_CNTOFF_START_DIS;
typedef enum PERFCOUNTER_RESTART_EN {
PERFCOUNTER_RESTART_DISABLE = 0x00000000,
PERFCOUNTER_RESTART_ENABLE = 0x00000001,
} PERFCOUNTER_RESTART_EN;
typedef enum PERFCOUNTER_INT_EN {
PERFCOUNTER_INT_DISABLE = 0x00000000,
PERFCOUNTER_INT_ENABLE = 0x00000001,
} PERFCOUNTER_INT_EN;
typedef enum PERFCOUNTER_OFF_MASK {
PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
} PERFCOUNTER_OFF_MASK;
typedef enum PERFCOUNTER_ACTIVE {
PERFCOUNTER_IS_IDLE = 0x00000000,
PERFCOUNTER_IS_ACTIVE = 0x00000001,
} PERFCOUNTER_ACTIVE;
typedef enum PERFCOUNTER_INT_TYPE {
PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
} PERFCOUNTER_INT_TYPE;
typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
} PERFCOUNTER_COUNTED_VALUE_TYPE;
typedef enum PERFCOUNTER_CNTL_SEL {
PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
} PERFCOUNTER_CNTL_SEL;
typedef enum PERFCOUNTER_CNT0_STATE {
PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT0_STATE_START = 0x00000001,
PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT0_STATE;
typedef enum PERFCOUNTER_STATE_SEL0 {
PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL0;
typedef enum PERFCOUNTER_CNT1_STATE {
PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT1_STATE_START = 0x00000001,
PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT1_STATE;
typedef enum PERFCOUNTER_STATE_SEL1 {
PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL1;
typedef enum PERFCOUNTER_CNT2_STATE {
PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT2_STATE_START = 0x00000001,
PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT2_STATE;
typedef enum PERFCOUNTER_STATE_SEL2 {
PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL2;
typedef enum PERFCOUNTER_CNT3_STATE {
PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT3_STATE_START = 0x00000001,
PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT3_STATE;
typedef enum PERFCOUNTER_STATE_SEL3 {
PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL3;
typedef enum PERFCOUNTER_CNT4_STATE {
PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT4_STATE_START = 0x00000001,
PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT4_STATE;
typedef enum PERFCOUNTER_STATE_SEL4 {
PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL4;
typedef enum PERFCOUNTER_CNT5_STATE {
PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT5_STATE_START = 0x00000001,
PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT5_STATE;
typedef enum PERFCOUNTER_STATE_SEL5 {
PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL5;
typedef enum PERFCOUNTER_CNT6_STATE {
PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT6_STATE_START = 0x00000001,
PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT6_STATE;
typedef enum PERFCOUNTER_STATE_SEL6 {
PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL6;
typedef enum PERFCOUNTER_CNT7_STATE {
PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT7_STATE_START = 0x00000001,
PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT7_STATE;
typedef enum PERFCOUNTER_STATE_SEL7 {
PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL7;
typedef enum PERFMON_STATE {
PERFMON_STATE_RESET = 0x00000000,
PERFMON_STATE_START = 0x00000001,
PERFMON_STATE_FREEZE = 0x00000002,
PERFMON_STATE_HW = 0x00000003,
} PERFMON_STATE;
typedef enum PERFMON_CNTOFF_AND_OR {
PERFMON_CNTOFF_OR = 0x00000000,
PERFMON_CNTOFF_AND = 0x00000001,
} PERFMON_CNTOFF_AND_OR;
typedef enum PERFMON_CNTOFF_INT_EN {
PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
} PERFMON_CNTOFF_INT_EN;
typedef enum PERFMON_CNTOFF_INT_TYPE {
PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
} PERFMON_CNTOFF_INT_TYPE;
typedef enum SCL_C_RAM_TAP_PAIR_IDX {
SCL_C_RAM_TAP_PAIR_ID0 = 0x00000000,
SCL_C_RAM_TAP_PAIR_ID1 = 0x00000001,
SCL_C_RAM_TAP_PAIR_ID2 = 0x00000002,
SCL_C_RAM_TAP_PAIR_ID3 = 0x00000003,
SCL_C_RAM_TAP_PAIR_ID4 = 0x00000004,
} SCL_C_RAM_TAP_PAIR_IDX;
typedef enum SCL_C_RAM_PHASE {
SCL_C_RAM_PHASE_0 = 0x00000000,
SCL_C_RAM_PHASE_1 = 0x00000001,
SCL_C_RAM_PHASE_2 = 0x00000002,
SCL_C_RAM_PHASE_3 = 0x00000003,
SCL_C_RAM_PHASE_4 = 0x00000004,
SCL_C_RAM_PHASE_5 = 0x00000005,
SCL_C_RAM_PHASE_6 = 0x00000006,
SCL_C_RAM_PHASE_7 = 0x00000007,
SCL_C_RAM_PHASE_8 = 0x00000008,
} SCL_C_RAM_PHASE;
typedef enum SCL_C_RAM_FILTER_TYPE {
SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x00000000,
SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x00000001,
SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x00000002,
SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x00000003,
} SCL_C_RAM_FILTER_TYPE;
typedef enum SCL_MODE_SEL {
SCL_MODE_RGB_BYPASS = 0x00000000,
SCL_MODE_RGB_SCALING = 0x00000001,
SCL_MODE_YCBCR_SCALING = 0x00000002,
SCL_MODE_YCBCR_BYPASS = 0x00000003,
} SCL_MODE_SEL;
typedef enum SCL_PSCL_EN {
SCL_PSCL_DISABLE = 0x00000000,
SCL_PSCL_ENANBLE = 0x00000001,
} SCL_PSCL_EN;
typedef enum SCL_V_NUM_OF_TAPS {
SCL_V_NUM_OF_TAPS_1 = 0x00000000,
SCL_V_NUM_OF_TAPS_2 = 0x00000001,
SCL_V_NUM_OF_TAPS_3 = 0x00000002,
SCL_V_NUM_OF_TAPS_4 = 0x00000003,
SCL_V_NUM_OF_TAPS_5 = 0x00000004,
SCL_V_NUM_OF_TAPS_6 = 0x00000005,
} SCL_V_NUM_OF_TAPS;
typedef enum SCL_H_NUM_OF_TAPS {
SCL_H_NUM_OF_TAPS_1 = 0x00000000,
SCL_H_NUM_OF_TAPS_2 = 0x00000001,
SCL_H_NUM_OF_TAPS_4 = 0x00000003,
SCL_H_NUM_OF_TAPS_6 = 0x00000005,
SCL_H_NUM_OF_TAPS_8 = 0x00000007,
SCL_H_NUM_OF_TAPS_10 = 0x00000009,
} SCL_H_NUM_OF_TAPS;
typedef enum SCL_BOUNDARY_MODE {
SCL_BOUNDARY_MODE_BLACK = 0x00000000,
SCL_BOUNDARY_MODE_EDGE = 0x00000001,
} SCL_BOUNDARY_MODE;
typedef enum SCL_EARLY_EOL_MOD {
SCL_EARLY_EOL_MODE_CRTC = 0x00000000,
SCL_EARLY_EOL_MODE_INTERNAL = 0x00000001,
} SCL_EARLY_EOL_MOD;
typedef enum SCL_BYPASS_MODE {
SCL_BYPASS_MODE_MC_MR = 0x00000000,
SCL_BYPASS_MODE_AC_NR = 0x00000001,
SCL_BYPASS_MODE_AC_AR = 0x00000002,
SCL_BYPASS_MODE_RESERVED = 0x00000003,
} SCL_BYPASS_MODE;
typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x00000000,
SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x00000001,
SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x00000002,
SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x00000003,
SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x00000004,
SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x00000005,
SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x00000006,
SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x00000007,
SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x00000008,
SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x00000009,
SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a,
SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b,
SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c,
SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d,
SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e,
SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f,
} SCL_V_MANUAL_REPLICATE_FACTOR;
typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x00000000,
SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x00000001,
SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x00000002,
SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x00000003,
SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x00000004,
SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x00000005,
SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x00000006,
SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x00000007,
SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x00000008,
SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x00000009,
SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a,
SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b,
SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c,
SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d,
SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e,
SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f,
} SCL_H_MANUAL_REPLICATE_FACTOR;
typedef enum SCL_V_CALC_AUTO_RATIO_EN {
SCL_V_CALC_AUTO_RATIO_DISABLE = 0x00000000,
SCL_V_CALC_AUTO_RATIO_ENABLE = 0x00000001,
} SCL_V_CALC_AUTO_RATIO_EN;
typedef enum SCL_H_CALC_AUTO_RATIO_EN {
SCL_H_CALC_AUTO_RATIO_DISABLE = 0x00000000,
SCL_H_CALC_AUTO_RATIO_ENABLE = 0x00000001,
} SCL_H_CALC_AUTO_RATIO_EN;
typedef enum SCL_H_FILTER_PICK_NEAREST {
SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x00000000,
SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x00000001,
} SCL_H_FILTER_PICK_NEAREST;
typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x00000000,
SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x00000001,
} SCL_H_2TAP_HARDCODE_COEF_EN;
typedef enum SCL_V_FILTER_PICK_NEAREST {
SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x00000000,
SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x00000001,
} SCL_V_FILTER_PICK_NEAREST;
typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x00000000,
SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x00000001,
} SCL_V_2TAP_HARDCODE_COEF_EN;
typedef enum SCL_UPDATE_TAKEN {
SCL_UPDATE_TAKEN_NO = 0x00000000,
SCL_UPDATE_TAKEN_YES = 0x00000001,
} SCL_UPDATE_TAKEN;
typedef enum SCL_UPDATE_LOCK {
SCL_UPDATE_UNLOCKED = 0x00000000,
SCL_UPDATE_LOCKED = 0x00000001,
} SCL_UPDATE_LOCK;
typedef enum SCL_COEF_UPDATE_COMPLETE {
SCL_COEF_UPDATE_NOT_COMPLETED = 0x00000000,
SCL_COEF_UPDATE_COMPLETED = 0x00000001,
} SCL_COEF_UPDATE_COMPLETE;
typedef enum SCL_HF_SHARP_SCALE_FACTOR {
SCL_HF_SHARP_SCALE_FACTOR_0 = 0x00000000,
SCL_HF_SHARP_SCALE_FACTOR_1 = 0x00000001,
SCL_HF_SHARP_SCALE_FACTOR_2 = 0x00000002,
SCL_HF_SHARP_SCALE_FACTOR_3 = 0x00000003,
SCL_HF_SHARP_SCALE_FACTOR_4 = 0x00000004,
SCL_HF_SHARP_SCALE_FACTOR_5 = 0x00000005,
SCL_HF_SHARP_SCALE_FACTOR_6 = 0x00000006,
SCL_HF_SHARP_SCALE_FACTOR_7 = 0x00000007,
} SCL_HF_SHARP_SCALE_FACTOR;
typedef enum SCL_HF_SHARP_EN {
SCL_HF_SHARP_DISABLE = 0x00000000,
SCL_HF_SHARP_ENABLE = 0x00000001,
} SCL_HF_SHARP_EN;
typedef enum SCL_VF_SHARP_SCALE_FACTOR {
SCL_VF_SHARP_SCALE_FACTOR_0 = 0x00000000,
SCL_VF_SHARP_SCALE_FACTOR_1 = 0x00000001,
SCL_VF_SHARP_SCALE_FACTOR_2 = 0x00000002,
SCL_VF_SHARP_SCALE_FACTOR_3 = 0x00000003,
SCL_VF_SHARP_SCALE_FACTOR_4 = 0x00000004,
SCL_VF_SHARP_SCALE_FACTOR_5 = 0x00000005,
SCL_VF_SHARP_SCALE_FACTOR_6 = 0x00000006,
SCL_VF_SHARP_SCALE_FACTOR_7 = 0x00000007,
} SCL_VF_SHARP_SCALE_FACTOR;
typedef enum SCL_VF_SHARP_EN {
SCL_VF_SHARP_DISABLE = 0x00000000,
SCL_VF_SHARP_ENABLE = 0x00000001,
} SCL_VF_SHARP_EN;
typedef enum SCL_ALU_DISABLE {
SCL_ALU_ENABLED = 0x00000000,
SCL_ALU_DISABLED = 0x00000001,
} SCL_ALU_DISABLE;
typedef enum SCL_HOST_CONFLICT_MASK {
SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x00000000,
SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x00000001,
} SCL_HOST_CONFLICT_MASK;
typedef enum SCL_SCL_MODE_CHANGE_MASK {
SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x00000000,
SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x00000001,
} SCL_SCL_MODE_CHANGE_MASK;
typedef enum SCLV_MODE_SEL {
SCLV_MODE_RGB_BYPASS = 0x00000000,
SCLV_MODE_RGB_SCALING = 0x00000001,
SCLV_MODE_YCBCR_SCALING = 0x00000002,
SCLV_MODE_YCBCR_BYPASS = 0x00000003,
} SCLV_MODE_SEL;
typedef enum SCLV_INTERLACE_SOURCE {
INTERLACE_SOURCE_PROGRESSIVE = 0x00000000,
INTERLACE_SOURCE_INTERLEAVE = 0x00000001,
INTERLACE_SOURCE_STACK = 0x00000002,
} SCLV_INTERLACE_SOURCE;
typedef enum SCLV_UPDATE_LOCK {
UPDATE_UNLOCKED = 0x00000000,
UPDATE_LOCKED = 0x00000001,
} SCLV_UPDATE_LOCK;
typedef enum SCLV_COEF_UPDATE_COMPLETE {
COEF_UPDATE_NOT_COMPLETE = 0x00000000,
COEF_UPDATE_COMPLETE = 0x00000001,
} SCLV_COEF_UPDATE_COMPLETE;
typedef enum DPRX_SD_PIXEL_ENCODING {
PIXEL_FORMAT_RGB_444 = 0x00000000,
PIXEL_FORMAT_YCBCR_444 = 0x00000001,
PIXEL_FORMAT_YCBCR_422 = 0x00000002,
PIXEL_FORMAT_Y_ONLY = 0x00000003,
} DPRX_SD_PIXEL_ENCODING;
typedef enum DPRX_SD_COMPONENT_DEPTH {
COMPONENT_DEPTH_6BPC = 0x00000000,
COMPONENT_DEPTH_8BPC = 0x00000001,
COMPONENT_DEPTH_10BPC = 0x00000002,
COMPONENT_DEPTH_12BPC = 0x00000003,
COMPONENT_DEPTH_16BPC = 0x00000004,
} DPRX_SD_COMPONENT_DEPTH;
typedef enum AZ_LATENCY_COUNTER_CONTROL {
AZ_LATENCY_COUNTER_NO_RESET = 0x00000000,
AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001,
} AZ_LATENCY_COUNTER_CONTROL;
typedef enum BLND_CONTROL_BLND_MODE {
BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001,
BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
} BLND_CONTROL_BLND_MODE;
typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003,
} BLND_CONTROL_BLND_STEREO_TYPE;
typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000,
BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001,
} BLND_CONTROL_BLND_STEREO_POLARITY;
typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000,
BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001,
} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003,
} BLND_CONTROL_BLND_ALPHA_MODE;
typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0x00000000,
BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 0x00000001,
} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001,
} BLND_CONTROL_BLND_MULTIPLIED_MODE;
typedef enum BLND_SM_CONTROL2_SM_MODE {
BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000,
BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
} BLND_SM_CONTROL2_SM_MODE;
typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
typedef enum BLND_CONTROL2_PTI_ENABLE {
BLND_CONTROL2_PTI_ENABLE_FALSE = 0x00000000,
BLND_CONTROL2_PTI_ENABLE_TRUE = 0x00000001,
} BLND_CONTROL2_PTI_ENABLE;
typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000,
BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001,
} BLND_DEBUG_BLND_CNV_MUX_SELECT;
typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001,
} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
typedef enum UNP_GRPH_EN {
UNP_GRPH_DISABLED = 0x00000000,
UNP_GRPH_ENABLED = 0x00000001,
} UNP_GRPH_EN;
typedef enum UNP_GRPH_DEPTH {
UNP_GRPH_8BPP = 0x00000000,
UNP_GRPH_16BPP = 0x00000001,
UNP_GRPH_32BPP = 0x00000002,
} UNP_GRPH_DEPTH;
typedef enum UNP_GRPH_NUM_BANKS {
UNP_GRPH_ADDR_SURF_2_BANK = 0x00000000,
UNP_GRPH_ADDR_SURF_4_BANK = 0x00000001,
UNP_GRPH_ADDR_SURF_8_BANK = 0x00000002,
UNP_GRPH_ADDR_SURF_16_BANK = 0x00000003,
} UNP_GRPH_NUM_BANKS;
typedef enum UNP_GRPH_BANK_WIDTH {
UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
} UNP_GRPH_BANK_WIDTH;
typedef enum UNP_GRPH_BANK_HEIGHT {
UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
} UNP_GRPH_BANK_HEIGHT;
typedef enum UNP_GRPH_TILE_SPLIT {
UNP_ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
UNP_ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
UNP_ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
UNP_ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
} UNP_GRPH_TILE_SPLIT;
typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x00000000,
UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x00000001,
} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
} UNP_GRPH_MACRO_TILE_ASPECT;
typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
UNP_GRPH_DYNAMIC_EXPANSION = 0x00000000,
UNP_GRPH_ZERO_EXPANSION = 0x00000001,
} UNP_GRPH_COLOR_EXPANSION_MODE;
typedef enum UNP_VIDEO_FORMAT {
UNP_VIDEO_FORMAT0 = 0x00000000,
UNP_VIDEO_FORMAT1 = 0x00000001,
UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x00000002,
UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x00000003,
UNP_VIDEO_FORMAT_YUV422_YCb = 0x00000004,
UNP_VIDEO_FORMAT_YUV422_YCr = 0x00000005,
UNP_VIDEO_FORMAT_YUV422_CbY = 0x00000006,
UNP_VIDEO_FORMAT_YUV422_CrY = 0x00000007,
} UNP_VIDEO_FORMAT;
typedef enum UNP_GRPH_ENDIAN_SWAP {
UNP_GRPH_ENDIAN_SWAP_NONE = 0x00000000,
UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001,
UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002,
UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x00000003,
} UNP_GRPH_ENDIAN_SWAP;
typedef enum UNP_GRPH_RED_CROSSBAR {
UNP_GRPH_RED_CROSSBAR_R_Cr = 0x00000000,
UNP_GRPH_RED_CROSSBAR_G_Y = 0x00000001,
UNP_GRPH_RED_CROSSBAR_B_Cb = 0x00000002,
UNP_GRPH_RED_CROSSBAR_A = 0x00000003,
} UNP_GRPH_RED_CROSSBAR;
typedef enum UNP_GRPH_GREEN_CROSSBAR {
UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x00000000,
UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x00000001,
UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x00000002,
UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x00000003,
} UNP_GRPH_GREEN_CROSSBAR;
typedef enum UNP_GRPH_BLUE_CROSSBAR {
UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x00000000,
UNP_GRPH_BLUE_CROSSBAR_A = 0x00000001,
UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x00000002,
UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x00000003,
} UNP_GRPH_BLUE_CROSSBAR;
typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
UNP_GRPH_UPDATE_LOCK_0 = 0x00000000,
UNP_GRPH_UPDATE_LOCK_1 = 0x00000001,
} UNP_GRPH_MODE_UPDATE_LOCKG;
typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x00000000,
UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x00000001,
} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000,
UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001,
} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000,
UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001,
} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x00000000,
UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x00000001,
} UNP_GRPH_STEREOSYNC_FLIP_EN;
typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x00000000,
UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x00000001,
UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x00000002,
UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x00000003,
} UNP_GRPH_STEREOSYNC_FLIP_MODE;
typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x00000000,
UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x00000001,
} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x00000000,
UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x00000001,
UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x00000002,
UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x00000003,
} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
UNP_GRPH_STEREOSYNC_SELECT_EN = 0x00000000,
UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x00000001,
} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
typedef enum UNP_CRC_SOURCE_SEL {
UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x00000000,
UNP_CRC_SOURCE_SEL_LOWER32 = 0x00000001,
UNP_CRC_SOURCE_SEL_RESERVED = 0x00000002,
UNP_CRC_SOURCE_SEL_LOWER16 = 0x00000003,
UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x00000004,
} UNP_CRC_SOURCE_SEL;
typedef enum UNP_CRC_LINE_SEL {
UNP_CRC_LINE_SEL_RESERVED = 0x00000000,
UNP_CRC_LINE_SEL_EVEN_ONLY = 0x00000001,
UNP_CRC_LINE_SEL_ODD_ONLY = 0x00000002,
UNP_CRC_LINE_SEL_ODD_EVEN = 0x00000003,
} UNP_CRC_LINE_SEL;
typedef enum UNP_ROTATION_ANGLE {
UNP_ROTATION_ANGLE_0 = 0x00000000,
UNP_ROTATION_ANGLE_90 = 0x00000001,
UNP_ROTATION_ANGLE_180 = 0x00000002,
UNP_ROTATION_ANGLE_270 = 0x00000003,
UNP_ROTATION_ANGLE_0m = 0x00000004,
UNP_ROTATION_ANGLE_90m = 0x00000005,
UNP_ROTATION_ANGLE_180m = 0x00000006,
UNP_ROTATION_ANGLE_270m = 0x00000007,
} UNP_ROTATION_ANGLE;
typedef enum UNP_PIXEL_DROP {
UNP_PIXEL_NO_DROP = 0x00000000,
UNP_PIXEL_DROPPING = 0x00000001,
} UNP_PIXEL_DROP;
typedef enum UNP_BUFFER_MODE {
UNP_BUFFER_MODE_LUMA = 0x00000000,
UNP_BUFFER_MODE_LUMA_CHROMA = 0x00000001,
} UNP_BUFFER_MODE;
typedef enum DP_LINK_TRAINING_COMPLETE {
DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000,
DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001,
} DP_LINK_TRAINING_COMPLETE;
typedef enum DP_EMBEDDED_PANEL_MODE {
DP_EXTERNAL_PANEL = 0x00000000,
DP_EMBEDDED_PANEL = 0x00000001,
} DP_EMBEDDED_PANEL_MODE;
typedef enum DP_PIXEL_ENCODING {
DP_PIXEL_ENCODING_RGB444 = 0x00000000,
DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
DP_PIXEL_ENCODING_RESERVED = 0x00000006,
} DP_PIXEL_ENCODING;
typedef enum DP_DYN_RANGE {
DP_DYN_VESA_RANGE = 0x00000000,
DP_DYN_CEA_RANGE = 0x00000001,
} DP_DYN_RANGE;
typedef enum DP_YCBCR_RANGE {
DP_YCBCR_RANGE_BT601_5 = 0x00000000,
DP_YCBCR_RANGE_BT709_5 = 0x00000001,
} DP_YCBCR_RANGE;
typedef enum DP_COMPONENT_DEPTH {
DP_COMPONENT_DEPTH_6BPC = 0x00000000,
DP_COMPONENT_DEPTH_8BPC = 0x00000001,
DP_COMPONENT_DEPTH_10BPC = 0x00000002,
DP_COMPONENT_DEPTH_12BPC = 0x00000003,
DP_COMPONENT_DEPTH_16BPC_RESERVED = 0x00000004,
DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
} DP_COMPONENT_DEPTH;
typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
MSA_MISC0_OVERRIDE_DISABLE = 0x00000000,
MSA_MISC0_OVERRIDE_ENABLE = 0x00000001,
} DP_MSA_MISC0_OVERRIDE_ENABLE;
typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0x00000000,
MSA_MISC1_BIT7_OVERRIDE_ENABLE = 0x00000001,
} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
typedef enum DP_UDI_LANES {
DP_UDI_1_LANE = 0x00000000,
DP_UDI_2_LANES = 0x00000001,
DP_UDI_LANES_RESERVED = 0x00000002,
DP_UDI_4_LANES = 0x00000003,
} DP_UDI_LANES;
typedef enum DP_VID_STREAM_DIS_DEFER {
DP_VID_STREAM_DIS_NO_DEFER = 0x00000000,
DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001,
DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002,
} DP_VID_STREAM_DIS_DEFER;
typedef enum DP_STEER_OVERFLOW_ACK {
DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
} DP_STEER_OVERFLOW_ACK;
typedef enum DP_STEER_OVERFLOW_MASK {
DP_STEER_OVERFLOW_MASKED = 0x00000000,
DP_STEER_OVERFLOW_UNMASK = 0x00000001,
} DP_STEER_OVERFLOW_MASK;
typedef enum DP_TU_OVERFLOW_ACK {
DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
} DP_TU_OVERFLOW_ACK;
typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0x00000000,
DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001,
} DPHY_ALT_SCRAMBLER_RESET_EN;
typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000,
DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001,
} DPHY_ALT_SCRAMBLER_RESET_SEL;
typedef enum DP_VID_TIMING_MODE {
DP_VID_TIMING_MODE_ASYNC = 0x00000000,
DP_VID_TIMING_MODE_SYNC = 0x00000001,
} DP_VID_TIMING_MODE;
typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000,
DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001,
} DP_VID_M_N_DOUBLE_BUFFER_MODE;
typedef enum DP_VID_M_N_GEN_EN {
DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000,
DP_VID_M_N_CALC_AUTO = 0x00000001,
} DP_VID_M_N_GEN_EN;
typedef enum DP_VID_M_DOUBLE_VALUE_EN {
DP_VID_M_INPUT_PIXEL_RATE = 0x00000000,
DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 0x00000001,
} DP_VID_M_DOUBLE_VALUE_EN;
typedef enum DP_VID_ENHANCED_FRAME_MODE {
VID_NORMAL_FRAME_MODE = 0x00000000,
VID_ENHANCED_MODE = 0x00000001,
} DP_VID_ENHANCED_FRAME_MODE;
typedef enum DP_VID_MSA_TOP_FIELD_MODE {
DP_TOP_FIELD_ONLY = 0x00000000,
DP_TOP_PLUS_BOTTOM_FIELD = 0x00000001,
} DP_VID_MSA_TOP_FIELD_MODE;
typedef enum DP_VID_VBID_FIELD_POL {
DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000,
DP_VID_VBID_FIELD_POL_INV = 0x00000001,
} DP_VID_VBID_FIELD_POL;
typedef enum DP_VID_STREAM_DISABLE_ACK {
ID_STREAM_DISABLE_NO_ACK = 0x00000000,
ID_STREAM_DISABLE_ACKED = 0x00000001,
} DP_VID_STREAM_DISABLE_ACK;
typedef enum DP_VID_STREAM_DISABLE_MASK {
VID_STREAM_DISABLE_MASKED = 0x00000000,
VID_STREAM_DISABLE_UNMASK = 0x00000001,
} DP_VID_STREAM_DISABLE_MASK;
typedef enum DPHY_ATEST_SEL_LANE0 {
DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000,
DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001,
} DPHY_ATEST_SEL_LANE0;
typedef enum DPHY_ATEST_SEL_LANE1 {
DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000,
DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001,
} DPHY_ATEST_SEL_LANE1;
typedef enum DPHY_ATEST_SEL_LANE2 {
DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000,
DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001,
} DPHY_ATEST_SEL_LANE2;
typedef enum DPHY_ATEST_SEL_LANE3 {
DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000,
DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001,
} DPHY_ATEST_SEL_LANE3;
typedef enum DPHY_SCRAMBLER_SEL {
DPHY_SCRAMBLER_SEL_LANE_DATA = 0x00000000,
DPHY_SCRAMBLER_SEL_DBG_DATA = 0x00000001,
} DPHY_SCRAMBLER_SEL;
typedef enum DPHY_BYPASS {
DPHY_8B10B_OUTPUT = 0x00000000,
DPHY_DBG_OUTPUT = 0x00000001,
} DPHY_BYPASS;
typedef enum DPHY_SKEW_BYPASS {
DPHY_WITH_SKEW = 0x00000000,
DPHY_NO_SKEW = 0x00000001,
} DPHY_SKEW_BYPASS;
typedef enum DPHY_TRAINING_PATTERN_SEL {
DPHY_TRAINING_PATTERN_1 = 0x00000000,
DPHY_TRAINING_PATTERN_2 = 0x00000001,
DPHY_TRAINING_PATTERN_3 = 0x00000002,
DPHY_TRAINING_PATTERN_4 = 0x00000003,
} DPHY_TRAINING_PATTERN_SEL;
typedef enum DPHY_8B10B_RESET {
DPHY_8B10B_NOT_RESET = 0x00000000,
DPHY_8B10B_RESETET = 0x00000001,
} DPHY_8B10B_RESET;
typedef enum DP_DPHY_8B10B_EXT_DISP {
DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000,
DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001,
} DP_DPHY_8B10B_EXT_DISP;
typedef enum DPHY_8B10B_CUR_DISP {
DPHY_8B10B_CUR_DISP_ZERO = 0x00000000,
DPHY_8B10B_CUR_DISP_ONE = 0x00000001,
} DPHY_8B10B_CUR_DISP;
typedef enum DPHY_PRBS_EN {
DPHY_PRBS_DISABLE = 0x00000000,
DPHY_PRBS_ENABLE = 0x00000001,
} DPHY_PRBS_EN;
typedef enum DPHY_PRBS_SEL {
DPHY_PRBS7_SELECTED = 0x00000000,
DPHY_PRBS23_SELECTED = 0x00000001,
DPHY_PRBS11_SELECTED = 0x00000002,
} DPHY_PRBS_SEL;
typedef enum DPHY_SCRAMBLER_DIS {
DPHY_SCR_ENABLED = 0x00000000,
DPHY_SCR_DISABLED = 0x00000001,
} DPHY_SCRAMBLER_DIS;
typedef enum DPHY_SCRAMBLER_ADVANCE {
DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0x00000000,
DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 0x00000001,
} DPHY_SCRAMBLER_ADVANCE;
typedef enum DPHY_SCRAMBLER_KCODE {
DPHY_SCRAMBLER_KCODE_DISABLED = 0x00000000,
DPHY_SCRAMBLER_KCODE_ENABLED = 0x00000001,
} DPHY_SCRAMBLER_KCODE;
typedef enum DPHY_LOAD_BS_COUNT_START {
DPHY_LOAD_BS_COUNT_STARTED = 0x00000000,
DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001,
} DPHY_LOAD_BS_COUNT_START;
typedef enum DPHY_CRC_EN {
DPHY_CRC_DISABLED = 0x00000000,
DPHY_CRC_ENABLED = 0x00000001,
} DPHY_CRC_EN;
typedef enum DPHY_CRC_CONT_EN {
DPHY_CRC_ONE_SHOT = 0x00000000,
DPHY_CRC_CONTINUOUS = 0x00000001,
} DPHY_CRC_CONT_EN;
typedef enum DPHY_CRC_FIELD {
DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000,
DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001,
} DPHY_CRC_FIELD;
typedef enum DPHY_CRC_SEL {
DPHY_CRC_LANE0_SELECTED = 0x00000000,
DPHY_CRC_LANE1_SELECTED = 0x00000001,
DPHY_CRC_LANE2_SELECTED = 0x00000002,
DPHY_CRC_LANE3_SELECTED = 0x00000003,
} DPHY_CRC_SEL;
typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000,
DPHY_FAST_TRAINING_CAPABLE = 0x00000001,
} DPHY_RX_FAST_TRAINING_CAPABLE;
typedef enum DP_SEC_COLLISION_ACK {
DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000,
DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001,
} DP_SEC_COLLISION_ACK;
typedef enum DP_SEC_AUDIO_MUTE {
DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000,
DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001,
} DP_SEC_AUDIO_MUTE;
typedef enum DP_SEC_TIMESTAMP_MODE {
DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000,
DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001,
} DP_SEC_TIMESTAMP_MODE;
typedef enum DP_SEC_ASP_PRIORITY {
DP_SEC_ASP_LOW_PRIORITY = 0x00000000,
DP_SEC_ASP_HIGH_PRIORITY = 0x00000001,
} DP_SEC_ASP_PRIORITY;
typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000,
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
typedef enum DP_MSE_SAT_UPDATE_ACT {
DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000,
DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001,
DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002,
} DP_MSE_SAT_UPDATE_ACT;
typedef enum DP_MSE_LINK_LINE {
DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000,
DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001,
DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002,
DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003,
} DP_MSE_LINK_LINE;
typedef enum DP_MSE_BLANK_CODE {
DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000,
DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001,
} DP_MSE_BLANK_CODE;
typedef enum DP_MSE_TIMESTAMP_MODE {
DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000,
DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001,
} DP_MSE_TIMESTAMP_MODE;
typedef enum DP_MSE_ZERO_ENCODER {
DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000,
DP_MSE_ZERO_FE_ENCODER = 0x00000001,
} DP_MSE_ZERO_ENCODER;
typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x00000000,
DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x00000001,
} DP_MSE_OUTPUT_DPDBG_DATA;
typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
DP_DPHY_HBR2_PASS_THROUGH = 0x00000000,
DP_DPHY_HBR2_PATTERN_1 = 0x00000001,
DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002,
DP_DPHY_HBR2_PATTERN_3 = 0x00000003,
DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006,
} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000,
DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001,
} DPHY_CRC_MST_PHASE_ERROR_ACK;
typedef enum DPHY_SW_FAST_TRAINING_START {
DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000,
DPHY_SW_FAST_TRAINING_STARTED = 0x00000001,
} DPHY_SW_FAST_TRAINING_START;
typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000,
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001,
} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000,
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001,
} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000,
DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001,
} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000,
MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001,
} DP_MSA_V_TIMING_OVERRIDE_EN;
typedef enum DP_SEC_GSP0_PRIORITY {
SEC_GSP0_PRIORITY_LOW = 0x00000000,
SEC_GSP0_PRIORITY_HIGH = 0x00000001,
} DP_SEC_GSP0_PRIORITY;
typedef enum DP_SEC_GSP0_SEND {
NOT_SENT = 0x00000000,
FORCE_SENT = 0x00000001,
} DP_SEC_GSP0_SEND;
typedef enum COL_MAN_UPDATE_LOCK {
COL_MAN_UPDATE_UNLOCKED = 0x00000000,
COL_MAN_UPDATE_LOCKED = 0x00000001,
} COL_MAN_UPDATE_LOCK;
typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
COL_MAN_MULTIPLE_UPDATE = 0x00000000,
COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x00000001,
} COL_MAN_DISABLE_MULTIPLE_UPDATE;
typedef enum COL_MAN_INPUTCSC_MODE {
INPUTCSC_MODE_BYPASS = 0x00000000,
INPUTCSC_MODE_A = 0x00000001,
INPUTCSC_MODE_B = 0x00000002,
INPUTCSC_MODE_UNITY = 0x00000003,
} COL_MAN_INPUTCSC_MODE;
typedef enum COL_MAN_INPUTCSC_TYPE {
INPUTCSC_TYPE_12_0 = 0x00000000,
INPUTCSC_TYPE_10_2 = 0x00000001,
INPUTCSC_TYPE_8_4 = 0x00000002,
} COL_MAN_INPUTCSC_TYPE;
typedef enum COL_MAN_INPUTCSC_CONVERT {
INPUTCSC_ROUND = 0x00000000,
INPUTCSC_TRUNCATE = 0x00000001,
} COL_MAN_INPUTCSC_CONVERT;
typedef enum COL_MAN_PRESCALE_MODE {
PRESCALE_MODE_BYPASS = 0x00000000,
PRESCALE_MODE_PROGRAM = 0x00000001,
PRESCALE_MODE_UNITY = 0x00000002,
} COL_MAN_PRESCALE_MODE;
typedef enum COL_MAN_INPUT_GAMMA_MODE {
INGAMMA_MODE_BYPASS = 0x00000000,
INGAMMA_MODE_FIX = 0x00000001,
INGAMMA_MODE_FLOAT = 0x00000002,
} COL_MAN_INPUT_GAMMA_MODE;
typedef enum COL_MAN_OUTPUT_CSC_MODE {
COL_MAN_OUTPUT_CSC_BYPASS = 0x00000000,
COL_MAN_OUTPUT_CSC_RGB = 0x00000001,
COL_MAN_OUTPUT_CSC_YCrCb601 = 0x00000002,
COL_MAN_OUTPUT_CSC_YCrCb709 = 0x00000003,
COL_MAN_OUTPUT_CSC_A = 0x00000004,
COL_MAN_OUTPUT_CSC_B = 0x00000005,
COL_MAN_OUTPUT_CSC_UNITY = 0x00000006,
} COL_MAN_OUTPUT_CSC_MODE;
typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
DENORM_CLAMP_MODE_UNITY = 0x00000000,
DENORM_CLAMP_MODE_8 = 0x00000001,
DENORM_CLAMP_MODE_10 = 0x00000002,
DENORM_CLAMP_MODE_12 = 0x00000003,
} COL_MAN_DENORM_CLAMP_CONTROL;
typedef enum COL_MAN_REGAMMA_MODE_CONTROL {
COL_MAN_REGAMMA_MODE_BYPASS = 0x00000000,
COL_MAN_REGAMMA_MODE_ROM_A = 0x00000001,
COL_MAN_REGAMMA_MODE_ROM_B = 0x00000002,
COL_MAN_REGAMMA_MODE_A = 0x00000003,
COL_MAN_REGAMMA_MODE_B = 0x00000004,
} COL_MAN_REGAMMA_MODE_CONTROL;
typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
CM_GLOBAL_PASSTHROUGH_DISBALE = 0x00000000,
CM_GLOBAL_PASSTHROUGH_ENABLE = 0x00000001,
} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
typedef enum COL_MAN_DEGAMMA_MODE {
DEGAMMA_MODE_BYPASS = 0x00000000,
DEGAMMA_MODE_A = 0x00000001,
DEGAMMA_MODE_B = 0x00000002,
} COL_MAN_DEGAMMA_MODE;
typedef enum COL_MAN_GAMUT_REMAP_MODE {
GAMUT_REMAP_MODE_BYPASS = 0x00000000,
GAMUT_REMAP_MODE_1 = 0x00000001,
GAMUT_REMAP_MODE_2 = 0x00000002,
GAMUT_REMAP_MODE_3 = 0x00000003,
} COL_MAN_GAMUT_REMAP_MODE;
typedef enum DP_AUX_CONTROL_HPD_SEL {
DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000,
DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001,
DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002,
DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003,
DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004,
DP_AUX_CONTROL_HPD6_SELECTED = 0x00000005,
} DP_AUX_CONTROL_HPD_SEL;
typedef enum DP_AUX_CONTROL_TEST_MODE {
DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000,
DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001,
} DP_AUX_CONTROL_TEST_MODE;
typedef enum DP_AUX_SW_CONTROL_SW_GO {
DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000,
DP_AUX_SW_CONTROL_SW__GO = 0x00000001,
} DP_AUX_SW_CONTROL_SW_GO;
typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000,
DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001,
} DP_AUX_SW_CONTROL_LS_READ_TRIG;
typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000,
DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001,
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002,
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003,
} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000,
DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001,
} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001,
} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
typedef enum DP_AUX_INT_ACK {
DP_AUX_INT__NOT_ACK = 0x00000000,
DP_AUX_INT__ACK = 0x00000001,
} DP_AUX_INT_ACK;
typedef enum DP_AUX_LS_UPDATE_ACK {
DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000,
DP_AUX_INT_LS_UPDATE_ACK = 0x00000001,
} DP_AUX_LS_UPDATE_ACK;
typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000,
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001,
} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x00000000,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x00000001,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x00000002,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x00000003,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x00000004,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x00000005,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x00000006,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x00000007,
} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007,
} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007,
} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x00000000,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x00000001,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x00000002,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x00000003,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x00000004,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x00000005,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x00000006,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x00000007,
} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007,
} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000,
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001,
} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000,
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001,
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002,
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003,
} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
typedef enum DP_AUX_ERR_OCCURRED_ACK {
DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000,
DP_AUX_ERR_OCCURRED__ACK = 0x00000001,
} DP_AUX_ERR_OCCURRED_ACK;
typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000,
DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001,
} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001,
} DP_AUX_DEFINITE_ERR_REACHED_ACK;
typedef enum DP_AUX_RESET {
DP_AUX_RESET_DEASSERTED = 0x00000000,
DP_AUX_RESET_ASSERTED = 0x00000001,
} DP_AUX_RESET;
typedef enum DP_AUX_RESET_DONE {
DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000,
DP_AUX_RESET_SEQUENCE_DONE = 0x00000001,
} DP_AUX_RESET_DONE;
typedef enum DSI_COMMAND_MODE_SRC_FORMAT {
DSI_COMMAND_SRC_FORMAT_RGB8BIT = 0x00000002,
DSI_COMMAND_SRC_FORMAT_RGB332 = 0x00000003,
DSI_COMMAND_SRC_FORMAT_RGB444 = 0x00000004,
DSI_COMMAND_SRC_FORMAT_RGB555 = 0x00000005,
DSI_COMMAND_SRC_FORMAT_RGB565 = 0x00000006,
DSI_COMMAND_SRC_FORMAT_RGB888 = 0x00000008,
} DSI_COMMAND_MODE_SRC_FORMAT;
typedef enum DSI_COMMAND_MODE_DST_FORMAT {
DSI_COMMAND_DST_FORMAT_RGB111 = 0x00000000,
DSI_COMMAND_DST_FORMAT_RGB332 = 0x00000003,
DSI_COMMAND_DST_FORMAT_RGB444 = 0x00000004,
DSI_COMMAND_DST_FORMAT_RGB565 = 0x00000006,
DSI_COMMAND_DST_FORMAT_RGB666 = 0x00000007,
DSI_COMMAND_DST_FORMAT_RGB888 = 0x00000008,
} DSI_COMMAND_MODE_DST_FORMAT;
typedef enum DSI_FLAG_CLR {
DSI_FLAG_NO_CLEAR = 0x00000000,
DSI_FLAG_CLEAR = 0x00000001,
} DSI_FLAG_CLR;
typedef enum DSI_BIT_SWAP {
DSI_BIT_SWAP_DISABLE = 0x00000000,
DSI_BIT_SWAP_ENABLE = 0x00000001,
} DSI_BIT_SWAP;
typedef enum DSI_CLK_GATING {
DSI_CLK_GATING_ENABLE = 0x00000000,
DSI_CLK_GATING_DISABLE = 0x00000001,
} DSI_CLK_GATING;
typedef enum DSI_LANE_ULPS_REQUEST {
DSI_LANE_ULPS_REQUEST_DEASSERT = 0x00000000,
DSI_LANE_ULPS_REQUEST_ASSERT = 0x00000001,
} DSI_LANE_ULPS_REQUEST;
typedef enum DSI_LANE_ULPS_EXIT {
DSI_LANE_ULPS_EXIT_DEASSERT = 0x00000000,
DSI_LANE_ULPS_EXIT_ASSERT = 0x00000001,
} DSI_LANE_ULPS_EXIT;
typedef enum DSI_LANE_FORCE_TX_STOP {
DSI_LANE_FORCE_TX_STOP_DEASSERT = 0x00000000,
DSI_LANE_FORCE_TX_STOP_ASSERT = 0x00000001,
} DSI_LANE_FORCE_TX_STOP;
typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST {
DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT = 0x00000000,
DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT = 0x00000001,
} DSI_CLOCK_LANE_HS_FORCE_REQUEST;
typedef enum DSI_CONTROLLER_EN {
DSI_CONTROLLER_DISABLE = 0x00000000,
DSI_CONTROLLER_ENABLE = 0x00000001,
} DSI_CONTROLLER_EN;
typedef enum DSI_VIDEO_MODE_EN {
DSI_VIDEO_MODE_DISABLE = 0x00000000,
DSI_VIDEO_MODE_ENABLE = 0x00000001,
} DSI_VIDEO_MODE_EN;
typedef enum DSI_CMD_MODE_EN {
DSI_CMD_MODE_DISABLE = 0x00000000,
DSI_CMD_MODE_ENABLE = 0x00000001,
} DSI_CMD_MODE_EN;
typedef enum DSI_DATA_LANE0_EN {
DSI_DATA_LANE0_DISABLE = 0x00000000,
DSI_DATA_LANE0_ENABLE = 0x00000001,
} DSI_DATA_LANE0_EN;
typedef enum DSI_DATA_LANE1_EN {
DSI_DATA_LANE1_DISABLE = 0x00000000,
DSI_DATA_LANE1_ENABLE = 0x00000001,
} DSI_DATA_LANE1_EN;
typedef enum DSI_DATA_LANE2_EN {
DSI_DATA_LANE2_DISABLE = 0x00000000,
DSI_DATA_LANE2_ENABLE = 0x00000001,
} DSI_DATA_LANE2_EN;
typedef enum DSI_DATA_LANE3_EN {
DSI_DATA_LANE3_DISABLE = 0x00000000,
DSI_DATA_LANE3_ENABLE = 0x00000001,
} DSI_DATA_LANE3_EN;
typedef enum DSI_CLOCK_LANE_EN {
DSI_CLOCK_LANE_DISABLE = 0x00000000,
DSI_CLOCK_LANE_ENABLE = 0x00000001,
} DSI_CLOCK_LANE_EN;
typedef enum DSI_PHY_DATA_LANE0_EN {
DSI_PHY_DATA_LANE0_DISABLE = 0x00000000,
DSI_PHY_DATA_LANE0_ENABLE = 0x00000001,
} DSI_PHY_DATA_LANE0_EN;
typedef enum DSI_PHY_DATA_LANE1_EN {
DSI_PHY_DATA_LANE1_DISABLE = 0x00000000,
DSI_PHY_DATA_LANE1_ENABLE = 0x00000001,
} DSI_PHY_DATA_LANE1_EN;
typedef enum DSI_PHY_DATA_LANE2_EN {
DSI_PHY_DATA_LANE2_DISABLE = 0x00000000,
DSI_PHY_DATA_LANE2_ENABLE = 0x00000001,
} DSI_PHY_DATA_LANE2_EN;
typedef enum DSI_PHY_DATA_LANE3_EN {
DSI_PHY_DATA_LANE3_DISABLE = 0x00000000,
DSI_PHY_DATA_LANE3_ENABLE = 0x00000001,
} DSI_PHY_DATA_LANE3_EN;
typedef enum DSI_RESET_DISPCLK {
DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000000,
DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000001,
} DSI_RESET_DISPCLK;
typedef enum DSI_RESET_DSICLK {
DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000000,
DSI_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000001,
} DSI_RESET_DSICLK;
typedef enum DSI_RESET_BYTECLK {
DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000000,
DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000001,
} DSI_RESET_BYTECLK;
typedef enum DSI_RESET_ESCCLK {
DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000000,
DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000001,
} DSI_RESET_ESCCLK;
typedef enum DSI_CRTC_SEL {
DSI_GET_PIXEL_STREAM_FROM_FMT0 = 0x00000000,
DSI_GET_PIXEL_STREAM_FROM_FMT1 = 0x00000001,
DSI_GET_PIXEL_STREAM_FROM_FMT2 = 0x00000002,
DSI_GET_PIXEL_STREAM_FROM_FMT3 = 0x00000003,
DSI_GET_PIXEL_STREAM_FROM_FMT4 = 0x00000004,
DSI_GET_PIXEL_STREAM_FROM_FMT5 = 0x00000005,
} DSI_CRTC_SEL;
typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP {
DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP = 0x00000000,
DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP = 0x00000001,
} DSI_PACKET_BYTE_MSB_LSB_FLIP;
typedef enum DSI_VIDEO_MODE_DST_FORMAT {
DSI_VIDEO_DST_FORMAT_RGB565 = 0x00000000,
DSI_VIDEO_DST_FORMAT_RGB666_PACKED = 0x00000001,
DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 0x00000002,
DSI_VIDEO_DST_FORMAT_RGB888 = 0x00000003,
} DSI_VIDEO_MODE_DST_FORMAT;
typedef enum DSI_VIDEO_TRAFFIC_MODE {
DSI_TRAFFIC_MODE_SYNC_PULSES = 0x00000000,
DSI_TRAFFIC_MODE_SYNC_EVENTS = 0x00000001,
DSI_TRAFFIC_MODE_BURST = 0x00000002,
DSI_TRAFFIC_MODE_RESERVED = 0x00000003,
} DSI_VIDEO_TRAFFIC_MODE;
typedef enum DSI_VIDEO_BLLP_PWR_MODE {
DSI_VIDEO_BLLP_PWR_MODE_HS = 0x00000000,
DSI_VIDEO_BLLP_PWR_MODE_LP = 0x00000001,
} DSI_VIDEO_BLLP_PWR_MODE;
typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE {
DSI_VIDEO_EOF_BLLP_PWR_MODE_HS = 0x00000000,
DSI_VIDEO_EOF_BLLP_PWR_MODE_LP = 0x00000001,
} DSI_VIDEO_EOF_BLLP_PWR_MODE;
typedef enum DSI_VIDEO_PWR_MODE {
DSI_VIDEO_PWR_MODE_HS = 0x00000000,
DSI_VIDEO_PWR_MODE_LP = 0x00000001,
} DSI_VIDEO_PWR_MODE;
typedef enum DSI_VIDEO_PULSE_MODE_OPT {
PULSE_MODE_OPT_NO_HSA = 0x00000000,
PULSE_MODE_OPT_SEND = 0x00000001,
} DSI_VIDEO_PULSE_MODE_OPT;
typedef enum DSI_RGB_SWAP {
DSI_SWAP_RGB = 0x00000000,
DSI_SWAP_RBG = 0x00000001,
DSI_SWAP_BGR = 0x00000002,
DSI_SWAP_BRG = 0x00000003,
DSI_SWAP_GRB = 0x00000004,
DSI_SWAP_GBR = 0x00000005,
} DSI_RGB_SWAP;
typedef enum DSI_CMD_PACKET_TYPE {
DSI_CMD_PACKET_TYPE_SHORT = 0x00000000,
DSI_CMD_PACKET_TYPE_LONG = 0x00000001,
} DSI_CMD_PACKET_TYPE;
typedef enum DSI_CMD_PWR_MODE {
DSI_CMD_PWR_MODE_HS = 0x00000000,
DSI_CMD_PWR_MODE_LP = 0x00000001,
} DSI_CMD_PWR_MODE;
typedef enum DSI_CMD_EMBEDDED_MODE {
CMD_EMBEDDED_MODE_DISABLE = 0x00000000,
CMD_EMBEDDED_MODE_ENABLE = 0x00000001,
} DSI_CMD_EMBEDDED_MODE;
typedef enum DSI_CMD_ORDER {
DSI_CMD_ORDER_COMMAND_FIRST = 0x00000000,
DSI_CMD_ORDER_DATA_FIRST = 0x00000001,
} DSI_CMD_ORDER;
typedef enum DSI_DATA_BUFFER_ID {
DSI_DATA_BUFFER_OFFSET0 = 0x00000000,
DSI_DATA_BUFFER_OFFSET1 = 0x00000001,
} DSI_DATA_BUFFER_ID;
typedef enum DSI_DWORD_BYTE_SWAP {
DWORD_BYTE_SWAP_NO_SWAP = 0x00000000,
DWORD_BYTE_SWAP_BYTE_SWAP = 0x00000001,
DWORD_BYTE_SWAP_WORD_SWAP = 0x00000002,
DWORD_BYTE_SWAP_BOTH_SWAP = 0x00000003,
} DSI_DWORD_BYTE_SWAP;
typedef enum DSI_INSERT_DCS_COMMAND {
DSI_INSERT_DCS_COMMAND_DISABLE = 0x00000000,
DSI_INSERT_DCS_COMMAND_ENABLE = 0x00000001,
} DSI_INSERT_DCS_COMMAND;
typedef enum DSI_DMAFIFO_WRITE_WATERMARK {
DSI_DMAFIFO_WRITE_WATERMARK_HALF = 0x00000000,
DSI_DMAFIFO_WRITE_WATERMARK_FOURTH = 0x00000001,
DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH = 0x00000002,
DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH = 0x00000003,
} DSI_DMAFIFO_WRITE_WATERMARK;
typedef enum DSI_DMAFIFO_READ_WATERMARK {
DSI_DMAFIFO_READ_WATERMARK_HALF = 0x00000000,
DSI_DMAFIFO_READ_WATERMARK_FOURTH = 0x00000001,
DSI_DMAFIFO_READ_WATERMARK_EIGHTH = 0x00000002,
DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH = 0x00000003,
} DSI_DMAFIFO_READ_WATERMARK;
typedef enum DSI_USE_DENG_LENGTH {
DSI_USE_DENG_LENGTH_DISABLE = 0x00000000,
DSI_USE_DENG_LENGTH_ENABLE = 0x00000001,
} DSI_USE_DENG_LENGTH;
typedef enum DSI_COMMAND_TRIGGER_MODE {
DSI_COMMAND_TRIGGER_MODE_AUTO = 0x00000000,
DSI_COMMAND_TRIGGER_MODE_MANUAL = 0x00000001,
} DSI_COMMAND_TRIGGER_MODE;
typedef enum DSI_COMMAND_TRIGGER_SEL {
DSI_COMMAND_TRIGGER_SEL_NONE = 0x00000000,
DSI_COMMAND_TRIGGER_SEL_CRTC = 0x00000001,
DSI_COMMAND_TRIGGER_SEL_TE = 0x00000002,
DSI_COMMAND_TRIGGER_SEL_HW = 0x00000003,
} DSI_COMMAND_TRIGGER_SEL;
typedef enum DSI_HW_SOURCE_SEL {
HW_SOURCE_SEL_NONE = 0x00000000,
HW_SOURCE_SEL_DSC_VUP = 0x00000001,
HW_SOURCE_SEL_DSC_VLP = 0x00000002,
HW_SOURCE_SEL_DSC_JPEG = 0x00000003,
} DSI_HW_SOURCE_SEL;
typedef enum DSI_COMMAND_TRIGGER_ORDER {
DSI_COMMAND_TRIGGER_ORDER_DMA = 0x00000000,
DSI_COMMAND_TRIGGER_ORDER_DENG = 0x00000001,
} DSI_COMMAND_TRIGGER_ORDER;
typedef enum DSI_TE_SRC_SEL {
DSI_TE_SEL_LINK = 0x00000000,
DSI_TE_SEL_PIN = 0x00000001,
} DSI_TE_SRC_SEL;
typedef enum DSI_EXT_TE_MUX {
DSI_XT_TE_MUX_LCDD17 = 0x00000000,
DSI_XT_TE_MUX_DCLK = 0x00000001,
DSI_XT_TE_MUX_SS = 0x00000002,
DSI_XT_TE_MUX_GCLK = 0x00000003,
DSI_XT_TE_MUX_GOE = 0x00000004,
DSI_XT_TE_MUX_DINV = 0x00000005,
DSI_XT_TE_MUX_FRAME = 0x00000006,
DSI_XT_TE_MUX_GPIO4 = 0x00000007,
DSI_XT_TE_MUX_GPIO5 = 0x00000008,
} DSI_EXT_TE_MUX;
typedef enum DSI_EXT_TE_MODE {
DSI_EXT_TE_MODE_VSYNC_EDGE = 0x00000000,
DSI_EXT_TE_MODE_VSYNC_WIDTH = 0x00000001,
DSI_EXT_TE_MODE_HVSYNC_EDGE = 0x00000002,
DSI_EXT_TE_MODE_HVSYNC_WIDTH = 0x00000003,
} DSI_EXT_TE_MODE;
typedef enum DSI_EXT_RESET_POL {
DSI_EXT_RESET_POL_HIGH = 0x00000000,
DSI_EXT_RESET_POL_LOW = 0x00000001,
} DSI_EXT_RESET_POL;
typedef enum DSI_EXT_TE_POL {
DSI_EXT_TE_POL_RISING = 0x00000000,
DSI_EXT_TE_POL_FALLING = 0x00000001,
} DSI_EXT_TE_POL;
typedef enum DSI_RESET_PANEL {
DSI_RESET_PANEL_DEASSERT = 0x00000000,
DSI_RESET_PANEL_ASSERT = 0x00000001,
} DSI_RESET_PANEL;
typedef enum DSI_CRC_ENABLE {
DSI_CRC_CAL_DISABLE = 0x00000000,
DSI_CRC_CAL_ENABLE = 0x00000001,
} DSI_CRC_ENABLE;
typedef enum DSI_TX_EOT_APPEND {
DSI_TX_EOT_APPEND_DISABLE = 0x00000000,
DSI_TX_EOT_APPEND_ENABLE = 0x00000001,
} DSI_TX_EOT_APPEND;
typedef enum DSI_RX_EOT_IGNORE {
DSI_RX_EOT_IGNORE_DISABLE = 0x00000000,
DSI_RX_EOT_IGNORE_ENABLE = 0x00000001,
} DSI_RX_EOT_IGNORE;
typedef enum DSI_MIPI_BIST_RESET {
DSI_MIPI_BIST_RESET_DEASSERT = 0x00000000,
DSI_MIPI_BIST_RESET_ASSERT = 0x00000001,
} DSI_MIPI_BIST_RESET;
typedef enum DSI_MIPI_BIST_VIDEO_FRMT {
DSI_MIPI_BIST_VIDEO_FRMT_YUV422 = 0x00000000,
DSI_MIPI_BIST_VIDEO_FRMT_RAW8 = 0x00000001,
} DSI_MIPI_BIST_VIDEO_FRMT;
typedef enum DSI_MIPI_BIST_START {
DSI_MIPI_BIST_START_DEASSERT = 0x00000000,
DSI_MIPI_BIST_START_ASSERT = 0x00000001,
} DSI_MIPI_BIST_START;
typedef enum DSI_DBG_CLK_SEL {
DSI_TEST_CLK_SEL_DISPCLK_P = 0x00000000,
DSI_TEST_CLK_SEL_DISPCLK_G = 0x00000001,
DSI_TEST_CLK_SEL_DISPCLK_R = 0x00000002,
DSI_TEST_CLK_SEL_ESCCLK_G = 0x00000003,
DSI_TEST_CLK_SEL_BYTECLK_G = 0x00000004,
DSI_TEST_CLK_SEL_DSICLK_P = 0x00000005,
DSI_TEST_CLK_SEL_DSICLK_R = 0x00000006,
DSI_TEST_CLK_SEL_DSICLK_G = 0x00000007,
DSI_TEST_CLK_SEL_DSICLK_TRN = 0x00000008,
} DSI_DBG_CLK_SEL;
typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL {
DSI_DENG_FIFO_LEVEL_OVERWRITE = 0x00000000,
DSI_DENG_FIFO_LEVEL_CAL_AVERAGE = 0x00000001,
} DSI_DENG_FIFO_USE_OVERWRITE_LEVEL;
typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE {
DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT = 0x00000000,
DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT = 0x00000001,
} DSI_DENG_FIFO_FORCE_RECAL_AVERAGE;
typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX {
DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT = 0x00000000,
DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT = 0x00000001,
} DSI_DENG_FIFO_FORCE_RECOMP_MINMAX;
typedef enum DSI_DENG_FIFO_START {
DSI_DENG_FIFO_START_DEASSERT = 0x00000000,
DSI_DENG_FIFO_START_ASSERT = 0x00000001,
} DSI_DENG_FIFO_START;
typedef enum DSI_USE_CMDFIFO {
DSI_CMD_USE_DMAFIFO = 0x00000000,
DSI_CMD_USE_CMDFIFO = 0x00000001,
} DSI_USE_CMDFIFO;
typedef enum DSI_CRTC_FREEZE_TRIG {
DSI_CRTC_FREEZE_TRIG_DEASSERT = 0x00000000,
DSI_CRTC_FREEZE_TRIG_ASSERT = 0x00000001,
} DSI_CRTC_FREEZE_TRIG;
typedef enum DSI_PERF_LATENCY_SEL {
DSI_PERF_LATENCY_SEL_DATA_LANE0 = 0x00000000,
DSI_PERF_LATENCY_SEL_DATA_LANE1 = 0x00000001,
DSI_PERF_LATENCY_SEL_DATA_LANE2 = 0x00000002,
DSI_PERF_LATENCY_SEL_DATA_LANE3 = 0x00000003,
} DSI_PERF_LATENCY_SEL;
typedef enum DSI_DEBUG_DSICLK_SEL {
DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE = 0x00000000,
DSI_DEBUG_DSICLK_SEL_CMD_ENGINE = 0x00000001,
DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO = 0x00000002,
DSI_DEBUG_DSICLK_SEL_CMDFIFO = 0x00000003,
DSI_DEBUG_DSICLK_SEL_CMDBUFFER = 0x00000004,
DSI_DEBUG_DSICLK_SEL_AFIFO = 0x00000005,
DSI_DEBUG_DSICLK_SEL_LANECTRL = 0x00000006,
} DSI_DEBUG_DSICLK_SEL;
typedef enum DSI_DEBUG_BYTECLK_SEL {
DSI_DEBUG_BYTECLK_SEL_AFIFO = 0x00000000,
DSI_DEBUG_BYTECLK_SEL_LANEFIFO0 = 0x00000001,
DSI_DEBUG_BYTECLK_SEL_LANEFIFO1 = 0x00000002,
DSI_DEBUG_BYTECLK_SEL_LANEFIFO2 = 0x00000003,
DSI_DEBUG_BYTECLK_SEL_LANEFIFO3 = 0x00000004,
DSI_DEBUG_BYTECLK_SEL_LANEBUF0 = 0x00000005,
DSI_DEBUG_BYTECLK_SEL_LANEBUF1 = 0x00000006,
DSI_DEBUG_BYTECLK_SEL_LANEBUF2 = 0x00000007,
DSI_DEBUG_BYTECLK_SEL_LANEBUF3 = 0x00000008,
DSI_DEBUG_BYTECLK_SEL_PINGPONG0 = 0x00000009,
DSI_DEBUG_BYTECLK_SEL_PINGPONG1 = 0x0000000a,
DSI_DEBUG_BYTECLK_SEL_PINGPING2 = 0x0000000b,
DSI_DEBUG_BYTECLK_SEL_PINGPING3 = 0x0000000c,
DSI_DEBUG_BYTECLK_SEL_EOT = 0x0000000d,
DSI_DEBUG_BYTECLK_SEL_LANECTRL = 0x0000000e,
} DSI_DEBUG_BYTECLK_SEL;
typedef enum DCIOCHIP_HPD_SEL {
DCIOCHIP_HPD_SEL_ASYNC = 0x00000000,
DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001,
} DCIOCHIP_HPD_SEL;
typedef enum DCIOCHIP_PAD_MODE {
DCIOCHIP_PAD_MODE_DDC = 0x00000000,
DCIOCHIP_PAD_MODE_DP = 0x00000001,
} DCIOCHIP_PAD_MODE;
typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x00000000,
DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x00000001,
} DCIOCHIP_AUXSLAVE_PAD_MODE;
typedef enum DCIOCHIP_INVERT {
DCIOCHIP_POL_NON_INVERT = 0x00000000,
DCIOCHIP_POL_INVERT = 0x00000001,
} DCIOCHIP_INVERT;
typedef enum DCIOCHIP_PD_EN {
DCIOCHIP_PD_EN_NOTALLOW = 0x00000000,
DCIOCHIP_PD_EN_ALLOW = 0x00000001,
} DCIOCHIP_PD_EN;
typedef enum DCIOCHIP_GPIO_MASK_EN {
DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000,
DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001,
} DCIOCHIP_GPIO_MASK_EN;
typedef enum DCIOCHIP_MASK {
DCIOCHIP_MASK_DISABLE = 0x00000000,
DCIOCHIP_MASK_ENABLE = 0x00000001,
} DCIOCHIP_MASK;
typedef enum DCIOCHIP_GPIO_I2C_MASK {
DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x00000000,
DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x00000001,
} DCIOCHIP_GPIO_I2C_MASK;
typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x00000000,
DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x00000001,
} DCIOCHIP_GPIO_I2C_DRIVE;
typedef enum DCIOCHIP_GPIO_I2C_EN {
DCIOCHIP_GPIO_I2C_DISABLE = 0x00000000,
DCIOCHIP_GPIO_I2C_ENABLE = 0x00000001,
} DCIOCHIP_GPIO_I2C_EN;
typedef enum DCIOCHIP_MASK_4BIT {
DCIOCHIP_MASK_4BIT_DISABLE = 0x00000000,
DCIOCHIP_MASK_4BIT_ENABLE = 0x0000000f,
} DCIOCHIP_MASK_4BIT;
typedef enum DCIOCHIP_ENABLE_4BIT {
DCIOCHIP_4BIT_DISABLE = 0x00000000,
DCIOCHIP_4BIT_ENABLE = 0x0000000f,
} DCIOCHIP_ENABLE_4BIT;
typedef enum DCIOCHIP_MASK_5BIT {
DCIOCHIP_MASIK_5BIT_DISABLE = 0x00000000,
DCIOCHIP_MASIK_5BIT_ENABLE = 0x0000001f,
} DCIOCHIP_MASK_5BIT;
typedef enum DCIOCHIP_ENABLE_5BIT {
DCIOCHIP_5BIT_DISABLE = 0x00000000,
DCIOCHIP_5BIT_ENABLE = 0x0000001f,
} DCIOCHIP_ENABLE_5BIT;
typedef enum DCIOCHIP_MASK_2BIT {
DCIOCHIP_MASK_2BIT_DISABLE = 0x00000000,
DCIOCHIP_MASK_2BIT_ENABLE = 0x00000003,
} DCIOCHIP_MASK_2BIT;
typedef enum DCIOCHIP_ENABLE_2BIT {
DCIOCHIP_2BIT_DISABLE = 0x00000000,
DCIOCHIP_2BIT_ENABLE = 0x00000003,
} DCIOCHIP_ENABLE_2BIT;
typedef enum DCIOCHIP_REF_27_SRC_SEL {
DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000,
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001,
DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002,
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003,
} DCIOCHIP_REF_27_SRC_SEL;
typedef enum DCIOCHIP_DVO_VREFPON {
DCIOCHIP_DVO_VREFPON_DISABLE = 0x00000000,
DCIOCHIP_DVO_VREFPON_ENABLE = 0x00000001,
} DCIOCHIP_DVO_VREFPON;
typedef enum DCIOCHIP_DVO_VREFSEL {
DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x00000000,
DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x00000001,
} DCIOCHIP_DVO_VREFSEL;
typedef enum DCIOCHIP_SPDIF1_IMODE {
DCIOCHIP_SPDIF1_IMODE_OE_A = 0x00000000,
DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x00000001,
} DCIOCHIP_SPDIF1_IMODE;
typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000,
DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001,
DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002,
DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003,
} DCIOCHIP_AUX_FALLSLEWSEL;
typedef enum DCIOCHIP_AUX_SPIKESEL {
DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000,
DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001,
} DCIOCHIP_AUX_SPIKESEL;
typedef enum DCIOCHIP_AUX_CSEL0P9 {
DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000,
DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001,
} DCIOCHIP_AUX_CSEL0P9;
typedef enum DCIOCHIP_AUX_CSEL1P1 {
DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000,
DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001,
} DCIOCHIP_AUX_CSEL1P1;
typedef enum DCIOCHIP_AUX_RSEL0P9 {
DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000,
DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001,
} DCIOCHIP_AUX_RSEL0P9;
typedef enum DCIOCHIP_AUX_RSEL1P1 {
DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000,
DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001,
} DCIOCHIP_AUX_RSEL1P1;
typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000,
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001,
} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000,
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001,
} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000,
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001,
} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000,
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001,
} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
typedef enum AZ_GLOBAL_CAPABILITIES {
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000,
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001,
} AZ_GLOBAL_CAPABILITIES;
typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000,
ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001,
} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000,
FLUSH_CONTROL_FLUSH_STARTED = 0x00000001,
} GLOBAL_CONTROL_FLUSH_CONTROL;
typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000,
CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001,
} GLOBAL_CONTROL_CONTROLLER_RESET;
typedef enum AZ_STATE_CHANGE_STATUS {
AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000,
AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001,
} AZ_STATE_CHANGE_STATUS;
typedef enum GLOBAL_STATUS_FLUSH_STATUS {
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000,
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001,
} GLOBAL_STATUS_FLUSH_STATUS;
typedef enum STREAM_0_SYNCHRONIZATION {
STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
} STREAM_0_SYNCHRONIZATION;
typedef enum STREAM_1_SYNCHRONIZATION {
STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
} STREAM_1_SYNCHRONIZATION;
typedef enum STREAM_2_SYNCHRONIZATION {
STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
} STREAM_2_SYNCHRONIZATION;
typedef enum STREAM_3_SYNCHRONIZATION {
STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
} STREAM_3_SYNCHRONIZATION;
typedef enum STREAM_4_SYNCHRONIZATION {
STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
} STREAM_4_SYNCHRONIZATION;
typedef enum STREAM_5_SYNCHRONIZATION {
STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
} STREAM_5_SYNCHRONIZATION;
typedef enum STREAM_6_SYNCHRONIZATION {
STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_6_SYNCHRONIZATION;
typedef enum STREAM_7_SYNCHRONIZATION {
STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_7_SYNCHRONIZATION;
typedef enum STREAM_8_SYNCHRONIZATION {
STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_8_SYNCHRONIZATION;
typedef enum STREAM_9_SYNCHRONIZATION {
STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_9_SYNCHRONIZATION;
typedef enum STREAM_10_SYNCHRONIZATION {
STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_10_SYNCHRONIZATION;
typedef enum STREAM_11_SYNCHRONIZATION {
STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_11_SYNCHRONIZATION;
typedef enum STREAM_12_SYNCHRONIZATION {
STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_12_SYNCHRONIZATION;
typedef enum STREAM_13_SYNCHRONIZATION {
STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_13_SYNCHRONIZATION;
typedef enum STREAM_14_SYNCHRONIZATION {
STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_14_SYNCHRONIZATION;
typedef enum STREAM_15_SYNCHRONIZATION {
STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
} STREAM_15_SYNCHRONIZATION;
typedef enum CORB_READ_POINTER_RESET {
CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000,
CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001,
} CORB_READ_POINTER_RESET;
typedef enum AZ_CORB_SIZE {
AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000,
AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001,
AZ_CORB_SIZE_256ENTRIES = 0x00000002,
AZ_CORB_SIZE_RESERVED = 0x00000003,
} AZ_CORB_SIZE;
typedef enum AZ_RIRB_WRITE_POINTER_RESET {
AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000,
AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001,
} AZ_RIRB_WRITE_POINTER_RESET;
typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
typedef enum AZ_RIRB_SIZE {
AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000,
AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001,
AZ_RIRB_SIZE_256ENTRIES = 0x00000002,
AZ_RIRB_SIZE_UNDEFINED = 0x00000003,
} AZ_RIRB_SIZE;
typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000,
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001,
} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000,
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001,
} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000,
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001,
} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000,
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001,
} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007,
} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007,
} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000,
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001,
} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
typedef enum ENABLE {
DISABLE_THE_FEATURE = 0x00000000,
ENABLE_THE_FEATURE = 0x00000001,
} ENABLE;
typedef enum ENABLE_CLOCK {
DISABLE_THE_CLOCK = 0x00000000,
ENABLE_THE_CLOCK = 0x00000001,
} ENABLE_CLOCK;
typedef enum FORCE_VBI {
FORCE_VBI_LOW = 0x00000000,
FORCE_VBI_HIGH = 0x00000001,
} FORCE_VBI;
typedef enum OVERRIDE_CGTT_SCLK {
OVERRIDE_CGTT_SCLK_NOOP = 0x00000000,
SET_OVERRIDE_CGTT_SCLK = 0x00000001,
} OVERRIDE_CGTT_SCLK;
typedef enum CLEAR_SMU_INTR {
SMU_INTR_STATUS_NOOP = 0x00000000,
SMU_INTR_STATUS_CLEAR = 0x00000001,
} CLEAR_SMU_INTR;
typedef enum STATIC_SCREEN_SMU_INTR {
STATIC_SCREEN_SMU_INTR_NOOP = 0x00000000,
SET_STATIC_SCREEN_SMU_INTR = 0x00000001,
} STATIC_SCREEN_SMU_INTR;
typedef enum JITTER_REMOVE_DISABLE {
ENABLE_JITTER_REMOVAL = 0x00000000,
DISABLE_JITTER_REMOVAL = 0x00000001,
} JITTER_REMOVE_DISABLE;
typedef enum DS_REF_SRC {
DS_REF_IS_XTALIN = 0x00000000,
DS_REF_IS_EXT_GENLOCK = 0x00000001,
DS_REF_IS_PCIE = 0x00000002,
} DS_REF_SRC;
typedef enum DISABLE_CLOCK_GATING {
CLOCK_GATING_ENABLED = 0x00000000,
CLOCK_GATING_DISABLED = 0x00000001,
} DISABLE_CLOCK_GATING;
typedef enum DISABLE_CLOCK_GATING_IN_DCO {
CLOCK_GATING_ENABLED_IN_DCO = 0x00000000,
CLOCK_GATING_DISABLED_IN_DCO = 0x00000001,
} DISABLE_CLOCK_GATING_IN_DCO;
typedef enum DCCG_DEEP_COLOR_CNTL {
DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000,
DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001,
DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002,
DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003,
} DCCG_DEEP_COLOR_CNTL;
typedef enum REFCLK_CLOCK_EN {
REFCLK_CLOCK_EN_XTALIN_CLK = 0x00000000,
REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 0x00000001,
} REFCLK_CLOCK_EN;
typedef enum REFCLK_SRC_SEL {
REFCLK_SRC_SEL_PCIE_REFCLK = 0x00000000,
REFCLK_SRC_SEL_CPL_REFCLK = 0x00000001,
} REFCLK_SRC_SEL;
typedef enum DPREFCLK_SRC_SEL {
DPREFCLK_SRC_SEL_CK = 0x00000000,
DPREFCLK_SRC_SEL_P0PLL = 0x00000001,
DPREFCLK_SRC_SEL_P1PLL = 0x00000002,
DPREFCLK_SRC_SEL_P2PLL = 0x00000003,
DPREFCLK_SRC_SEL_P3PLL = 0x00000004,
} DPREFCLK_SRC_SEL;
typedef enum XTAL_REF_SEL {
XTAL_REF_SEL_1X = 0x00000000,
XTAL_REF_SEL_2X = 0x00000001,
} XTAL_REF_SEL;
typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000,
XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 0x00000001,
} XTAL_REF_CLOCK_SOURCE_SEL;
typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001,
} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
typedef enum ALLOW_SR_ON_TRANS_REQ {
ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000,
ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001,
} ALLOW_SR_ON_TRANS_REQ;
typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001,
} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
typedef enum PIPE_PIXEL_RATE_SOURCE {
PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000,
PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001,
PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002,
} PIPE_PIXEL_RATE_SOURCE;
typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x00000004,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x00000005,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 0x00000006,
} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000,
PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001,
} PIPE_PIXEL_RATE_PLL_SOURCE;
typedef enum DP_DTO_DS_DISABLE {
DP_DTO_DESPREAD_DISABLE = 0x00000000,
DP_DTO_DESPREAD_ENABLE = 0x00000001,
} DP_DTO_DS_DISABLE;
typedef enum CRTC_ADD_PIXEL {
CRTC_ADD_PIXEL_NOOP = 0x00000000,
CRTC_ADD_PIXEL_FORCE = 0x00000001,
} CRTC_ADD_PIXEL;
typedef enum CRTC_DROP_PIXEL {
CRTC_DROP_PIXEL_NOOP = 0x00000000,
CRTC_DROP_PIXEL_FORCE = 0x00000001,
} CRTC_DROP_PIXEL;
typedef enum SYMCLK_FE_FORCE_EN {
SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000,
SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001,
} SYMCLK_FE_FORCE_EN;
typedef enum SYMCLK_FE_FORCE_SRC {
SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000,
SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001,
SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002,
SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003,
SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x00000004,
SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x00000005,
SYMCLK_FE_FORCE_SRC_UNIPHYG = 0x00000006,
} SYMCLK_FE_FORCE_SRC;
typedef enum DPDBG_CLK_FORCE_EN {
DPDBG_CLK_FORCE_EN_DISABLE = 0x00000000,
DPDBG_CLK_FORCE_EN_ENABLE = 0x00000001,
} DPDBG_CLK_FORCE_EN;
typedef enum DVOACLK_COARSE_SKEW_CNTL {
DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004,
DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005,
DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006,
DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007,
DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008,
DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009,
DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a,
DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b,
DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c,
DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d,
DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e,
DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f,
DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010,
DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011,
DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012,
DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013,
DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014,
DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015,
DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016,
DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017,
DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018,
DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019,
DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a,
DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b,
DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c,
DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d,
DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e,
} DVOACLK_COARSE_SKEW_CNTL;
typedef enum DVOACLK_FINE_SKEW_CNTL {
DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004,
DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005,
DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006,
DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007,
} DVOACLK_FINE_SKEW_CNTL;
typedef enum DVOACLKD_IN_PHASE {
DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
} DVOACLKD_IN_PHASE;
typedef enum DVOACLKC_IN_PHASE {
DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
} DVOACLKC_IN_PHASE;
typedef enum DVOACLKC_MVP_IN_PHASE {
DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
} DVOACLKC_MVP_IN_PHASE;
typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000,
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001,
} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
typedef enum MVP_CLK_SRC_SEL {
MVP_CLK_SRC_SEL_RSRV = 0x00000000,
MVP_CLK_SRC_SEL_IO_1 = 0x00000001,
MVP_CLK_SRC_SEL_IO_2 = 0x00000002,
MVP_CLK_SRC_SEL_REFCLK = 0x00000003,
} MVP_CLK_SRC_SEL;
typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0x00000000,
DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 0x00000001,
DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 0x00000002,
DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 0x00000003,
DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 0x00000004,
DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 0x00000005,
DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000006,
} DCCG_AUDIO_DTO0_SOURCE_SEL;
typedef enum DCCG_AUDIO_DTO_SEL {
DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000,
DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001,
DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002,
} DCCG_AUDIO_DTO_SEL;
typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000,
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x00000001,
} DCCG_AUDIO_DTO2_SOURCE_SEL;
typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000,
DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001,
} DCCG_AUDIO_DTO_USE_512FBR_DTO;
typedef enum DCCG_DBG_EN {
DCCG_DBG_EN_DISABLE = 0x00000000,
DCCG_DBG_EN_ENABLE = 0x00000001,
} DCCG_DBG_EN;
typedef enum DCCG_DBG_BLOCK_SEL {
DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000,
DCCG_DBG_BLOCK_SEL_PMON = 0x00000001,
DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002,
} DCCG_DBG_BLOCK_SEL;
typedef enum DISPCLK_FREQ_RAMP_DONE {
DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000,
DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001,
} DISPCLK_FREQ_RAMP_DONE;
typedef enum DCCG_FIFO_ERRDET_RESET {
DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000,
DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001,
} DCCG_FIFO_ERRDET_RESET;
typedef enum DCCG_FIFO_ERRDET_STATE {
DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000000,
DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000001,
} DCCG_FIFO_ERRDET_STATE;
typedef enum DCCG_FIFO_ERRDET_OVR_EN {
DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000,
DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001,
} DCCG_FIFO_ERRDET_OVR_EN;
typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000,
DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001,
} DISPCLK_CHG_FWD_CORR_DISABLE;
typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000,
DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001,
} DC_MEM_GLOBAL_PWR_REQ_DIS;
typedef enum DCCG_PERF_RUN {
DCCG_PERF_RUN_NOOP = 0x00000000,
DCCG_PERF_RUN_START = 0x00000001,
} DCCG_PERF_RUN;
typedef enum DCCG_PERF_MODE_VSYNC {
DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000,
DCCG_PERF_MODE_VSYNC_START = 0x00000001,
} DCCG_PERF_MODE_VSYNC;
typedef enum DCCG_PERF_MODE_HSYNC {
DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000,
DCCG_PERF_MODE_HSYNC_START = 0x00000001,
} DCCG_PERF_MODE_HSYNC;
typedef enum DCCG_PERF_CRTC_SELECT {
DCCG_PERF_SEL_CRTC0 = 0x00000000,
DCCG_PERF_SEL_CRTC1 = 0x00000001,
DCCG_PERF_SEL_CRTC2 = 0x00000002,
DCCG_PERF_SEL_CRTC3 = 0x00000003,
DCCG_PERF_SEL_CRTC4 = 0x00000004,
DCCG_PERF_SEL_CRTC5 = 0x00000005,
} DCCG_PERF_CRTC_SELECT;
typedef enum CLOCK_BRANCH_SOFT_RESET {
CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000,
CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001,
} CLOCK_BRANCH_SOFT_RESET;
typedef enum PLL_CFG_IF_SOFT_RESET {
PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000,
PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001,
} PLL_CFG_IF_SOFT_RESET;
typedef enum DVO_ENABLE_RST {
DVO_ENABLE_RST_DISABLE = 0x00000000,
DVO_ENABLE_RST_ENABLE = 0x00000001,
} DVO_ENABLE_RST;
typedef enum LptNumPipes {
LPT_NUM_PIPES_1CH = 0x00000000,
LPT_NUM_PIPES_2CH = 0x00000001,
LPT_NUM_PIPES_4CH = 0x00000002,
LPT_NUM_PIPES_8CH = 0x00000003,
} LptNumPipes;
typedef enum LptNumBanks {
LPT_NUM_BANKS_2BANK = 0x00000000,
LPT_NUM_BANKS_4BANK = 0x00000001,
LPT_NUM_BANKS_8BANK = 0x00000002,
LPT_NUM_BANKS_16BANK =