#ifndef DSI_PHY_28NM_8960_XML
#define DSI_PHY_28NM_8960_XML

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git

The rules-ng-ng source files this header was generated from are:
- /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-03-03 01:18:13)
- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2020-12-31 19:26:32)
- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-01-30 18:25:22)
- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-01-30 18:25:22)
- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-01-30 18:25:22)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml               (  17560 bytes, from 2021-09-16 22:37:02)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-07-22 15:21:56)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-07-22 15:21:56)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-07-22 15:21:56)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-07-22 15:21:56)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-07-22 15:21:56)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-07-22 15:21:56)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-03 01:18:13)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-01-30 18:25:22)
- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-01-30 18:25:22)
- /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-01-30 18:25:22)
- /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-01-30 18:25:22)
- /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-01-30 18:25:22)

Copyright (C) 2013-2021 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/


static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }

#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0			0x00000100

#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1			0x00000104

#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2			0x00000108

#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH		0x0000010c

#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0			0x00000114

#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1			0x00000118

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0			0x00000140
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1			0x00000144
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT	0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2			0x00000148
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK	0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT	0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3			0x0000014c

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4			0x00000150
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5			0x00000154
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6			0x00000158
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK	0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT	0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7			0x0000015c
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8			0x00000160
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9			0x00000164
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK		0x00000007
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
}
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK		0x00000070
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT		4
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10			0x00000168
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK		0x00000007
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11			0x0000016c
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK	0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT	0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
}

#define REG_DSI_28nm_8960_PHY_CTRL_0				0x00000170

#define REG_DSI_28nm_8960_PHY_CTRL_1				0x00000174

#define REG_DSI_28nm_8960_PHY_CTRL_2				0x00000178

#define REG_DSI_28nm_8960_PHY_CTRL_3				0x0000017c

#define REG_DSI_28nm_8960_PHY_STRENGTH_0			0x00000180

#define REG_DSI_28nm_8960_PHY_STRENGTH_1			0x00000184

#define REG_DSI_28nm_8960_PHY_STRENGTH_2			0x00000188

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0			0x0000018c

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1			0x00000190

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2			0x00000194

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3			0x00000198

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4			0x0000019c

#define REG_DSI_28nm_8960_PHY_LDO_CTRL				0x000001b0

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0		0x00000000

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1		0x00000004

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2		0x00000008

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3		0x0000000c

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4		0x00000010

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5		0x00000014

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG	0x00000018

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER		0x00000028

#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0			0x0000002c

#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1			0x00000030

#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2			0x00000034

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0			0x00000038

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1			0x0000003c

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2			0x00000040

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3			0x00000044

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4			0x00000048

#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS			0x00000050
#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY		0x00000010

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0			0x00000000
#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE			0x00000001

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1			0x00000004

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2			0x00000008

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3			0x0000000c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4			0x00000010

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5			0x00000014

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6			0x00000018

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7			0x0000001c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8			0x00000020

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9			0x00000024

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10			0x00000028

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11			0x0000002c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12			0x00000030

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13			0x00000034

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14			0x00000038

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15			0x0000003c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16			0x00000040

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17			0x00000044

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18			0x00000048

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19			0x0000004c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20			0x00000050

#define REG_DSI_28nm_8960_PHY_PLL_RDY				0x00000080
#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY			0x00000001


#endif /* DSI_PHY_28NM_8960_XML */