/*
 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#if !defined (_navi10_ENUM_HEADER)
#define _navi10_ENUM_HEADER

#ifndef _DRIVER_BUILD
#ifndef GL_ZERO
#define GL__ZERO                      BLEND_ZERO
#define GL__ONE                       BLEND_ONE
#define GL__SRC_COLOR                 BLEND_SRC_COLOR
#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
#define GL__DST_COLOR                 BLEND_DST_COLOR
#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
#define GL__DST_ALPHA                 BLEND_DST_ALPHA
#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
#endif
#endif

/*******************************************************
 * GDS DATA_TYPE Enums
 *******************************************************/

#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
#define ENUMS_GDS_PERFCOUNT_SELECT_H
typedef enum GDS_PERFCOUNT_SELECT {
 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
 GDS_PERF_SEL_DS_BANK_CONFL = 1,
 GDS_PERF_SEL_WBUF_FLUSH = 2,
 GDS_PERF_SEL_WR_COMP = 3,
 GDS_PERF_SEL_WBUF_WR = 4,
 GDS_PERF_SEL_RBUF_HIT = 5,
 GDS_PERF_SEL_RBUF_MISS = 6,
 GDS_PERF_SEL_SE0_SH0_NORET = 7,
 GDS_PERF_SEL_SE0_SH0_RET = 8,
 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
 GDS_PERF_SEL_SE0_SH1_NORET = 21,
 GDS_PERF_SEL_SE0_SH1_RET = 22,
 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
 GDS_PERF_SEL_SE1_SH0_NORET = 35,
 GDS_PERF_SEL_SE1_SH0_RET = 36,
 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
 GDS_PERF_SEL_SE1_SH1_NORET = 49,
 GDS_PERF_SEL_SE1_SH1_RET = 50,
 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
 GDS_PERF_SEL_SE2_SH0_NORET = 63,
 GDS_PERF_SEL_SE2_SH0_RET = 64,
 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
 GDS_PERF_SEL_SE2_SH1_NORET = 77,
 GDS_PERF_SEL_SE2_SH1_RET = 78,
 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
 GDS_PERF_SEL_SE3_SH0_NORET = 91,
 GDS_PERF_SEL_SE3_SH0_RET = 92,
 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
 GDS_PERF_SEL_SE3_SH1_NORET = 105,
 GDS_PERF_SEL_SE3_SH1_RET = 106,
 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
 GDS_PERF_SEL_GWS_RELEASED = 119,
 GDS_PERF_SEL_GWS_BYPASS = 120,
} GDS_PERFCOUNT_SELECT;
#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/

/*******************************************************
 * Chip Enums
 *******************************************************/

/*
 * GATCL1RequestType enum
 */

typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL                       = 0x00000000,
GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
GATCL1_TYPE_BYPASS                       = 0x00000002,
} GATCL1RequestType;

/*
 * UTCL1RequestType enum
 */

typedef enum UTCL1RequestType {
UTCL1_TYPE_NORMAL                        = 0x00000000,
UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,
UTCL1_TYPE_BYPASS                        = 0x00000002,
} UTCL1RequestType;

/*
 * UTCL1FaultType enum
 */

typedef enum UTCL1FaultType {
UTCL1_XNACK_SUCCESS                      = 0x00000000,
UTCL1_XNACK_RETRY                        = 0x00000001,
UTCL1_XNACK_PRT                          = 0x00000002,
UTCL1_XNACK_NO_RETRY                     = 0x00000003,
} UTCL1FaultType;

/*
 * UTCL0RequestType enum
 */

typedef enum UTCL0RequestType {
UTCL0_TYPE_NORMAL                        = 0x00000000,
UTCL0_TYPE_SHOOTDOWN                     = 0x00000001,
UTCL0_TYPE_BYPASS                        = 0x00000002,
} UTCL0RequestType;

/*
 * UTCL0FaultType enum
 */

typedef enum UTCL0FaultType {
UTCL0_XNACK_SUCCESS                      = 0x00000000,
UTCL0_XNACK_RETRY                        = 0x00000001,
UTCL0_XNACK_PRT                          = 0x00000002,
UTCL0_XNACK_NO_RETRY                     = 0x00000003,
} UTCL0FaultType;

/*
 * VMEMCMD_RETURN_ORDER enum
 */

typedef enum VMEMCMD_RETURN_ORDER {
VMEMCMD_RETURN_OUT_OF_ORDER              = 0x00000000,
VMEMCMD_RETURN_IN_ORDER                  = 0x00000001,
VMEMCMD_RETURN_IN_ORDER_READ             = 0x00000002,
} VMEMCMD_RETURN_ORDER;

/*
 * GL0V_CACHE_POLICIES enum
 */

typedef enum GL0V_CACHE_POLICIES {
GL0V_CACHE_POLICY_MISS_LRU               = 0x00000000,
GL0V_CACHE_POLICY_MISS_EVICT             = 0x00000001,
GL0V_CACHE_POLICY_HIT_LRU                = 0x00000002,
GL0V_CACHE_POLICY_HIT_EVICT              = 0x00000003,
} GL0V_CACHE_POLICIES;

/*
 * GL1_CACHE_POLICIES enum
 */

typedef enum GL1_CACHE_POLICIES {
GL1_CACHE_POLICY_MISS_LRU                = 0x00000000,
GL1_CACHE_POLICY_MISS_EVICT              = 0x00000001,
GL1_CACHE_POLICY_HIT_LRU                 = 0x00000002,
GL1_CACHE_POLICY_HIT_EVICT               = 0x00000003,
} GL1_CACHE_POLICIES;

/*
 * GL1_CACHE_STORE_POLICIES enum
 */

typedef enum GL1_CACHE_STORE_POLICIES {
GL1_CACHE_STORE_POLICY_BYPASS            = 0x00000000,
} GL1_CACHE_STORE_POLICIES;

/*
 * TCC_CACHE_POLICIES enum
 */

typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU                     = 0x00000000,
TCC_CACHE_POLICY_STREAM                  = 0x00000001,
} TCC_CACHE_POLICIES;

/*
 * TCC_MTYPE enum
 */

typedef enum TCC_MTYPE {
MTYPE_NC                                 = 0x00000000,
MTYPE_WC                                 = 0x00000001,
MTYPE_CC                                 = 0x00000002,
} TCC_MTYPE;

/*
 * GL2_CACHE_POLICIES enum
 */

typedef enum GL2_CACHE_POLICIES {
GL2_CACHE_POLICY_LRU                     = 0x00000000,
GL2_CACHE_POLICY_STREAM                  = 0x00000001,
GL2_CACHE_POLICY_NOA                     = 0x00000002,
GL2_CACHE_POLICY_BYPASS                  = 0x00000003,
} GL2_CACHE_POLICIES;

/*
 * MTYPE enum
 */

typedef enum MTYPE {
MTYPE_C_RW_US                            = 0x00000000,
MTYPE_RESERVED_1                         = 0x00000001,
MTYPE_C_RO_S                             = 0x00000002,
MTYPE_UC                                 = 0x00000003,
MTYPE_C_RW_S                             = 0x00000004,
MTYPE_RESERVED_5                         = 0x00000005,
MTYPE_C_RO_US                            = 0x00000006,
MTYPE_RESERVED_7                         = 0x00000007,
} MTYPE;

/*
 * RMI_CID enum
 */

typedef enum RMI_CID {
RMI_CID_CC                               = 0x00000000,
RMI_CID_FC                               = 0x00000001,
RMI_CID_CM                               = 0x00000002,
RMI_CID_DC                               = 0x00000003,
RMI_CID_Z                                = 0x00000004,
RMI_CID_S                                = 0x00000005,
RMI_CID_TILE                             = 0x00000006,
RMI_CID_ZPCPSD                           = 0x00000007,
} RMI_CID;

/*
 * WritePolicy enum
 */

typedef enum WritePolicy {
CACHE_LRU_WR                             = 0x00000000,
CACHE_STREAM                             = 0x00000001,
CACHE_BYPASS                             = 0x00000002,
UNCACHED_WR                              = 0x00000003,
} WritePolicy;

/*
 * ReadPolicy enum
 */

typedef enum ReadPolicy {
CACHE_LRU_RD                             = 0x00000000,
CACHE_NOA                                = 0x00000001,
UNCACHED_RD                              = 0x00000002,
RESERVED_RDPOLICY                        = 0x00000003,
} ReadPolicy;

/*
 * PERFMON_COUNTER_MODE enum
 */

typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT  = 0x00000005,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT  = 0x00000006,
PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
} PERFMON_COUNTER_MODE;

/*
 * PERFMON_SPM_MODE enum
 */

typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF                     = 0x00000000,
PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
} PERFMON_SPM_MODE;

/*
 * SurfaceTiling enum
 */

typedef enum SurfaceTiling {
ARRAY_LINEAR                             = 0x00000000,
ARRAY_TILED                              = 0x00000001,
} SurfaceTiling;

/*
 * SurfaceArray enum
 */

typedef enum SurfaceArray {
ARRAY_1D                                 = 0x00000000,
ARRAY_2D                                 = 0x00000001,
ARRAY_3D                                 = 0x00000002,
ARRAY_3D_SLICE                           = 0x00000003,
} SurfaceArray;

/*
 * ColorArray enum
 */

typedef enum ColorArray {
ARRAY_2D_ALT_COLOR                       = 0x00000000,
ARRAY_2D_COLOR                           = 0x00000001,
ARRAY_3D_SLICE_COLOR                     = 0x00000003,
} ColorArray;

/*
 * DepthArray enum
 */

typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH                       = 0x00000000,
ARRAY_2D_DEPTH                           = 0x00000001,
} DepthArray;

/*
 * ENUM_NUM_SIMD_PER_CU enum
 */

typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU                          = 0x00000004,
} ENUM_NUM_SIMD_PER_CU;

/*
 * DSM_ENABLE_ERROR_INJECT enum
 */

typedef enum DSM_ENABLE_ERROR_INJECT {
DSM_ENABLE_ERROR_INJECT_FED_IN           = 0x00000000,
DSM_ENABLE_ERROR_INJECT_SINGLE           = 0x00000001,
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE    = 0x00000002,
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED  = 0x00000003,
} DSM_ENABLE_ERROR_INJECT;

/*
 * DSM_SELECT_INJECT_DELAY enum
 */

typedef enum DSM_SELECT_INJECT_DELAY {
DSM_SELECT_INJECT_DELAY_NO_DELAY         = 0x00000000,
DSM_SELECT_INJECT_DELAY_DELAY_ERROR      = 0x00000001,
} DSM_SELECT_INJECT_DELAY;

/*
 * DSM_DATA_SEL enum
 */

typedef enum DSM_DATA_SEL {
DSM_DATA_SEL_DISABLE                     = 0x00000000,
DSM_DATA_SEL_0                           = 0x00000001,
DSM_DATA_SEL_1                           = 0x00000002,
DSM_DATA_SEL_BOTH                        = 0x00000003,
} DSM_DATA_SEL;

/*
 * DSM_SINGLE_WRITE enum
 */

typedef enum DSM_SINGLE_WRITE {
DSM_SINGLE_WRITE_DIS                     = 0x00000000,
DSM_SINGLE_WRITE_EN                      = 0x00000001,
} DSM_SINGLE_WRITE;

/*
 * Hdp_SurfaceEndian enum
 */

typedef enum Hdp_SurfaceEndian {
HDP_ENDIAN_NONE                          = 0x00000000,
HDP_ENDIAN_8IN16                         = 0x00000001,
HDP_ENDIAN_8IN32                         = 0x00000002,
HDP_ENDIAN_8IN64                         = 0x00000003,
} Hdp_SurfaceEndian;

/*******************************************************
 * CNVC_CFG Enums
 *******************************************************/

/*
 * CNVC_ENABLE enum
 */

typedef enum CNVC_ENABLE {
CNVC_DIS                                 = 0x00000000,
CNVC_EN                                  = 0x00000001,
} CNVC_ENABLE;

/*
 * CNVC_BYPASS enum
 */

typedef enum CNVC_BYPASS {
CNVC_BYPASS_DISABLE                      = 0x00000000,
CNVC_BYPASS_EN                           = 0x00000001,
} CNVC_BYPASS;

/*
 * CNVC_PENDING enum
 */

typedef enum CNVC_PENDING {
CNVC_NOT_PENDING                         = 0x00000000,
CNVC_YES_PENDING                         = 0x00000001,
} CNVC_PENDING;

/*
 * DENORM_TRUNCATE enum
 */

typedef enum DENORM_TRUNCATE {
CNVC_ROUND                               = 0x00000000,
CNVC_TRUNCATE                            = 0x00000001,
} DENORM_TRUNCATE;

/*
 * PIX_EXPAND_MODE enum
 */

typedef enum PIX_EXPAND_MODE {
PIX_DYNAMIC_EXPANSION                    = 0x00000000,
PIX_ZERO_EXPANSION                       = 0x00000001,
} PIX_EXPAND_MODE;

/*
 * SURFACE_PIXEL_FORMAT enum
 */

typedef enum SURFACE_PIXEL_FORMAT {
ARGB1555                                 = 0x00000001,
RGBA5551                                 = 0x00000002,
RGB565                                   = 0x00000003,
BGR565                                   = 0x00000004,
ARGB4444                                 = 0x00000005,
RGBA4444                                 = 0x00000006,
ARGB8888                                 = 0x00000008,
RGBA8888                                 = 0x00000009,
ARGB2101010                              = 0x0000000a,
RGBA1010102                              = 0x0000000b,
AYCrCb8888                               = 0x0000000c,
YCrCbA8888                               = 0x0000000d,
ACrYCb8888                               = 0x0000000e,
CrYCbA8888                               = 0x0000000f,
ARGB16161616_10MSB                       = 0x00000010,
RGBA16161616_10MSB                       = 0x00000011,
ARGB16161616_10LSB                       = 0x00000012,
RGBA16161616_10LSB                       = 0x00000013,
ARGB16161616_12MSB                       = 0x00000014,
RGBA16161616_12MSB                       = 0x00000015,
ARGB16161616_12LSB                       = 0x00000016,
RGBA16161616_12LSB                       = 0x00000017,
ARGB16161616_FLOAT                       = 0x00000018,
RGBA16161616_FLOAT                       = 0x00000019,
ARGB16161616_UNORM                       = 0x0000001a,
RGBA16161616_UNORM                       = 0x0000001b,
ARGB16161616_SNORM                       = 0x0000001c,
RGBA16161616_SNORM                       = 0x0000001d,
AYCrCb16161616_10MSB                     = 0x00000020,
AYCrCb16161616_10LSB                     = 0x00000021,
YCrCbA16161616_10MSB                     = 0x00000022,
YCrCbA16161616_10LSB                     = 0x00000023,
ACrYCb16161616_10MSB                     = 0x00000024,
ACrYCb16161616_10LSB                     = 0x00000025,
CrYCbA16161616_10MSB                     = 0x00000026,
CrYCbA16161616_10LSB                     = 0x00000027,
AYCrCb16161616_12MSB                     = 0x00000028,
AYCrCb16161616_12LSB                     = 0x00000029,
YCrCbA16161616_12MSB                     = 0x0000002a,
YCrCbA16161616_12LSB                     = 0x0000002b,
ACrYCb16161616_12MSB                     = 0x0000002c,
ACrYCb16161616_12LSB                     = 0x0000002d,
CrYCbA16161616_12MSB                     = 0x0000002e,
CrYCbA16161616_12LSB                     = 0x0000002f,
Y8_CrCb88_420_PLANAR                     = 0x00000040,
Y8_CbCr88_420_PLANAR                     = 0x00000041,
Y10_CrCb1010_420_PLANAR                  = 0x00000042,
Y10_CbCr1010_420_PLANAR                  = 0x00000043,
Y12_CrCb1212_420_PLANAR                  = 0x00000044,
Y12_CbCr1212_420_PLANAR                  = 0x00000045,
YCrYCb8888_422_PACKED                    = 0x00000048,
YCbYCr8888_422_PACKED                    = 0x00000049,
CrYCbY8888_422_PACKED                    = 0x0000004a,
CbYCrY8888_422_PACKED                    = 0x0000004b,
YCrYCb10101010_422_PACKED                = 0x0000004c,
YCbYCr10101010_422_PACKED                = 0x0000004d,
CrYCbY10101010_422_PACKED                = 0x0000004e,
CbYCrY10101010_422_PACKED                = 0x0000004f,
YCrYCb12121212_422_PACKED                = 0x00000050,
YCbYCr12121212_422_PACKED                = 0x00000051,
CrYCbY12121212_422_PACKED                = 0x00000052,
CbYCrY12121212_422_PACKED                = 0x00000053,
RGB111110_FIX                            = 0x00000070,
BGR101111_FIX                            = 0x00000071,
ACrYCb2101010                            = 0x00000072,
CrYCbA1010102                            = 0x00000073,
RGB111110_FLOAT                          = 0x00000076,
BGR101111_FLOAT                          = 0x00000077,
MONO_8                                   = 0x00000078,
MONO_10MSB                               = 0x00000079,
MONO_10LSB                               = 0x0000007a,
MONO_12MSB                               = 0x0000007b,
MONO_12LSB                               = 0x0000007c,
MONO_16                                  = 0x0000007d,
} SURFACE_PIXEL_FORMAT;

/*
 * XNORM enum
 */

typedef enum XNORM {
XNORM_A                                  = 0x00000000,
XNORM_B                                  = 0x00000001,
} XNORM;

/*
 * COLOR_KEYER_MODE enum
 */

typedef enum COLOR_KEYER_MODE {
FORCE_00                                 = 0x00000000,
FORCE_FF                                 = 0x00000001,
RANGE_00                                 = 0x00000002,
RANGE_FF                                 = 0x00000003,
} COLOR_KEYER_MODE;

/*******************************************************
 * CNVC_CUR Enums
 *******************************************************/

/*
 * CUR_ENABLE enum
 */

typedef enum CUR_ENABLE {
CUR_DIS                                  = 0x00000000,
CUR_EN                                   = 0x00000001,
} CUR_ENABLE;

/*
 * CUR_PENDING enum
 */

typedef enum CUR_PENDING {
CUR_NOT_PENDING                          = 0x00000000,
CUR_YES_PENDING                          = 0x00000001,
} CUR_PENDING;

/*
 * CUR_EXPAND_MODE enum
 */

typedef enum CUR_EXPAND_MODE {
CUR_DYNAMIC_EXPANSION                    = 0x00000000,
CUR_ZERO_EXPANSION                       = 0x00000001,
} CUR_EXPAND_MODE;

/*
 * CUR_ROM_EN enum
 */

typedef enum CUR_ROM_EN {
CUR_FP_NO_ROM                            = 0x00000000,
CUR_FP_USE_ROM                           = 0x00000001,
} CUR_ROM_EN;

/*
 * CUR_MODE enum
 */

typedef enum CUR_MODE {
MONO_2BIT                                = 0x00000000,
COLOR_24BIT_1BIT_AND                     = 0x00000001,
COLOR_24BIT_8BIT_ALPHA_PREMULT           = 0x00000002,
COLOR_24BIT_8BIT_ALPHA_UNPREMULT         = 0x00000003,
COLOR_64BIT_FP_PREMULT                   = 0x00000004,
COLOR_64BIT_FP_UNPREMULT                 = 0x00000005,
} CUR_MODE;

/*
 * CUR_INV_CLAMP enum
 */

typedef enum CUR_INV_CLAMP {
CUR_CLAMP_DIS                            = 0x00000000,
CUR_CLAMP_EN                             = 0x00000001,
} CUR_INV_CLAMP;

/*******************************************************
 * DSCL Enums
 *******************************************************/

/*
 * SCL_COEF_FILTER_TYPE_SEL enum
 */

typedef enum SCL_COEF_FILTER_TYPE_SEL {
SCL_COEF_LUMA_VERT_FILTER                = 0x00000000,
SCL_COEF_LUMA_HORZ_FILTER                = 0x00000001,
SCL_COEF_CHROMA_VERT_FILTER              = 0x00000002,
SCL_COEF_CHROMA_HORZ_FILTER              = 0x00000003,
SCL_COEF_ALPHA_VERT_FILTER               = 0x00000004,
SCL_COEF_ALPHA_HORZ_FILTER               = 0x00000005,
} SCL_COEF_FILTER_TYPE_SEL;

/*
 * DSCL_MODE_SEL enum
 */

typedef enum DSCL_MODE_SEL {
DSCL_MODE_SCALING_444_BYPASS             = 0x00000000,
DSCL_MODE_SCALING_444_RGB_ENABLE         = 0x00000001,
DSCL_MODE_SCALING_444_YCBCR_ENABLE       = 0x00000002,
DSCL_MODE_SCALING_YCBCR_ENABLE           = 0x00000003,
DSCL_MODE_LUMA_SCALING_BYPASS            = 0x00000004,
DSCL_MODE_CHROMA_SCALING_BYPASS          = 0x00000005,
DSCL_MODE_DSCL_BYPASS                    = 0x00000006,
} DSCL_MODE_SEL;

/*
 * SCL_AUTOCAL_MODE enum
 */

typedef enum SCL_AUTOCAL_MODE {
AUTOCAL_MODE_OFF                         = 0x00000000,
AUTOCAL_MODE_AUTOSCALE                   = 0x00000001,
AUTOCAL_MODE_AUTOCENTER                  = 0x00000002,
AUTOCAL_MODE_AUTOREPLICATE               = 0x00000003,
} SCL_AUTOCAL_MODE;

/*
 * SCL_COEF_RAM_SEL enum
 */

typedef enum SCL_COEF_RAM_SEL {
SCL_COEF_RAM_SEL_0                       = 0x00000000,
SCL_COEF_RAM_SEL_1                       = 0x00000001,
} SCL_COEF_RAM_SEL;

/*
 * SCL_CHROMA_COEF enum
 */

typedef enum SCL_CHROMA_COEF {
SCL_CHROMA_COEF_LUMA                     = 0x00000000,
SCL_CHROMA_COEF_CHROMA                   = 0x00000001,
} SCL_CHROMA_COEF;

/*
 * SCL_ALPHA_COEF enum
 */

typedef enum SCL_ALPHA_COEF {
SCL_ALPHA_COEF_LUMA                      = 0x00000000,
SCL_ALPHA_COEF_ALPHA                     = 0x00000001,
} SCL_ALPHA_COEF;

/*
 * COEF_RAM_SELECT_RD enum
 */

typedef enum COEF_RAM_SELECT_RD {
COEF_RAM_SELECT_BACK                     = 0x00000000,
COEF_RAM_SELECT_CURRENT                  = 0x00000001,
} COEF_RAM_SELECT_RD;

/*
 * SCL_2TAP_HARDCODE enum
 */

typedef enum SCL_2TAP_HARDCODE {
SCL_COEF_2TAP_HARDCODE_OFF               = 0x00000000,
SCL_COEF_2TAP_HARDCODE_ON                = 0x00000001,
} SCL_2TAP_HARDCODE;

/*
 * SCL_SHARP_EN enum
 */

typedef enum SCL_SHARP_EN {
SCL_SHARP_DISABLE                        = 0x00000000,
SCL_SHARP_ENABLE                         = 0x00000001,
} SCL_SHARP_EN;

/*
 * SCL_BOUNDARY enum
 */

typedef enum SCL_BOUNDARY {
SCL_BOUNDARY_EDGE                        = 0x00000000,
SCL_BOUNDARY_BLACK                       = 0x00000001,
} SCL_BOUNDARY;

/*
 * LB_INTERLEAVE_EN enum
 */

typedef enum LB_INTERLEAVE_EN {
LB_INTERLEAVE_DISABLE                    = 0x00000000,
LB_INTERLEAVE_ENABLE                     = 0x00000001,
} LB_INTERLEAVE_EN;

/*
 * LB_ALPHA_EN enum
 */

typedef enum LB_ALPHA_EN {
LB_ALPHA_DISABLE                         = 0x00000000,
LB_ALPHA_ENABLE                          = 0x00000001,
} LB_ALPHA_EN;

/*
 * OBUF_BYPASS_SEL enum
 */

typedef enum OBUF_BYPASS_SEL {
OBUF_BYPASS_DIS                          = 0x00000000,
OBUF_BYPASS_EN                           = 0x00000001,
} OBUF_BYPASS_SEL;

/*
 * OBUF_USE_FULL_BUFFER_SEL enum
 */

typedef enum OBUF_USE_FULL_BUFFER_SEL {
OBUF_RECOUT                              = 0x00000000,
OBUF_FULL                                = 0x00000001,
} OBUF_USE_FULL_BUFFER_SEL;

/*
 * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
 */

typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
OBUF_FULL_RECOUT                         = 0x00000000,
OBUF_HALF_RECOUT                         = 0x00000001,
} OBUF_IS_HALF_RECOUT_WIDTH_SEL;

/*******************************************************
 * CM Enums
 *******************************************************/

/*
 * CM_BYPASS enum
 */

typedef enum CM_BYPASS {
NON_BYPASS                               = 0x00000000,
BYPASS_EN                                = 0x00000001,
} CM_BYPASS;

/*
 * CM_EN enum
 */

typedef enum CM_EN {
CM_DISABLE                               = 0x00000000,
CM_ENABLE                                = 0x00000001,
} CM_EN;

/*
 * CM_PENDING enum
 */

typedef enum CM_PENDING {
CM_NOT_PENDING                           = 0x00000000,
CM_YES_PENDING                           = 0x00000001,
} CM_PENDING;

/*
 * CM_DATA_SIGNED enum
 */

typedef enum CM_DATA_SIGNED {
UNSIGNED                                 = 0x00000000,
SIGNED                                   = 0x00000001,
} CM_DATA_SIGNED;

/*
 * CM_WRITE_BASE_ONLY enum
 */

typedef enum CM_WRITE_BASE_ONLY {
WRITE_BOTH                               = 0x00000000,
WRITE_BASE_ONLY                          = 0x00000001,
} CM_WRITE_BASE_ONLY;

/*
 * CM_LUT_4_CONFIG_ENUM enum
 */

typedef enum CM_LUT_4_CONFIG_ENUM {
LUT_4CFG_NO_MEMORY                       = 0x00000000,
LUT_4CFG_ROM_A                           = 0x00000001,
LUT_4CFG_ROM_B                           = 0x00000002,
LUT_4CFG_MEMORY_A                        = 0x00000003,
LUT_4CFG_MEMORY_B                        = 0x00000004,
} CM_LUT_4_CONFIG_ENUM;

/*
 * CM_LUT_2_CONFIG_ENUM enum
 */

typedef enum CM_LUT_2_CONFIG_ENUM {
LUT_2CFG_NO_MEMORY                       = 0x00000000,
LUT_2CFG_MEMORY_A                        = 0x00000001,
LUT_2CFG_MEMORY_B                        = 0x00000002,
} CM_LUT_2_CONFIG_ENUM;

/*
 * CM_LUT_4_MODE_ENUM enum
 */

typedef enum CM_LUT_4_MODE_ENUM {
LUT_4_MODE_BYPASS                        = 0x00000000,
LUT_4_MODE_ROMA_LUT                      = 0x00000001,
LUT_4_MODE_ROMB_LUT                      = 0x00000002,
LUT_4_MODE_RAMA_LUT                      = 0x00000003,
LUT_4_MODE_RAMB_LUT                      = 0x00000004,
} CM_LUT_4_MODE_ENUM;

/*
 * CM_LUT_2_MODE_ENUM enum
 */

typedef enum CM_LUT_2_MODE_ENUM {
LUT_2_MODE_BYPASS                        = 0x00000000,
LUT_2_MODE_RAMA_LUT                      = 0x00000001,
LUT_2_MODE_RAMB_LUT                      = 0x00000002,
} CM_LUT_2_MODE_ENUM;

/*
 * CM_LUT_RAM_SEL enum
 */

typedef enum CM_LUT_RAM_SEL {
RAMA_ACCESS                              = 0x00000000,
RAMB_ACCESS                              = 0x00000001,
} CM_LUT_RAM_SEL;

/*
 * CM_LUT_NUM_SEG enum
 */

typedef enum CM_LUT_NUM_SEG {
SEGMENTS_1                               = 0x00000000,
SEGMENTS_2                               = 0x00000001,
SEGMENTS_4                               = 0x00000002,
SEGMENTS_8                               = 0x00000003,
SEGMENTS_16                              = 0x00000004,
SEGMENTS_32                              = 0x00000005,
SEGMENTS_64                              = 0x00000006,
SEGMENTS_128                             = 0x00000007,
} CM_LUT_NUM_SEG;

/*
 * CM_ICSC_MODE_ENUM enum
 */

typedef enum CM_ICSC_MODE_ENUM {
BYPASS_ICSC                              = 0x00000000,
COEF_ICSC                                = 0x00000001,
COEF_ICSC_B                              = 0x00000002,
} CM_ICSC_MODE_ENUM;

/*
 * CM_GAMUT_REMAP_MODE_ENUM enum
 */

typedef enum CM_GAMUT_REMAP_MODE_ENUM {
BYPASS_GAMUT                             = 0x00000000,
GAMUT_COEF                               = 0x00000001,
GAMUT_COEF_B                             = 0x00000002,
} CM_GAMUT_REMAP_MODE_ENUM;

/*
 * CM_COEF_FORMAT_ENUM enum
 */

typedef enum CM_COEF_FORMAT_ENUM {
FIX_S2_13                                = 0x00000000,
FIX_S3_12                                = 0x00000001,
} CM_COEF_FORMAT_ENUM;

/*
 * CMC_LUT_2_CONFIG_ENUM enum
 */

typedef enum CMC_LUT_2_CONFIG_ENUM {
CMC_LUT_2CFG_NO_MEMORY                   = 0x00000000,
CMC_LUT_2CFG_MEMORY_A                    = 0x00000001,
CMC_LUT_2CFG_MEMORY_B                    = 0x00000002,
} CMC_LUT_2_CONFIG_ENUM;

/*
 * CMC_LUT_2_MODE_ENUM enum
 */

typedef enum CMC_LUT_2_MODE_ENUM {
CMC_LUT_2_MODE_BYPASS                    = 0x00000000,
CMC_LUT_2_MODE_RAMA_LUT                  = 0x00000001,
CMC_LUT_2_MODE_RAMB_LUT                  = 0x00000002,
} CMC_LUT_2_MODE_ENUM;

/*
 * CMC_LUT_RAM_SEL enum
 */

typedef enum CMC_LUT_RAM_SEL {
CMC_RAMA_ACCESS                          = 0x00000000,
CMC_RAMB_ACCESS                          = 0x00000001,
} CMC_LUT_RAM_SEL;

/*
 * CMC_3DLUT_RAM_SEL enum
 */

typedef enum CMC_3DLUT_RAM_SEL {
CMC_RAM0_ACCESS                          = 0x00000000,
CMC_RAM1_ACCESS                          = 0x00000001,
CMC_RAM2_ACCESS                          = 0x00000002,
CMC_RAM3_ACCESS                          = 0x00000003,
} CMC_3DLUT_RAM_SEL;

/*
 * CMC_LUT_NUM_SEG enum
 */

typedef enum CMC_LUT_NUM_SEG {
CMC_SEGMENTS_1                           = 0x00000000,
CMC_SEGMENTS_2                           = 0x00000001,
CMC_SEGMENTS_4                           = 0x00000002,
CMC_SEGMENTS_8                           = 0x00000003,
CMC_SEGMENTS_16                          = 0x00000004,
CMC_SEGMENTS_32                          = 0x00000005,
CMC_SEGMENTS_64                          = 0x00000006,
CMC_SEGMENTS_128                         = 0x00000007,
} CMC_LUT_NUM_SEG;

/*
 * CMC_3DLUT_30BIT_ENUM enum
 */

typedef enum CMC_3DLUT_30BIT_ENUM {
CMC_3DLUT_36BIT                          = 0x00000000,
CMC_3DLUT_30BIT                          = 0x00000001,
} CMC_3DLUT_30BIT_ENUM;

/*
 * CMC_3DLUT_SIZE_ENUM enum
 */

typedef enum CMC_3DLUT_SIZE_ENUM {
CMC_3DLUT_17CUBE                         = 0x00000000,
CMC_3DLUT_9CUBE                          = 0x00000001,
} CMC_3DLUT_SIZE_ENUM;

/*******************************************************
 * DPP_TOP Enums
 *******************************************************/

/*
 * TEST_CLK_SEL enum
 */

typedef enum TEST_CLK_SEL {
TEST_CLK_SEL_0                           = 0x00000000,
TEST_CLK_SEL_1                           = 0x00000001,
TEST_CLK_SEL_2                           = 0x00000002,
TEST_CLK_SEL_3                           = 0x00000003,
TEST_CLK_SEL_4                           = 0x00000004,
TEST_CLK_SEL_5                           = 0x00000005,
TEST_CLK_SEL_6                           = 0x00000006,
TEST_CLK_SEL_7                           = 0x00000007,
TEST_CLK_SEL_8                           = 0x00000008,
} TEST_CLK_SEL;

/*
 * CRC_SRC_SEL enum
 */

typedef enum CRC_SRC_SEL {
CRC_SRC_0                                = 0x00000000,
CRC_SRC_1                                = 0x00000001,
CRC_SRC_2                                = 0x00000002,
CRC_SRC_3                                = 0x00000003,
} CRC_SRC_SEL;

/*
 * CRC_IN_PIX_SEL enum
 */

typedef enum CRC_IN_PIX_SEL {
CRC_IN_PIX_0                             = 0x00000000,
CRC_IN_PIX_1                             = 0x00000001,
CRC_IN_PIX_2                             = 0x00000002,
CRC_IN_PIX_3                             = 0x00000003,
CRC_IN_PIX_4                             = 0x00000004,
CRC_IN_PIX_5                             = 0x00000005,
CRC_IN_PIX_6                             = 0x00000006,
CRC_IN_PIX_7                             = 0x00000007,
} CRC_IN_PIX_SEL;

/*
 * CRC_CUR_BITS_SEL enum
 */

typedef enum CRC_CUR_BITS_SEL {
CRC_CUR_BITS_0                           = 0x00000000,
CRC_CUR_BITS_1                           = 0x00000001,
} CRC_CUR_BITS_SEL;

/*
 * CRC_IN_CUR_SEL enum
 */

typedef enum CRC_IN_CUR_SEL {
CRC_IN_CUR_0                             = 0x00000000,
CRC_IN_CUR_1                             = 0x00000001,
} CRC_IN_CUR_SEL;

/*
 * CRC_CUR_SEL enum
 */

typedef enum CRC_CUR_SEL {
CRC_CUR_0                                = 0x00000000,
CRC_CUR_1                                = 0x00000001,
} CRC_CUR_SEL;

/*
 * CRC_STEREO_SEL enum
 */

typedef enum CRC_STEREO_SEL {
CRC_STEREO_0                             = 0x00000000,
CRC_STEREO_1                             = 0x00000001,
CRC_STEREO_2                             = 0x00000002,
CRC_STEREO_3                             = 0x00000003,
} CRC_STEREO_SEL;

/*
 * CRC_INTERLACE_SEL enum
 */

typedef enum CRC_INTERLACE_SEL {
CRC_INTERLACE_0                          = 0x00000000,
CRC_INTERLACE_1                          = 0x00000001,
CRC_INTERLACE_2                          = 0x00000002,
CRC_INTERLACE_3                          = 0x00000003,
} CRC_INTERLACE_SEL;

/*******************************************************
 * DC_PERFMON Enums
 *******************************************************/

/*
 * PERFCOUNTER_CVALUE_SEL enum
 */

typedef enum PERFCOUNTER_CVALUE_SEL {
PERFCOUNTER_CVALUE_SEL_47_0              = 0x00000000,
PERFCOUNTER_CVALUE_SEL_15_0              = 0x00000001,
PERFCOUNTER_CVALUE_SEL_31_16             = 0x00000002,
PERFCOUNTER_CVALUE_SEL_47_32             = 0x00000003,
PERFCOUNTER_CVALUE_SEL_11_0              = 0x00000004,
PERFCOUNTER_CVALUE_SEL_23_12             = 0x00000005,
PERFCOUNTER_CVALUE_SEL_35_24             = 0x00000006,
PERFCOUNTER_CVALUE_SEL_47_36             = 0x00000007,
} PERFCOUNTER_CVALUE_SEL;

/*
 * PERFCOUNTER_INC_MODE enum
 */

typedef enum PERFCOUNTER_INC_MODE {
PERFCOUNTER_INC_MODE_MULTI_BIT           = 0x00000000,
PERFCOUNTER_INC_MODE_BOTH_EDGE           = 0x00000001,
PERFCOUNTER_INC_MODE_LSB                 = 0x00000002,
PERFCOUNTER_INC_MODE_POS_EDGE            = 0x00000003,
PERFCOUNTER_INC_MODE_NEG_EDGE            = 0x00000004,
} PERFCOUNTER_INC_MODE;

/*
 * PERFCOUNTER_HW_CNTL_SEL enum
 */

typedef enum PERFCOUNTER_HW_CNTL_SEL {
PERFCOUNTER_HW_CNTL_SEL_RUNEN            = 0x00000000,
PERFCOUNTER_HW_CNTL_SEL_CNTOFF           = 0x00000001,
} PERFCOUNTER_HW_CNTL_SEL;

/*
 * PERFCOUNTER_RUNEN_MODE enum
 */

typedef enum PERFCOUNTER_RUNEN_MODE {
PERFCOUNTER_RUNEN_MODE_LEVEL             = 0x00000000,
PERFCOUNTER_RUNEN_MODE_EDGE              = 0x00000001,
} PERFCOUNTER_RUNEN_MODE;

/*
 * PERFCOUNTER_CNTOFF_START_DIS enum
 */

typedef enum PERFCOUNTER_CNTOFF_START_DIS {
PERFCOUNTER_CNTOFF_START_ENABLE          = 0x00000000,
PERFCOUNTER_CNTOFF_START_DISABLE         = 0x00000001,
} PERFCOUNTER_CNTOFF_START_DIS;

/*
 * PERFCOUNTER_RESTART_EN enum
 */

typedef enum PERFCOUNTER_RESTART_EN {
PERFCOUNTER_RESTART_DISABLE              = 0x00000000,
PERFCOUNTER_RESTART_ENABLE               = 0x00000001,
} PERFCOUNTER_RESTART_EN;

/*
 * PERFCOUNTER_INT_EN enum
 */

typedef enum PERFCOUNTER_INT_EN {
PERFCOUNTER_INT_DISABLE                  = 0x00000000,
PERFCOUNTER_INT_ENABLE                   = 0x00000001,
} PERFCOUNTER_INT_EN;

/*
 * PERFCOUNTER_OFF_MASK enum
 */

typedef enum PERFCOUNTER_OFF_MASK {
PERFCOUNTER_OFF_MASK_DISABLE             = 0x00000000,
PERFCOUNTER_OFF_MASK_ENABLE              = 0x00000001,
} PERFCOUNTER_OFF_MASK;

/*
 * PERFCOUNTER_ACTIVE enum
 */

typedef enum PERFCOUNTER_ACTIVE {
PERFCOUNTER_IS_IDLE                      = 0x00000000,
PERFCOUNTER_IS_ACTIVE                    = 0x00000001,
} PERFCOUNTER_ACTIVE;

/*
 * PERFCOUNTER_INT_TYPE enum
 */

typedef enum PERFCOUNTER_INT_TYPE {
PERFCOUNTER_INT_TYPE_LEVEL               = 0x00000000,
PERFCOUNTER_INT_TYPE_PULSE               = 0x00000001,
} PERFCOUNTER_INT_TYPE;

/*
 * PERFCOUNTER_COUNTED_VALUE_TYPE enum
 */

typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
PERFCOUNTER_COUNTED_VALUE_TYPE_ACC       = 0x00000000,
PERFCOUNTER_COUNTED_VALUE_TYPE_MAX       = 0x00000001,
PERFCOUNTER_COUNTED_VALUE_TYPE_MIN       = 0x00000002,
} PERFCOUNTER_COUNTED_VALUE_TYPE;

/*
 * PERFCOUNTER_HW_STOP1_SEL enum
 */

typedef enum PERFCOUNTER_HW_STOP1_SEL {
PERFCOUNTER_HW_STOP1_0                   = 0x00000000,
PERFCOUNTER_HW_STOP1_1                   = 0x00000001,
} PERFCOUNTER_HW_STOP1_SEL;

/*
 * PERFCOUNTER_HW_STOP2_SEL enum
 */

typedef enum PERFCOUNTER_HW_STOP2_SEL {
PERFCOUNTER_HW_STOP2_0                   = 0x00000000,
PERFCOUNTER_HW_STOP2_1                   = 0x00000001,
} PERFCOUNTER_HW_STOP2_SEL;

/*
 * PERFCOUNTER_CNTL_SEL enum
 */

typedef enum PERFCOUNTER_CNTL_SEL {
PERFCOUNTER_CNTL_SEL_0                   = 0x00000000,
PERFCOUNTER_CNTL_SEL_1                   = 0x00000001,
PERFCOUNTER_CNTL_SEL_2                   = 0x00000002,
PERFCOUNTER_CNTL_SEL_3                   = 0x00000003,
PERFCOUNTER_CNTL_SEL_4                   = 0x00000004,
PERFCOUNTER_CNTL_SEL_5                   = 0x00000005,
PERFCOUNTER_CNTL_SEL_6                   = 0x00000006,
PERFCOUNTER_CNTL_SEL_7                   = 0x00000007,
} PERFCOUNTER_CNTL_SEL;

/*
 * PERFCOUNTER_CNT0_STATE enum
 */

typedef enum PERFCOUNTER_CNT0_STATE {
PERFCOUNTER_CNT0_STATE_RESET             = 0x00000000,
PERFCOUNTER_CNT0_STATE_START             = 0x00000001,
PERFCOUNTER_CNT0_STATE_FREEZE            = 0x00000002,
PERFCOUNTER_CNT0_STATE_HW                = 0x00000003,
} PERFCOUNTER_CNT0_STATE;

/*
 * PERFCOUNTER_STATE_SEL0 enum
 */

typedef enum PERFCOUNTER_STATE_SEL0 {
PERFCOUNTER_STATE_SEL0_GLOBAL            = 0x00000000,
PERFCOUNTER_STATE_SEL0_LOCAL             = 0x00000001,
} PERFCOUNTER_STATE_SEL0;

/*
 * PERFCOUNTER_CNT1_STATE enum
 */

typedef enum PERFCOUNTER_CNT1_STATE {
PERFCOUNTER_CNT1_STATE_RESET             = 0x00000000,
PERFCOUNTER_CNT1_STATE_START             = 0x00000001,
PERFCOUNTER_CNT1_STATE_FREEZE            = 0x00000002,
PERFCOUNTER_CNT1_STATE_HW                = 0x00000003,
} PERFCOUNTER_CNT1_STATE;

/*
 * PERFCOUNTER_STATE_SEL1 enum
 */

typedef enum PERFCOUNTER_STATE_SEL1 {
PERFCOUNTER_STATE_SEL1_GLOBAL            = 0x00000000,
PERFCOUNTER_STATE_SEL1_LOCAL             = 0x00000001,
} PERFCOUNTER_STATE_SEL1;

/*
 * PERFCOUNTER_CNT2_STATE enum
 */

typedef enum PERFCOUNTER_CNT2_STATE {
PERFCOUNTER_CNT2_STATE_RESET             = 0x00000000,
PERFCOUNTER_CNT2_STATE_START             = 0x00000001,
PERFCOUNTER_CNT2_STATE_FREEZE            = 0x00000002,
PERFCOUNTER_CNT2_STATE_HW                = 0x00000003,
} PERFCOUNTER_CNT2_STATE;

/*
 * PERFCOUNTER_STATE_SEL2 enum
 */

typedef enum PERFCOUNTER_STATE_SEL2 {
PERFCOUNTER_STATE_SEL2_GLOBAL            = 0x00000000,
PERFCOUNTER_STATE_SEL2_LOCAL             = 0x00000001,
} PERFCOUNTER_STATE_SEL2;

/*
 * PERFCOUNTER_CNT3_STATE enum
 */

typedef enum PERFCOUNTER_CNT3_STATE {
PERFCOUNTER_CNT3_STATE_RESET             = 0x00000000,
PERFCOUNTER_CNT3_STATE_START             = 0x00000001,
PERFCOUNTER_CNT3_STATE_FREEZE            = 0x00000002,
PERFCOUNTER_CNT3_STATE_HW                = 0x00000003,
} PERFCOUNTER_CNT3_STATE;

/*
 * PERFCOUNTER_STATE_SEL3 enum
 */

typedef enum PERFCOUNTER_STATE_SEL3 {
PERFCOUNTER_STATE_SEL3_GLOBAL            = 0x00000000,
PERFCOUNTER_STATE_SEL3_LOCAL             = 0x00000001,
} PERFCOUNTER_STATE_SEL3;

/*
 * PERFCOUNTER_CNT4_STATE enum
 */

typedef enum PERFCOUNTER_CNT4_STATE {
PERFCOUNTER_CNT4_STATE_RESET             = 0x00000000,
PERFCOUNTER_CNT4_STATE_START             = 0x00000001,
PERFCOUNTER_CNT4_STATE_FREEZE            = 0x00000002,
PERFCOUNTER_CNT4_STATE_HW                = 0x00000003,
} PERFCOUNTER_CNT4_STATE;

/*
 * PERFCOUNTER_STATE_SEL4 enum
 */

typedef enum PERFCOUNTER_STATE_SEL4 {
PERFCOUNTER_STATE_SEL4_GLOBAL            = 0x00000000,
PERFCOUNTER_STATE_SEL4_LOCAL             = 0x00000001,
} PERFCOUNTER_STATE_SEL4;

/*
 * PERFCOUNTER_CNT5_STATE enum
 */

typedef enum PERFCOUNTER_CNT5_STATE {
PERFCOUNTER_CNT5_STATE_RESET             = 0x00000000,
PERFCOUNTER_CNT5_STATE_START             = 0x00000001,
PERFCOUNTER_CNT5_STATE_FREEZE            = 0x00000002,
PERFCOUNTER_CNT5_STATE_HW                = 0x00000003,
} PERFCOUNTER_CNT5_STATE;

/*
 * PERFCOUNTER_STATE_SEL5 enum
 */

typedef enum PERFCOUNTER_STATE_SEL5 {
PERFCOUNTER_STATE_SEL5_GLOBAL            = 0x00000000,
PERFCOUNTER_STATE_SEL5_LOCAL             = 0x00000001,
} PERFCOUNTER_STATE_SEL5;

/*
 * PERFCOUNTER_CNT6_STATE enum
 */

typedef enum PERFCOUNTER_CNT6_STATE {
PERFCOUNTER_CNT6_STATE_RESET             = 0x00000000,
PERFCOUNTER_CNT6_STATE_START             = 0x00000001,
PERFCOUNTER_CNT6_STATE_FREEZE            = 0x00000002,
PERFCOUNTER_CNT6_STATE_HW                = 0x00000003,
} PERFCOUNTER_CNT6_STATE;

/*
 * PERFCOUNTER_STATE_SEL6 enum
 */

typedef enum PERFCOUNTER_STATE_SEL6 {
PERFCOUNTER_STATE_SEL6_GLOBAL            = 0x00000000,
PERFCOUNTER_STATE_SEL6_LOCAL             = 0x00000001,
} PERFCOUNTER_STATE_SEL6;

/*
 * PERFCOUNTER_CNT7_STATE enum
 */

typedef enum PERFCOUNTER_CNT7_STATE {
PERFCOUNTER_CNT7_STATE_RESET             = 0x00000000,
PERFCOUNTER_CNT7_STATE_START             = 0x00000001,
PERFCOUNTER_CNT7_STATE_FREEZE            = 0x00000002,
PERFCOUNTER_CNT7_STATE_HW                = 0x00000003,
} PERFCOUNTER_CNT7_STATE;

/*
 * PERFCOUNTER_STATE_SEL7 enum
 */

typedef enum PERFCOUNTER_STATE_SEL7 {
PERFCOUNTER_STATE_SEL7_GLOBAL            = 0x00000000,
PERFCOUNTER_STATE_SEL7_LOCAL             = 0x00000001,
} PERFCOUNTER_STATE_SEL7;

/*
 * PERFMON_STATE enum
 */

typedef enum PERFMON_STATE {
PERFMON_STATE_RESET                      = 0x00000000,
PERFMON_STATE_START                      = 0x00000001,
PERFMON_STATE_FREEZE                     = 0x00000002,
PERFMON_STATE_HW                         = 0x00000003,
} PERFMON_STATE;

/*
 * PERFMON_CNTOFF_AND_OR enum
 */

typedef enum PERFMON_CNTOFF_AND_OR {
PERFMON_CNTOFF_OR                        = 0x00000000,
PERFMON_CNTOFF_AND                       = 0x00000001,
} PERFMON_CNTOFF_AND_OR;

/*
 * PERFMON_CNTOFF_INT_EN enum
 */

typedef enum PERFMON_CNTOFF_INT_EN {
PERFMON_CNTOFF_INT_DISABLE               = 0x00000000,
PERFMON_CNTOFF_INT_ENABLE                = 0x00000001,
} PERFMON_CNTOFF_INT_EN;

/*
 * PERFMON_CNTOFF_INT_TYPE enum
 */

typedef enum PERFMON_CNTOFF_INT_TYPE {
PERFMON_CNTOFF_INT_TYPE_LEVEL            = 0x00000000,
PERFMON_CNTOFF_INT_TYPE_PULSE            = 0x00000001,
} PERFMON_CNTOFF_INT_TYPE;

/*******************************************************
 * HUBP Enums
 *******************************************************/

/*
 * ROTATION_ANGLE enum
 */

typedef enum ROTATION_ANGLE {
ROTATE_0_DEGREES                         = 0x00000000,
ROTATE_90_DEGREES                        = 0x00000001,
ROTATE_180_DEGREES                       = 0x00000002,
ROTATE_270_DEGREES                       = 0x00000003,
} ROTATION_ANGLE;

/*
 * H_MIRROR_EN enum
 */

typedef enum H_MIRROR_EN {
HW_MIRRORING_DISABLE                     = 0x00000000,
HW_MIRRORING_ENABLE                      = 0x00000001,
} H_MIRROR_EN;

/*
 * NUM_PIPES enum
 */

typedef enum NUM_PIPES {
ONE_PIPE                                 = 0x00000000,
TWO_PIPES                                = 0x00000001,
FOUR_PIPES                               = 0x00000002,
EIGHT_PIPES                              = 0x00000003,
SIXTEEN_PIPES                            = 0x00000004,
THIRTY_TWO_PIPES                         = 0x00000005,
SIXTY_FOUR_PIPES                         = 0x00000006,
} NUM_PIPES;

/*
 * NUM_BANKS enum
 */

typedef enum NUM_BANKS {
ONE_BANK                                 = 0x00000000,
TWO_BANKS                                = 0x00000001,
FOUR_BANKS                               = 0x00000002,
EIGHT_BANKS                              = 0x00000003,
SIXTEEN_BANKS                            = 0x00000004,
} NUM_BANKS;

/*
 * SW_MODE enum
 */

typedef enum SW_MODE {
SWIZZLE_LINEAR                           = 0x00000000,
SWIZZLE_4KB_S                            = 0x00000005,
SWIZZLE_4KB_D                            = 0x00000006,
SWIZZLE_64KB_S                           = 0x00000009,
SWIZZLE_64KB_D                           = 0x0000000a,
SWIZZLE_VAR_S                            = 0x0000000d,
SWIZZLE_VAR_D                            = 0x0000000e,
SWIZZLE_64KB_S_T                         = 0x00000011,
SWIZZLE_64KB_D_T                         = 0x00000012,
SWIZZLE_4KB_S_X                          = 0x00000015,
SWIZZLE_4KB_D_X                          = 0x00000016,
SWIZZLE_64KB_S_X                         = 0x00000019,
SWIZZLE_64KB_D_X                         = 0x0000001a,
SWIZZLE_64KB_R_X                         = 0x0000001b,
SWIZZLE_VAR_S_X                          = 0x0000001d,
SWIZZLE_VAR_D_X                          = 0x0000001e,
} SW_MODE;

/*
 * PIPE_INTERLEAVE enum
 */

typedef enum PIPE_INTERLEAVE {
PIPE_INTERLEAVE_256B                     = 0x00000000,
PIPE_INTERLEAVE_512B                     = 0x00000001,
PIPE_INTERLEAVE_1KB                      = 0x00000002,
} PIPE_INTERLEAVE;

/*
 * LEGACY_PIPE_INTERLEAVE enum
 */

typedef enum LEGACY_PIPE_INTERLEAVE {
LEGACY_PIPE_INTERLEAVE_256B              = 0x00000000,
LEGACY_PIPE_INTERLEAVE_512B              = 0x00000001,
} LEGACY_PIPE_INTERLEAVE;

/*
 * NUM_SE enum
 */

typedef enum NUM_SE {
ONE_SHADER_ENGIN                         = 0x00000000,
TWO_SHADER_ENGINS                        = 0x00000001,
FOUR_SHADER_ENGINS                       = 0x00000002,
EIGHT_SHADER_ENGINS                      = 0x00000003,
} NUM_SE;

/*
 * NUM_RB_PER_SE enum
 */

typedef enum NUM_RB_PER_SE {
ONE_RB_PER_SE                            = 0x00000000,
TWO_RB_PER_SE                            = 0x00000001,
FOUR_RB_PER_SE                           = 0x00000002,
} NUM_RB_PER_SE;

/*
 * MAX_COMPRESSED_FRAGS enum
 */

typedef enum MAX_COMPRESSED_FRAGS {
ONE_FRAGMENT                             = 0x00000000,
TWO_FRAGMENTS                            = 0x00000001,
FOUR_FRAGMENTS                           = 0x00000002,
EIGHT_FRAGMENTS                          = 0x00000003,
} MAX_COMPRESSED_FRAGS;

/*
 * DIM_TYPE enum
 */

typedef enum DIM_TYPE {
DIM_TYPE_1D                              = 0x00000000,
DIM_TYPE_2D                              = 0x00000001,
DIM_TYPE_3D                              = 0x00000002,
DIM_TYPE_RESERVED                        = 0x00000003,
} DIM_TYPE;

/*
 * META_LINEAR enum
 */

typedef enum META_LINEAR {
META_SURF_TILED                          = 0x00000000,
META_SURF_LINEAR                         = 0x00000001,
} META_LINEAR;

/*
 * RB_ALIGNED enum
 */

typedef enum RB_ALIGNED {
RB_UNALIGNED_META_SURF                   = 0x00000000,
RB_ALIGNED_META_SURF                     = 0x00000001,
} RB_ALIGNED;

/*
 * PIPE_ALIGNED enum
 */

typedef enum PIPE_ALIGNED {
PIPE_UNALIGNED_SURF                      = 0x00000000,
PIPE_ALIGNED_SURF                        = 0x00000001,
} PIPE_ALIGNED;

/*
 * ARRAY_MODE enum
 */

typedef enum ARRAY_MODE {
AM_LINEAR_GENERAL                        = 0x00000000,
AM_LINEAR_ALIGNED                        = 0x00000001,
AM_1D_TILED_THIN1                        = 0x00000002,
AM_1D_TILED_THICK                        = 0x00000003,
AM_2D_TILED_THIN1                        = 0x00000004,
AM_PRT_TILED_THIN1                       = 0x00000005,
AM_PRT_2D_TILED_THIN1                    = 0x00000006,
AM_2D_TILED_THICK                        = 0x00000007,
AM_2D_TILED_XTHICK                       = 0x00000008,
AM_PRT_TILED_THICK                       = 0x00000009,
AM_PRT_2D_TILED_THICK                    = 0x0000000a,
AM_PRT_3D_TILED_THIN1                    = 0x0000000b,
AM_3D_TILED_THIN1                        = 0x0000000c,
AM_3D_TILED_THICK                        = 0x0000000d,
AM_3D_TILED_XTHICK                       = 0x0000000e,
AM_PRT_3D_TILED_THICK                    = 0x0000000f,
} ARRAY_MODE;

/*
 * PIPE_CONFIG enum
 */

typedef enum PIPE_CONFIG {
P2                                       = 0x00000000,
P4_8x16                                  = 0x00000004,
P4_16x16                                 = 0x00000005,
P4_16x32                                 = 0x00000006,
P4_32x32                                 = 0x00000007,
P8_16x16_8x16                            = 0x00000008,
P8_16x32_8x16                            = 0x00000009,
P8_32x32_8x16                            = 0x0000000a,
P8_16x32_16x16                           = 0x0000000b,
P8_32x32_16x16                           = 0x0000000c,
P8_32x32_16x32                           = 0x0000000d,
P8_32x64_32x32                           = 0x0000000e,
P16_32x32_8x16                           = 0x00000010,
P16_32x32_16x16                          = 0x00000011,
P16_ADDR_SURF                            = 0x00000012,
} PIPE_CONFIG;

/*
 * MICRO_TILE_MODE_NEW enum
 */

typedef enum MICRO_TILE_MODE_NEW {
DISPLAY_MICRO_TILING                     = 0x00000000,
THIN_MICRO_TILING                        = 0x00000001,
DEPTH_MICRO_TILING                       = 0x00000002,
ROTATED_MICRO_TILING                     = 0x00000003,
THICK_MICRO_TILING                       = 0x00000004,
} MICRO_TILE_MODE_NEW;

/*
 * TILE_SPLIT enum
 */

typedef enum TILE_SPLIT {
SURF_TILE_SPLIT_64B                      = 0x00000000,
SURF_TILE_SPLIT_128B                     = 0x00000001,
SURF_TILE_SPLIT_256B                     = 0x00000002,
SURF_TILE_SPLIT_512B                     = 0x00000003,
SURF_TILE_SPLIT_1KB                      = 0x00000004,
SURF_TILE_SPLIT_2KB                      = 0x00000005,
SURF_TILE_SPLIT_4KB                      = 0x00000006,
} TILE_SPLIT;

/*
 * BANK_WIDTH enum
 */

typedef enum BANK_WIDTH {
SURF_BANK_WIDTH_1                        = 0x00000000,
SURF_BANK_WIDTH_2                        = 0x00000001,
SURF_BANK_WIDTH_4                        = 0x00000002,
SURF_BANK_WIDTH_8                        = 0x00000003,
} BANK_WIDTH;

/*
 * BANK_HEIGHT enum
 */

typedef enum BANK_HEIGHT {
SURF_BANK_HEIGHT_1                       = 0x00000000,
SURF_BANK_HEIGHT_2                       = 0x00000001,
SURF_BANK_HEIGHT_4                       = 0x00000002,
SURF_BANK_HEIGHT_8                       = 0x00000003,
} BANK_HEIGHT;

/*
 * MACRO_TILE_ASPECT enum
 */

typedef enum MACRO_TILE_ASPECT {
SURF_MACRO_ASPECT_1                      = 0x00000000,
SURF_MACRO_ASPECT_2                      = 0x00000001,
SURF_MACRO_ASPECT_4                      = 0x00000002,
SURF_MACRO_ASPECT_8                      = 0x00000003,
} MACRO_TILE_ASPECT;

/*
 * LEGACY_NUM_BANKS enum
 */

typedef enum LEGACY_NUM_BANKS {
SURF_2_BANK                              = 0x00000000,
SURF_4_BANK                              = 0x00000001,
SURF_8_BANK                              = 0x00000002,
SURF_16_BANK                             = 0x00000003,
} LEGACY_NUM_BANKS;

/*
 * SWATH_HEIGHT enum
 */

typedef enum SWATH_HEIGHT {
SWATH_HEIGHT_1L                          = 0x00000000,
SWATH_HEIGHT_2L                          = 0x00000001,
SWATH_HEIGHT_4L                          = 0x00000002,
SWATH_HEIGHT_8L                          = 0x00000003,
SWATH_HEIGHT_16L                         = 0x00000004,
} SWATH_HEIGHT;

/*
 * PTE_ROW_HEIGHT_LINEAR enum
 */

typedef enum PTE_ROW_HEIGHT_LINEAR {
PTE_ROW_HEIGHT_LINEAR_8L                 = 0x00000000,
PTE_ROW_HEIGHT_LINEAR_16L                = 0x00000001,
PTE_ROW_HEIGHT_LINEAR_32L                = 0x00000002,
PTE_ROW_HEIGHT_LINEAR_64L                = 0x00000003,
PTE_ROW_HEIGHT_LINEAR_128L               = 0x00000004,
PTE_ROW_HEIGHT_LINEAR_256L               = 0x00000005,
PTE_ROW_HEIGHT_LINEAR_512L               = 0x00000006,
PTE_ROW_HEIGHT_LINEAR_1024L              = 0x00000007,
} PTE_ROW_HEIGHT_LINEAR;

/*
 * CHUNK_SIZE enum
 */

typedef enum CHUNK_SIZE {
CHUNK_SIZE_1KB                           = 0x00000000,
CHUNK_SIZE_2KB                           = 0x00000001,
CHUNK_SIZE_4KB                           = 0x00000002,
CHUNK_SIZE_8KB                           = 0x00000003,
CHUNK_SIZE_16KB                          = 0x00000004,
CHUNK_SIZE_32KB                          = 0x00000005,
CHUNK_SIZE_64KB                          = 0x00000006,
} CHUNK_SIZE;

/*
 * MIN_CHUNK_SIZE enum
 */

typedef enum MIN_CHUNK_SIZE {
NO_MIN_CHUNK_SIZE                        = 0x00000000,
MIN_CHUNK_SIZE_256B                      = 0x00000001,
MIN_CHUNK_SIZE_512B                      = 0x00000002,
MIN_CHUNK_SIZE_1024B                     = 0x00000003,
} MIN_CHUNK_SIZE;

/*
 * META_CHUNK_SIZE enum
 */

typedef enum META_CHUNK_SIZE {
META_CHUNK_SIZE_1KB                      = 0x00000000,
META_CHUNK_SIZE_2KB                      = 0x00000001,
META_CHUNK_SIZE_4KB                      = 0x00000002,
META_CHUNK_SIZE_8KB                      = 0x00000003,
} META_CHUNK_SIZE;

/*
 * MIN_META_CHUNK_SIZE enum
 */

typedef enum MIN_META_CHUNK_SIZE {
NO_MIN_META_CHUNK_SIZE                   = 0x00000000,
MIN_META_CHUNK_SIZE_64B                  = 0x00000001,
MIN_META_CHUNK_SIZE_128B                 = 0x00000002,
MIN_META_CHUNK_SIZE_256B                 = 0x00000003,
} MIN_META_CHUNK_SIZE;

/*
 * DPTE_GROUP_SIZE enum
 */

typedef enum DPTE_GROUP_SIZE {
DPTE_GROUP_SIZE_64B                      = 0x00000000,
DPTE_GROUP_SIZE_128B                     = 0x00000001,
DPTE_GROUP_SIZE_256B                     = 0x00000002,
DPTE_GROUP_SIZE_512B                     = 0x00000003,
DPTE_GROUP_SIZE_1024B                    = 0x00000004,
DPTE_GROUP_SIZE_2048B                    = 0x00000005,
DPTE_GROUP_SIZE_4096B                    = 0x00000006,
DPTE_GROUP_SIZE_8192B                    = 0x00000007,
} DPTE_GROUP_SIZE;

/*
 * MPTE_GROUP_SIZE enum
 */

typedef enum MPTE_GROUP_SIZE {
MPTE_GROUP_SIZE_64B                      = 0x00000000,
MPTE_GROUP_SIZE_128B                     = 0x00000001,
MPTE_GROUP_SIZE_256B                     = 0x00000002,
MPTE_GROUP_SIZE_512B                     = 0x00000003,
MPTE_GROUP_SIZE_1024B                    = 0x00000004,
MPTE_GROUP_SIZE_2048B                    = 0x00000005,
MPTE_GROUP_SIZE_4096B                    = 0x00000006,
MPTE_GROUP_SIZE_8192B                    = 0x00000007,
} MPTE_GROUP_SIZE;

/*
 * HUBP_BLANK_EN enum
 */

typedef enum HUBP_BLANK_EN {
HUBP_BLANK_SW_DEASSERT                   = 0x00000000,
HUBP_BLANK_SW_ASSERT                     = 0x00000001,
} HUBP_BLANK_EN;

/*
 * HUBP_DISABLE enum
 */

typedef enum HUBP_DISABLE {
HUBP_ENABLED                             = 0x00000000,
HUBP_DISABLED                            = 0x00000001,
} HUBP_DISABLE;

/*
 * HUBP_TTU_DISABLE enum
 */

typedef enum HUBP_TTU_DISABLE {
HUBP_TTU_ENABLED                         = 0x00000000,
HUBP_TTU_DISABLED                        = 0x00000001,
} HUBP_TTU_DISABLE;

/*
 * HUBP_NO_OUTSTANDING_REQ enum
 */

typedef enum HUBP_NO_OUTSTANDING_REQ {
OUTSTANDING_REQ                          = 0x00000000,
NO_OUTSTANDING_REQ                       = 0x00000001,
} HUBP_NO_OUTSTANDING_REQ;

/*
 * HUBP_IN_BLANK enum
 */

typedef enum HUBP_IN_BLANK {
HUBP_IN_ACTIVE                           = 0x00000000,
HUBP_IN_VBLANK                           = 0x00000001,
} HUBP_IN_BLANK;

/*
 * HUBP_VTG_SEL enum
 */

typedef enum HUBP_VTG_SEL {
VTG_SEL_0                                = 0x00000000,
VTG_SEL_1                                = 0x00000001,
VTG_SEL_2                                = 0x00000002,
VTG_SEL_3                                = 0x00000003,
VTG_SEL_4                                = 0x00000004,
VTG_SEL_5                                = 0x00000005,
} HUBP_VTG_SEL;

/*
 * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
 */

typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
VREADY_BEFORE_VSYNC                      = 0x00000000,
VREADY_AT_OR_AFTER_VSYNC                 = 0x00000001,
} HUBP_VREADY_AT_OR_AFTER_VSYNC;

/*
 * VMPG_SIZE enum
 */

typedef enum VMPG_SIZE {
VMPG_SIZE_4KB                            = 0x00000000,
VMPG_SIZE_64KB                           = 0x00000001,
} VMPG_SIZE;

/*
 * HUBP_MEASURE_WIN_MODE_DCFCLK enum
 */

typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
HUBP_MEASURE_WIN_MODE_DCFCLK_0           = 0x00000000,
HUBP_MEASURE_WIN_MODE_DCFCLK_1           = 0x00000001,
HUBP_MEASURE_WIN_MODE_DCFCLK_2           = 0x00000002,
HUBP_MEASURE_WIN_MODE_DCFCLK_3           = 0x00000003,
} HUBP_MEASURE_WIN_MODE_DCFCLK;

/*******************************************************
 * HUBPREQ Enums
 *******************************************************/

/*
 * SURFACE_TMZ enum
 */

typedef enum SURFACE_TMZ {
SURFACE_IS_NOT_TMZ                       = 0x00000000,
SURFACE_IS_TMZ                           = 0x00000001,
} SURFACE_TMZ;

/*
 * SURFACE_DCC enum
 */

typedef enum SURFACE_DCC {
SURFACE_IS_NOT_DCC                       = 0x00000000,
SURFACE_IS_DCC                           = 0x00000001,
} SURFACE_DCC;

/*
 * SURFACE_DCC_IND_64B enum
 */

typedef enum SURFACE_DCC_IND_64B {
SURFACE_DCC_IS_NOT_IND_64B               = 0x00000000,
SURFACE_DCC_IS_IND_64B                   = 0x00000001,
} SURFACE_DCC_IND_64B;

/*
 * SURFACE_FLIP_TYPE enum
 */

typedef enum SURFACE_FLIP_TYPE {
SURFACE_V_FLIP                           = 0x00000000,
SURFACE_I_FLIP                           = 0x00000001,
} SURFACE_FLIP_TYPE;

/*
 * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
 */

typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
FLIP_ANY_FRAME                           = 0x00000000,
FLIP_LEFT_EYE                            = 0x00000001,
FLIP_RIGHT_EYE                           = 0x00000002,
SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED  = 0x00000003,
} SURFACE_FLIP_MODE_FOR_STEREOSYNC;

/*
 * SURFACE_UPDATE_LOCK enum
 */

typedef enum SURFACE_UPDATE_LOCK {
SURFACE_UPDATE_IS_UNLOCKED               = 0x00000000,
SURFACE_UPDATE_IS_LOCKED                 = 0x00000001,
} SURFACE_UPDATE_LOCK;

/*
 * SURFACE_FLIP_IN_STEREOSYNC enum
 */

typedef enum SURFACE_FLIP_IN_STEREOSYNC {
SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE      = 0x00000000,
SURFACE_FLIP_IN_STEREOSYNC_MODE          = 0x00000001,
} SURFACE_FLIP_IN_STEREOSYNC;

/*
 * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
 */

typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
SURFACE_FLIP_STEREO_SELECT_ENABLED       = 0x00000000,
SURFACE_FLIP_STEREO_SELECT_DISABLED      = 0x00000001,
} SURFACE_FLIP_STEREO_SELECT_DISABLE;

/*
 * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
 */

typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT  = 0x00000000,
SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT  = 0x00000001,
} SURFACE_FLIP_STEREO_SELECT_POLARITY;

/*
 * SURFACE_INUSE_RAED_NO_LATCH enum
 */

typedef enum SURFACE_INUSE_RAED_NO_LATCH {
SURFACE_INUSE_IS_LATCHED                 = 0x00000000,
SURFACE_INUSE_IS_NOT_LATCHED             = 0x00000001,
} SURFACE_INUSE_RAED_NO_LATCH;

/*
 * INT_MASK enum
 */

typedef enum INT_MASK {
INT_DISABLED                             = 0x00000000,
INT_ENABLED                              = 0x00000001,
} INT_MASK;

/*
 * SURFACE_FLIP_INT_TYPE enum
 */

typedef enum SURFACE_FLIP_INT_TYPE {
SURFACE_FLIP_INT_LEVEL                   = 0x00000000,
SURFACE_FLIP_INT_PULSE                   = 0x00000001,
} SURFACE_FLIP_INT_TYPE;

/*
 * SURFACE_FLIP_AWAY_INT_TYPE enum
 */

typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
SURFACE_FLIP_AWAY_INT_LEVEL              = 0x00000000,
SURFACE_FLIP_AWAY_INT_PULSE              = 0x00000001,
} SURFACE_FLIP_AWAY_INT_TYPE;

/*
 * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
 */

typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
SURFACE_FLIP_VUPDATE_SKIP_NUM_0          = 0x00000000,
SURFACE_FLIP_VUPDATE_SKIP_NUM_1          = 0x00000001,
SURFACE_FLIP_VUPDATE_SKIP_NUM_2          = 0x00000002,
SURFACE_FLIP_VUPDATE_SKIP_NUM_3          = 0x00000003,
SURFACE_FLIP_VUPDATE_SKIP_NUM_4          = 0x00000004,
SURFACE_FLIP_VUPDATE_SKIP_NUM_5          = 0x00000005,
SURFACE_FLIP_VUPDATE_SKIP_NUM_6          = 0x00000006,
SURFACE_FLIP_VUPDATE_SKIP_NUM_7          = 0x00000007,
SURFACE_FLIP_VUPDATE_SKIP_NUM_8          = 0x00000008,
SURFACE_FLIP_VUPDATE_SKIP_NUM_9          = 0x00000009,
SURFACE_FLIP_VUPDATE_SKIP_NUM_10         = 0x0000000a,
SURFACE_FLIP_VUPDATE_SKIP_NUM_11         = 0x0000000b,
SURFACE_FLIP_VUPDATE_SKIP_NUM_12         = 0x0000000c,
SURFACE_FLIP_VUPDATE_SKIP_NUM_13         = 0x0000000d,
SURFACE_FLIP_VUPDATE_SKIP_NUM_14         = 0x0000000e,
SURFACE_FLIP_VUPDATE_SKIP_NUM_15         = 0x0000000f,
} SURFACE_FLIP_VUPDATE_SKIP_NUM;

/*
 * DFQ_SIZE enum
 */

typedef enum DFQ_SIZE {
DFQ_SIZE_0                               = 0x00000000,
DFQ_SIZE_1                               = 0x00000001,
DFQ_SIZE_2                               = 0x00000002,
DFQ_SIZE_3                               = 0x00000003,
DFQ_SIZE_4                               = 0x00000004,
DFQ_SIZE_5                               = 0x00000005,
DFQ_SIZE_6                               = 0x00000006,
DFQ_SIZE_7                               = 0x00000007,
} DFQ_SIZE;

/*
 * DFQ_MIN_FREE_ENTRIES enum
 */

typedef enum DFQ_MIN_FREE_ENTRIES {
DFQ_MIN_FREE_ENTRIES_0                   = 0x00000000,
DFQ_MIN_FREE_ENTRIES_1                   = 0x00000001,
DFQ_MIN_FREE_ENTRIES_2                   = 0x00000002,
DFQ_MIN_FREE_ENTRIES_3                   = 0x00000003,
DFQ_MIN_FREE_ENTRIES_4                   = 0x00000004,
DFQ_MIN_FREE_ENTRIES_5                   = 0x00000005,
DFQ_MIN_FREE_ENTRIES_6                   = 0x00000006,
DFQ_MIN_FREE_ENTRIES_7                   = 0x00000007,
} DFQ_MIN_FREE_ENTRIES;

/*
 * DFQ_NUM_ENTRIES enum
 */

typedef enum DFQ_NUM_ENTRIES {
DFQ_NUM_ENTRIES_0                        = 0x00000000,
DFQ_NUM_ENTRIES_1                        = 0x00000001,
DFQ_NUM_ENTRIES_2                        = 0x00000002,
DFQ_NUM_ENTRIES_3                        = 0x00000003,
DFQ_NUM_ENTRIES_4                        = 0x00000004,
DFQ_NUM_ENTRIES_5                        = 0x00000005,
DFQ_NUM_ENTRIES_6                        = 0x00000006,
DFQ_NUM_ENTRIES_7                        = 0x00000007,
DFQ_NUM_ENTRIES_8                        = 0x00000008,
} DFQ_NUM_ENTRIES;

/*
 * FLIP_RATE enum
 */

typedef enum FLIP_RATE {
FLIP_RATE_0                              = 0x00000000,
FLIP_RATE_1                              = 0x00000001,
FLIP_RATE_2                              = 0x00000002,
FLIP_RATE_3                              = 0x00000003,
FLIP_RATE_4                              = 0x00000004,
FLIP_RATE_5                              = 0x00000005,
FLIP_RATE_6                              = 0x00000006,
FLIP_RATE_7                              = 0x00000007,
} FLIP_RATE;

/*******************************************************
 * HUBPRET Enums
 *******************************************************/

/*
 * DETILE_BUFFER_PACKER_ENABLE enum
 */

typedef enum DETILE_BUFFER_PACKER_ENABLE {
DETILE_BUFFER_PACKER_IS_DISABLE          = 0x00000000,
DETILE_BUFFER_PACKER_IS_ENABLE           = 0x00000001,
} DETILE_BUFFER_PACKER_ENABLE;

/*
 * CROSSBAR_FOR_ALPHA enum
 */

typedef enum CROSSBAR_FOR_ALPHA {
ALPHA_DATA_ON_ALPHA_PORT                 = 0x00000000,
ALPHA_DATA_ON_Y_G_PORT                   = 0x00000001,
ALPHA_DATA_ON_CB_B_PORT                  = 0x00000002,
ALPHA_DATA_ON_CR_R_PORT                  = 0x00000003,
} CROSSBAR_FOR_ALPHA;

/*
 * CROSSBAR_FOR_Y_G enum
 */

typedef enum CROSSBAR_FOR_Y_G {
Y_G_DATA_ON_ALPHA_PORT                   = 0x00000000,
Y_G_DATA_ON_Y_G_PORT                     = 0x00000001,
Y_G_DATA_ON_CB_B_PORT                    = 0x00000002,
Y_G_DATA_ON_CR_R_PORT                    = 0x00000003,
} CROSSBAR_FOR_Y_G;

/*
 * CROSSBAR_FOR_CB_B enum
 */

typedef enum CROSSBAR_FOR_CB_B {
CB_B_DATA_ON_ALPHA_PORT                  = 0x00000000,
CB_B_DATA_ON_Y_G_PORT                    = 0x00000001,
CB_B_DATA_ON_CB_B_PORT                   = 0x00000002,
CB_B_DATA_ON_CR_R_PORT                   = 0x00000003,
} CROSSBAR_FOR_CB_B;

/*
 * CROSSBAR_FOR_CR_R enum
 */

typedef enum CROSSBAR_FOR_CR_R {
CR_R_DATA_ON_ALPHA_PORT                  = 0x00000000,
CR_R_DATA_ON_Y_G_PORT                    = 0x00000001,
CR_R_DATA_ON_CB_B_PORT                   = 0x00000002,
CR_R_DATA_ON_CR_R_PORT                   = 0x00000003,
} CROSSBAR_FOR_CR_R;

/*
 * DET_MEM_PWR_LIGHT_SLEEP_MODE enum
 */

typedef enum DET_MEM_PWR_LIGHT_SLEEP_MODE {
DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF       = 0x00000000,
DET_MEM_POWER_LIGHT_SLEEP_MODE_1         = 0x00000001,
DET_MEM_POWER_LIGHT_SLEEP_MODE_2         = 0x00000002,
} DET_MEM_PWR_LIGHT_SLEEP_MODE;

/*
 * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
 */

typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF    = 0x00000000,
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1      = 0x00000001,
} PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE;

/*******************************************************
 * CURSOR Enums
 *******************************************************/

/*
 * CURSOR_ENABLE enum
 */

typedef enum CURSOR_ENABLE {
CURSOR_IS_DISABLE                        = 0x00000000,
CURSOR_IS_ENABLE                         = 0x00000001,
} CURSOR_ENABLE;

/*
 * CURSOR_2X_MAGNIFY enum
 */

typedef enum CURSOR_2X_MAGNIFY {
CURSOR_2X_MAGNIFY_IS_DISABLE             = 0x00000000,
CURSOR_2X_MAGNIFY_IS_ENABLE              = 0x00000001,
} CURSOR_2X_MAGNIFY;

/*
 * CURSOR_MODE enum
 */

typedef enum CURSOR_MODE {
CURSOR_MONO_2BIT                         = 0x00000000,
CURSOR_COLOR_24BIT_1BIT_AND              = 0x00000001,
CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT    = 0x00000002,
CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT  = 0x00000003,
CURSOR_COLOR_64BIT_FP_PREMULT            = 0x00000004,
CURSOR_COLOR_64BIT_FP_UNPREMULT          = 0x00000005,
} CURSOR_MODE;

/*
 * CURSOR_SURFACE_TMZ enum
 */

typedef enum CURSOR_SURFACE_TMZ {
CURSOR_SURFACE_IS_NOT_TMZ                = 0x00000000,
CURSOR_SURFACE_IS_TMZ                    = 0x00000001,
} CURSOR_SURFACE_TMZ;

/*
 * CURSOR_SNOOP enum
 */

typedef enum CURSOR_SNOOP {
CURSOR_IS_NOT_SNOOP                      = 0x00000000,
CURSOR_IS_SNOOP                          = 0x00000001,
} CURSOR_SNOOP;

/*
 * CURSOR_SYSTEM enum
 */

typedef enum CURSOR_SYSTEM {
CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS        = 0x00000000,
CURSOR_IN_GUEST_PHYSICAL_ADDRESS         = 0x00000001,
} CURSOR_SYSTEM;

/*
 * CURSOR_PITCH enum
 */

typedef enum CURSOR_PITCH {
CURSOR_PITCH_64_PIXELS                   = 0x00000000,
CURSOR_PITCH_128_PIXELS                  = 0x00000001,
CURSOR_PITCH_256_PIXELS                  = 0x00000002,
} CURSOR_PITCH;

/*
 * CURSOR_LINES_PER_CHUNK enum
 */

typedef enum CURSOR_LINES_PER_CHUNK {
CURSOR_LINE_PER_CHUNK_1                  = 0x00000000,
CURSOR_LINE_PER_CHUNK_2                  = 0x00000001,
CURSOR_LINE_PER_CHUNK_4                  = 0x00000002,
CURSOR_LINE_PER_CHUNK_8                  = 0x00000003,
CURSOR_LINE_PER_CHUNK_16                 = 0x00000004,
} CURSOR_LINES_PER_CHUNK;

/*
 * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
 */

typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED  = 0x00000000,
CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED  = 0x00000001,
} CURSOR_PERFMON_LATENCY_MEASURE_EN;

/*
 * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
 */

typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY  = 0x00000000,
CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY  = 0x00000001,
} CURSOR_PERFMON_LATENCY_MEASURE_SEL;

/*
 * CURSOR_STEREO_EN enum
 */

typedef enum CURSOR_STEREO_EN {
CURSOR_STEREO_IS_DISABLED                = 0x00000000,
CURSOR_STEREO_IS_ENABLED                 = 0x00000001,
} CURSOR_STEREO_EN;

/*
 * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
 */

typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0  = 0x00000000,
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1  = 0x00000001,
} CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS;

/*
 * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
 */

typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF      = 0x00000000,
CROB_MEM_POWER_LIGHT_SLEEP_MODE_1        = 0x00000001,
CROB_MEM_POWER_LIGHT_SLEEP_MODE_2        = 0x00000002,
} CROB_MEM_PWR_LIGHT_SLEEP_MODE;

/*
 * DMDATA_UPDATED enum
 */

typedef enum DMDATA_UPDATED {
DMDATA_NOT_UPDATED                       = 0x00000000,
DMDATA_WAS_UPDATED                       = 0x00000001,
} DMDATA_UPDATED;

/*
 * DMDATA_REPEAT enum
 */

typedef enum DMDATA_REPEAT {
DMDATA_USE_FOR_CURRENT_FRAME_ONLY        = 0x00000000,
DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES  = 0x00000001,
} DMDATA_REPEAT;

/*
 * DMDATA_MODE enum
 */

typedef enum DMDATA_MODE {
DMDATA_SOFTWARE_UPDATE_MODE              = 0x00000000,
DMDATA_HARDWARE_UPDATE_MODE              = 0x00000001,
} DMDATA_MODE;

/*
 * DMDATA_QOS_MODE enum
 */

typedef enum DMDATA_QOS_MODE {
DMDATA_QOS_LEVEL_FROM_TTU                = 0x00000000,
DMDATA_QOS_LEVEL_FROM_SOFTWARE           = 0x00000001,
} DMDATA_QOS_MODE;

/*
 * DMDATA_DONE enum
 */

typedef enum DMDATA_DONE {
DMDATA_NOT_SENT_TO_DIG                   = 0x00000000,
DMDATA_SENT_TO_DIG                       = 0x00000001,
} DMDATA_DONE;

/*
 * DMDATA_UNDERFLOW enum
 */

typedef enum DMDATA_UNDERFLOW {
DMDATA_NOT_UNDERFLOW                     = 0x00000000,
DMDATA_UNDERFLOWED                       = 0x00000001,
} DMDATA_UNDERFLOW;

/*
 * DMDATA_UNDERFLOW_CLEAR enum
 */

typedef enum DMDATA_UNDERFLOW_CLEAR {
DMDATA_DONT_CLEAR                        = 0x00000000,
DMDATA_CLEAR_UNDERFLOW_STATUS            = 0x00000001,
} DMDATA_UNDERFLOW_CLEAR;

/*******************************************************
 * HUBPXFC Enums
 *******************************************************/

/*
 * HUBP_XFC_PIXEL_FORMAT_ENUM enum
 */

typedef enum HUBP_XFC_PIXEL_FORMAT_ENUM {
HUBP_XFC_PIXEL_IS_32BPP                  = 0x00000000,
HUBP_XFC_PIXEL_IS_64BPP                  = 0x00000001,
} HUBP_XFC_PIXEL_FORMAT_ENUM;

/*
 * HUBP_XFC_FRAME_MODE_ENUM enum
 */

typedef enum HUBP_XFC_FRAME_MODE_ENUM {
HUBP_XFC_PARTIAL_FRAME_MODE              = 0x00000000,
HUBP_XFC_FULL_FRAME_MODE                 = 0x00000001,
} HUBP_XFC_FRAME_MODE_ENUM;

/*
 * HUBP_XFC_CHUNK_SIZE_ENUM enum
 */

typedef enum HUBP_XFC_CHUNK_SIZE_ENUM {
HUBP_XFC_CHUNK_SIZE_256B                 = 0x00000000,
HUBP_XFC_CHUNK_SIZE_512B                 = 0x00000001,
HUBP_XFC_CHUNK_SIZE_1KB                  = 0x00000002,
HUBP_XFC_CHUNK_SIZE_2KB                  = 0x00000003,
HUBP_XFC_CHUNK_SIZE_4KB                  = 0x00000004,
HUBP_XFC_CHUNK_SIZE_8KB                  = 0x00000005,
HUBP_XFC_CHUNK_SIZE_16KB                 = 0x00000006,
HUBP_XFC_CHUNK_SIZE_32KB                 = 0x00000007,
} HUBP_XFC_CHUNK_SIZE_ENUM;

/*******************************************************
 * XFC Enums
 *******************************************************/

/*
 * MMHUBBUB_XFC_XFCMON_MODE_ENUM enum
 */

typedef enum MMHUBBUB_XFC_XFCMON_MODE_ENUM {
MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT        = 0x00000000,
MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS      = 0x00000001,
MMHUBBUB_XFC_XFCMON_MODE_PERIODS         = 0x00000002,
} MMHUBBUB_XFC_XFCMON_MODE_ENUM;

/*
 * MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM enum
 */

typedef enum MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM {
MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB  = 0x00000000,
MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB  = 0x00000001,
} MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM;

/*******************************************************
 * XFCP Enums
 *******************************************************/

/*
 * MMHUBBUB_XFC_PIXEL_FORMAT_ENUM enum
 */

typedef enum MMHUBBUB_XFC_PIXEL_FORMAT_ENUM {
MMHUBBUB_XFC_PIXEL_IS_32BPP              = 0x00000000,
MMHUBBUB_XFC_PIXEL_IS_64BPP              = 0x00000001,
} MMHUBBUB_XFC_PIXEL_FORMAT_ENUM;

/*
 * MMHUBBUB_XFC_FRAME_MODE_ENUM enum
 */

typedef enum MMHUBBUB_XFC_FRAME_MODE_ENUM {
MMHUBBUB_XFC_PARTIAL_FRAME_MODE          = 0x00000000,
MMHUBBUB_XFC_FULL_FRAME_MODE             = 0x00000001,
} MMHUBBUB_XFC_FRAME_MODE_ENUM;

/*******************************************************
 * MPC_CFG Enums
 *******************************************************/

/*
 * MPC_CFG_MPC_TEST_CLK_SEL enum
 */

typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
MPC_CFG_MPC_TEST_CLK_SEL_0               = 0x00000000,
MPC_CFG_MPC_TEST_CLK_SEL_1               = 0x00000001,
MPC_CFG_MPC_TEST_CLK_SEL_2               = 0x00000002,
MPC_CFG_MPC_TEST_CLK_SEL_3               = 0x00000003,
} MPC_CFG_MPC_TEST_CLK_SEL;

/*
 * MPC_CRC_CALC_MODE enum
 */

typedef enum MPC_CRC_CALC_MODE {
MPC_CRC_ONE_SHOT_MODE                    = 0x00000000,
MPC_CRC_CONTINUOUS_MODE                  = 0x00000001,
} MPC_CRC_CALC_MODE;

/*
 * MPC_CRC_CALC_STEREO_MODE enum
 */

typedef enum MPC_CRC_CALC_STEREO_MODE {
MPC_CRC_STEREO_MODE_LEFT                 = 0x00000000,
MPC_CRC_STEREO_MODE_RIGHT                = 0x00000001,
MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT     = 0x00000002,
MPC_CRC_STEREO_MODE_BOTH_RESET_EACH      = 0x00000003,
} MPC_CRC_CALC_STEREO_MODE;

/*
 * MPC_CRC_CALC_INTERLACE_MODE enum
 */

typedef enum MPC_CRC_CALC_INTERLACE_MODE {
MPC_CRC_INTERLACE_MODE_TOP               = 0x00000000,
MPC_CRC_INTERLACE_MODE_BOTTOM            = 0x00000001,
MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM  = 0x00000002,
MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH   = 0x00000003,
} MPC_CRC_CALC_INTERLACE_MODE;

/*
 * MPC_CRC_SOURCE_SELECT enum
 */

typedef enum MPC_CRC_SOURCE_SELECT {
MPC_CRC_SOURCE_SEL_DPP                   = 0x00000000,
MPC_CRC_SOURCE_SEL_OPP                   = 0x00000001,
MPC_CRC_SOURCE_SEL_DWB                   = 0x00000002,
MPC_CRC_SOURCE_SEL_OTHER                 = 0x00000003,
} MPC_CRC_SOURCE_SELECT;

/*
 * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
 */

typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE  = 0x00000000,
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE  = 0x00000001,
} MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET;

/*
 * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
 */

typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE   = 0x00000000,
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE    = 0x00000001,
} MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET;

/*
 * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
 */

typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE       = 0x00000000,
MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE        = 0x00000001,
} MPC_CFG_CFG_VUPDATE_LOCK_SET;

/*
 * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
 */

typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE       = 0x00000000,
MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE        = 0x00000001,
} MPC_CFG_ADR_VUPDATE_LOCK_SET;

/*
 * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
 */

typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE       = 0x00000000,
MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE        = 0x00000001,
} MPC_CFG_CUR_VUPDATE_LOCK_SET;

/*
 * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
 */

typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
MPC_OUT_RATE_CONTROL_SET_ENABLE          = 0x00000000,
MPC_OUT_RATE_CONTROL_SET_DISABLE         = 0x00000001,
} MPC_OUT_RATE_CONTROL_DISABLE_SET;

/*
 * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
 */

typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS  = 0x00000000,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS  = 0x00000001,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS  = 0x00000002,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS  = 0x00000003,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS  = 0x00000004,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS  = 0x00000005,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS  = 0x00000006,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH  = 0x00000007,
} MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE;

/*******************************************************
 * MPC_OCSC Enums
 *******************************************************/

/*
 * MPC_OCSC_COEF_FORMAT enum
 */

typedef enum MPC_OCSC_COEF_FORMAT {
MPC_OCSC_COEF_FORMAT_S2_13               = 0x00000000,
MPC_OCSC_COEF_FORMAT_S3_12               = 0x00000001,
} MPC_OCSC_COEF_FORMAT;

/*
 * MPC_OUT_CSC_MODE enum
 */

typedef enum MPC_OUT_CSC_MODE {
MPC_OUT_CSC_MODE_0                       = 0x00000000,
MPC_OUT_CSC_MODE_1                       = 0x00000001,
MPC_OUT_CSC_MODE_2                       = 0x00000002,
MPC_OUT_CSC_MODE_RSV                     = 0x00000003,
} MPC_OUT_CSC_MODE;

/*******************************************************
 * MPCC Enums
 *******************************************************/

/*
 * MPCC_CONTROL_MPCC_MODE enum
 */

typedef enum MPCC_CONTROL_MPCC_MODE {
MPCC_CONTROL_MPCC_MODE_BYPASS            = 0x00000000,
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH  = 0x00000001,
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY    = 0x00000002,
MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING  = 0x00000003,
} MPCC_CONTROL_MPCC_MODE;

/*
 * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
 */

typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA  = 0x00000000,
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN  = 0x00000001,
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA  = 0x00000002,
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED  = 0x00000003,
} MPCC_CONTROL_MPCC_ALPHA_BLND_MODE;

/*
 * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
 */

typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE  = 0x00000000,
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE  = 0x00000001,
} MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE;

/*
 * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
 */

typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE  = 0x00000000,
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE  = 0x00000001,
} MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY;

/*
 * MPCC_SM_CONTROL_MPCC_SM_EN enum
 */

typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
MPCC_SM_CONTROL_MPCC_SM_EN_FALSE         = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_EN_TRUE          = 0x00000001,
} MPCC_SM_CONTROL_MPCC_SM_EN;

/*
 * MPCC_SM_CONTROL_MPCC_SM_MODE enum
 */

typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE  = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING  = 0x00000002,
MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING  = 0x00000004,
MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING  = 0x00000006,
} MPCC_SM_CONTROL_MPCC_SM_MODE;

/*
 * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
 */

typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE  = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE   = 0x00000001,
} MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT;

/*
 * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
 */

typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE  = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE   = 0x00000001,
} MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT;

/*
 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
 */

typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE  = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED  = 0x00000001,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW  = 0x00000002,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH  = 0x00000003,
} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL;

/*
 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
 */

typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE  = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED  = 0x00000001,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW  = 0x00000002,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH  = 0x00000003,
} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL;

/*
 * MPCC_STALL_STATUS_MPCC_STALL_INT_ACK enum
 */

typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_ACK {
MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE = 0x00000000,
MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE = 0x00000001,
} MPCC_STALL_STATUS_MPCC_STALL_INT_ACK;

/*
 * MPCC_STALL_STATUS_MPCC_STALL_INT_MASK enum
 */

typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_MASK {
MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE  = 0x00000000,
MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE  = 0x00000001,
} MPCC_STALL_STATUS_MPCC_STALL_INT_MASK;

/*
 * MPCC_BG_COLOR_BPC enum
 */

typedef enum MPCC_BG_COLOR_BPC {
MPCC_BG_COLOR_BPC_8bit                   = 0x00000000,
MPCC_BG_COLOR_BPC_9bit                   = 0x00000001,
MPCC_BG_COLOR_BPC_10bit                  = 0x00000002,
MPCC_BG_COLOR_BPC_11bit                  = 0x00000003,
MPCC_BG_COLOR_BPC_12bit                  = 0x00000004,
} MPCC_BG_COLOR_BPC;

/*
 * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
 */

typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0        = 0x00000000,
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1        = 0x00000001,
} MPCC_CONTROL_MPCC_BOT_GAIN_MODE;

/*******************************************************
 * MPCC_OGAM Enums
 *******************************************************/

/*
 * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
 */

typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA  = 0x00000000,
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB  = 0x00000001,
} MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL;

/*
 * MPCC_OGAM_MODE_MPCC_OGAM_MODE enum
 */

typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE {
MPCC_OGAM_MODE_0                         = 0x00000000,
MPCC_OGAM_MODE_1                         = 0x00000001,
MPCC_OGAM_MODE_2                         = 0x00000002,
MPCC_OGAM_MODE_RSV                       = 0x00000003,
} MPCC_OGAM_MODE_MPCC_OGAM_MODE;

/*******************************************************
 * DPG Enums
 *******************************************************/

/*
 * ENUM_DPG_EN enum
 */

typedef enum ENUM_DPG_EN {
ENUM_DPG_DISABLE                         = 0x00000000,
ENUM_DPG_ENABLE                          = 0x00000001,
} ENUM_DPG_EN;

/*
 * ENUM_DPG_MODE enum
 */

typedef enum ENUM_DPG_MODE {
ENUM_DPG_MODE_RGB_COLOUR_BLOCK           = 0x00000000,
ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK     = 0x00000001,
ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK     = 0x00000002,
ENUM_DPG_MODE_VERTICAL_BAR               = 0x00000003,
ENUM_DPG_MODE_HORIZONTAL_BAR             = 0x00000004,
ENUM_DPG_MODE_RGB_SINGLE_RAMP            = 0x00000005,
ENUM_DPG_MODE_RGB_DUAL_RAMP              = 0x00000006,
ENUM_DPG_MODE_RGB_XR_BIAS                = 0x00000007,
} ENUM_DPG_MODE;

/*
 * ENUM_DPG_DYNAMIC_RANGE enum
 */

typedef enum ENUM_DPG_DYNAMIC_RANGE {
ENUM_DPG_DYNAMIC_RANGE_VESA              = 0x00000000,
ENUM_DPG_DYNAMIC_RANGE_CEA               = 0x00000001,
} ENUM_DPG_DYNAMIC_RANGE;

/*
 * ENUM_DPG_BIT_DEPTH enum
 */

typedef enum ENUM_DPG_BIT_DEPTH {
ENUM_DPG_BIT_DEPTH_6BPC                  = 0x00000000,
ENUM_DPG_BIT_DEPTH_8BPC                  = 0x00000001,
ENUM_DPG_BIT_DEPTH_10BPC                 = 0x00000002,
ENUM_DPG_BIT_DEPTH_12BPC                 = 0x00000003,
} ENUM_DPG_BIT_DEPTH;

/*
 * ENUM_DPG_FIELD_POLARITY enum
 */

typedef enum ENUM_DPG_FIELD_POLARITY {
ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD  = 0x00000000,
ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN  = 0x00000001,
} ENUM_DPG_FIELD_POLARITY;

/*******************************************************
 * FMT Enums
 *******************************************************/

/*
 * FMT_CONTROL_PIXEL_ENCODING enum
 */

typedef enum FMT_CONTROL_PIXEL_ENCODING {
FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444  = 0x00000000,
FMT_CONTROL_PIXEL_ENCODING_YCBCR422      = 0x00000001,
FMT_CONTROL_PIXEL_ENCODING_YCBCR420      = 0x00000002,
FMT_CONTROL_PIXEL_ENCODING_RESERVED      = 0x00000003,
} FMT_CONTROL_PIXEL_ENCODING;

/*
 * FMT_CONTROL_SUBSAMPLING_MODE enum
 */

typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
FMT_CONTROL_SUBSAMPLING_MODE_DROP        = 0x00000000,
FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE     = 0x00000001,
FMT_CONTROL_SUBSAMPLING_MOME_3_TAP       = 0x00000002,
FMT_CONTROL_SUBSAMPLING_MOME_RESERVED    = 0x00000003,
} FMT_CONTROL_SUBSAMPLING_MODE;

/*
 * FMT_CONTROL_SUBSAMPLING_ORDER enum
 */

typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR  = 0x00000000,
FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB  = 0x00000001,
} FMT_CONTROL_SUBSAMPLING_ORDER;

/*
 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
 */

typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE  = 0x00000000,
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE  = 0x00000001,
} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;

/*
 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
 */

typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION  = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING  = 0x00000001,
} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;

/*
 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
 */

typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP  = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP  = 0x00000001,
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP  = 0x00000002,
} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;

/*
 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
 */

typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP  = 0x00000000,
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP  = 0x00000001,
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP  = 0x00000002,
} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;

/*
 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
 */

typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP  = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP  = 0x00000001,
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP  = 0x00000002,
} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;

/*
 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
 */

typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2  = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4  = 0x00000001,
} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;

/*
 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
 */

typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei       = 0x00000000,
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi       = 0x00000001,
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi       = 0x00000002,
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED  = 0x00000003,
} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;

/*
 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
 */

typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A        = 0x00000000,
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B        = 0x00000001,
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C        = 0x00000002,
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D        = 0x00000003,
} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;

/*
 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
 */

typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E        = 0x00000000,
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F        = 0x00000001,
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G        = 0x00000002,
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED  = 0x00000003,
} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;

/*
 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
 */

typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR  = 0x00000000,
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB  = 0x00000001,
} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;

/*
 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
 */

typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC         = 0x00000000,
FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC         = 0x00000001,
FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC        = 0x00000002,
FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC        = 0x00000003,
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1    = 0x00000004,
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2    = 0x00000005,
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3    = 0x00000006,
FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE  = 0x00000007,
} FMT_CLAMP_CNTL_COLOR_FORMAT;

/*
 * FMT_SPATIAL_DITHER_MODE enum
 */

typedef enum FMT_SPATIAL_DITHER_MODE {
FMT_SPATIAL_DITHER_MODE_0                = 0x00000000,
FMT_SPATIAL_DITHER_MODE_1                = 0x00000001,
FMT_SPATIAL_DITHER_MODE_2                = 0x00000002,
FMT_SPATIAL_DITHER_MODE_3                = 0x00000003,
} FMT_SPATIAL_DITHER_MODE;

/*
 * FMT_DYNAMIC_EXP_MODE enum
 */

typedef enum FMT_DYNAMIC_EXP_MODE {
FMT_DYNAMIC_EXP_MODE_10to12              = 0x00000000,
FMT_DYNAMIC_EXP_MODE_8to12               = 0x00000001,
} FMT_DYNAMIC_EXP_MODE;

/*
 * FMTMEM_PWR_FORCE_CTRL enum
 */

typedef enum FMTMEM_PWR_FORCE_CTRL {
FMTMEM_NO_FORCE_REQUEST                  = 0x00000000,
FMTMEM_FORCE_LIGHT_SLEEP_REQUEST         = 0x00000001,
FMTMEM_FORCE_DEEP_SLEEP_REQUEST          = 0x00000002,
FMTMEM_FORCE_SHUT_DOWN_REQUEST           = 0x00000003,
} FMTMEM_PWR_FORCE_CTRL;

/*
 * FMTMEM_PWR_DIS_CTRL enum
 */

typedef enum FMTMEM_PWR_DIS_CTRL {
FMTMEM_ENABLE_MEM_PWR_CTRL               = 0x00000000,
FMTMEM_DISABLE_MEM_PWR_CTRL              = 0x00000001,
} FMTMEM_PWR_DIS_CTRL;

/*
 * FMT_POWER_STATE_ENUM enum
 */

typedef enum FMT_POWER_STATE_ENUM {
FMT_POWER_STATE_ENUM_ON                  = 0x00000000,
FMT_POWER_STATE_ENUM_LS                  = 0x00000001,
FMT_POWER_STATE_ENUM_DS                  = 0x00000002,
FMT_POWER_STATE_ENUM_SD                  = 0x00000003,
} FMT_POWER_STATE_ENUM;

/*
 * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
 */

typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
FMT_STEREOSYNC_OVERRIDE_CONTROL_0        = 0x00000000,
FMT_STEREOSYNC_OVERRIDE_CONTROL_1        = 0x00000001,
} FMT_STEREOSYNC_OVERRIDE_CONTROL;

/*
 * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
 */

typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP  = 0x00000000,
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1  = 0x00000001,
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2  = 0x00000002,
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED  = 0x00000003,
} FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL;

/*
 * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
 */

typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME  = 0x00000000,
FMT_FRAME_RANDOM_ENABLE_RESET_ONCE       = 0x00000001,
} FMT_FRAME_RANDOM_ENABLE_CONTROL;

/*
 * FMT_RGB_RANDOM_ENABLE_CONTROL enum
 */

typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE    = 0x00000000,
FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE     = 0x00000001,
} FMT_RGB_RANDOM_ENABLE_CONTROL;

/*
 * ENUM_FMT_PTI_FIELD_POLARITY enum
 */

typedef enum ENUM_FMT_PTI_FIELD_POLARITY {
ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD  = 0x00000000,
ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN  = 0x00000001,
} ENUM_FMT_PTI_FIELD_POLARITY;

/*******************************************************
 * OPP_PIPE Enums
 *******************************************************/

/*
 * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
 */

typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
OPP_PIPE_CLOCK_DISABLE                   = 0x00000000,
OPP_PIPE_CLOCK_ENABLE                    = 0x00000001,
} OPP_PIPE_CLOCK_ENABLE_CONTROL;

/*
 * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
 */

typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
OPP_PIPE_DIGTIAL_BYPASS_DISABLE          = 0x00000000,
OPP_PIPE_DIGTIAL_BYPASS_ENABLE           = 0x00000001,
} OPP_PIPE_DIGTIAL_BYPASS_CONTROL;

/*******************************************************
 * OPP_PIPE_CRC Enums
 *******************************************************/

/*
 * OPP_PIPE_CRC_EN enum
 */

typedef enum OPP_PIPE_CRC_EN {
OPP_PIPE_CRC_DISABLE                     = 0x00000000,
OPP_PIPE_CRC_ENABLE                      = 0x00000001,
} OPP_PIPE_CRC_EN;

/*
 * OPP_PIPE_CRC_CONT_EN enum
 */

typedef enum OPP_PIPE_CRC_CONT_EN {
OPP_PIPE_CRC_MODE_ONE_SHOT               = 0x00000000,
OPP_PIPE_CRC_MODE_CONTINUOUS             = 0x00000001,
} OPP_PIPE_CRC_CONT_EN;

/*
 * OPP_PIPE_CRC_STEREO_MODE enum
 */

typedef enum OPP_PIPE_CRC_STEREO_MODE {
OPP_PIPE_CRC_STEREO_MODE_LEFT            = 0x00000000,
OPP_PIPE_CRC_STEREO_MODE_RIGHT           = 0x00000001,
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE  = 0x00000002,
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE  = 0x00000003,
} OPP_PIPE_CRC_STEREO_MODE;

/*
 * OPP_PIPE_CRC_STEREO_EN enum
 */

typedef enum OPP_PIPE_CRC_STEREO_EN {
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO  = 0x00000000,
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO  = 0x00000001,
} OPP_PIPE_CRC_STEREO_EN;

/*
 * OPP_PIPE_CRC_INTERLACE_MODE enum
 */

typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
OPP_PIPE_CRC_INTERLACE_MODE_TOP          = 0x00000000,
OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM       = 0x00000001,
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD  = 0x00000002,
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD  = 0x00000003,
} OPP_PIPE_CRC_INTERLACE_MODE;

/*
 * OPP_PIPE_CRC_INTERLACE_EN enum
 */

typedef enum OPP_PIPE_CRC_INTERLACE_EN {
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE  = 0x00000000,
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED  = 0x00000001,
} OPP_PIPE_CRC_INTERLACE_EN;

/*
 * OPP_PIPE_CRC_PIXEL_SELECT enum
 */

typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS     = 0x00000000,
OPP_PIPE_CRC_PIXEL_SELECT_RESERVED       = 0x00000001,
OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS    = 0x00000002,
OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS     = 0x00000003,
} OPP_PIPE_CRC_PIXEL_SELECT;

/*
 * OPP_PIPE_CRC_SOURCE_SELECT enum
 */

typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
OPP_PIPE_CRC_SOURCE_SELECT_FMT           = 0x00000000,
OPP_PIPE_CRC_SOURCE_SELECT_SFT           = 0x00000001,
} OPP_PIPE_CRC_SOURCE_SELECT;

/*
 * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
 */

typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING  = 0x00000000,
OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING    = 0x00000001,
} OPP_PIPE_CRC_ONE_SHOT_PENDING;

/*******************************************************
 * OPP_TOP Enums
 *******************************************************/

/*
 * OPP_TOP_CLOCK_GATING_CONTROL enum
 */

typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
OPP_TOP_CLOCK_GATING_ENABLED             = 0x00000000,
OPP_TOP_CLOCK_GATING_DISABLED            = 0x00000001,
} OPP_TOP_CLOCK_GATING_CONTROL;

/*
 * OPP_TOP_CLOCK_ENABLE_STATUS enum
 */

typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
OPP_TOP_CLOCK_DISABLED_STATUS            = 0x00000000,
OPP_TOP_CLOCK_ENABLED_STATUS             = 0x00000001,
} OPP_TOP_CLOCK_ENABLE_STATUS;

/*
 * OPP_TEST_CLK_SEL_CONTROL enum
 */

typedef enum OPP_TEST_CLK_SEL_CONTROL {
OPP_TEST_CLK_SEL_DISPCLK_P               = 0x00000000,
OPP_TEST_CLK_SEL_DISPCLK_R               = 0x00000001,
OPP_TEST_CLK_SEL_DISPCLK_ABM0            = 0x00000002,
OPP_TEST_CLK_SEL_RESERVED0               = 0x00000003,
OPP_TEST_CLK_SEL_DISPCLK_OPP0            = 0x00000004,
OPP_TEST_CLK_SEL_DISPCLK_OPP1            = 0x00000005,
OPP_TEST_CLK_SEL_DISPCLK_OPP2            = 0x00000006,
OPP_TEST_CLK_SEL_DISPCLK_OPP3            = 0x00000007,
OPP_TEST_CLK_SEL_DISPCLK_OPP4            = 0x00000008,
OPP_TEST_CLK_SEL_DISPCLK_OPP5            = 0x00000009,
} OPP_TEST_CLK_SEL_CONTROL;

/*******************************************************
 * OTG Enums
 *******************************************************/

/*
 * OTG_CONTROL_OTG_START_POINT_CNTL enum
 */

typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL  = 0x00000000,
OTG_CONTROL_OTG_START_POINT_CNTL_DP      = 0x00000001,
} OTG_CONTROL_OTG_START_POINT_CNTL;

/*
 * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
 */

typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP     = 0x00000001,
} OTG_CONTROL_OTG_FIELD_NUMBER_CNTL;

/*
 * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
 */

typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE  = 0x00000000,
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT  = 0x00000001,
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED  = 0x00000002,
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST  = 0x00000003,
} OTG_CONTROL_OTG_DISABLE_POINT_CNTL;

/*
 * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
 */

typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE  = 0x00000000,
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE  = 0x00000001,
} OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY;

/*
 * OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE enum
 */

typedef enum OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE {
OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE  = 0x00000000,
OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE  = 0x00000001,
} OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE;

/*
 * OTG_CONTROL_OTG_SOF_PULL_EN enum
 */

typedef enum OTG_CONTROL_OTG_SOF_PULL_EN {
OTG_CONTROL_OTG_SOF_PULL_EN_FALSE        = 0x00000000,
OTG_CONTROL_OTG_SOF_PULL_EN_TRUE         = 0x00000001,
} OTG_CONTROL_OTG_SOF_PULL_EN;

/*
 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
 */

typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE  = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE  = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL;

/*
 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
 */

typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE  = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE  = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL;

/*
 * OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN enum
 */

typedef enum OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN {
OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE  = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE  = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN;

/*
 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
 */

typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE  = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC;

/*
 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
 */

typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE  = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT;

/*
 * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
 */

typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0  = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1  = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD;

/*
 * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
 */

typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE  = 0x00000001,
} OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;

/*
 * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
 */

typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE  = 0x00000001,
} OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR;

/*
 * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
 */

typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE  = 0x00000000,
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE  = 0x00000001,
} OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN;

/*
 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
 */

typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0  = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN  = 0x00000001,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN  = 0x00000002,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN  = 0x00000003,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN  = 0x00000004,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN  = 0x00000005,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN  = 0x00000006,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN  = 0x00000007,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN  = 0x00000008,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN  = 0x00000009,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN  = 0x0000000a,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1  = 0x0000000b,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2  = 0x0000000c,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN  = 0x0000000d,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL  = 0x0000000e,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK  = 0x0000000f,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP  = 0x00000010,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING  = 0x00000011,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF  = 0x00000012,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC  = 0x00000013,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC  = 0x00000014,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL  = 0x00000015,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL  = 0x00000016,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1  = 0x00000017,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING  = 0x00000018,
} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT;

/*
 * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
 */

typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0  = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE  = 0x00000001,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA  = 0x00000002,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB  = 0x00000003,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA  = 0x00000004,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1  = 0x00000005,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC  = 0x00000006,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD  = 0x00000007,
} OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT;

/*
 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
 */

typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0  = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN  = 0x00000001,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN  = 0x00000002,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN  = 0x00000003,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN  = 0x00000004,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN  = 0x00000005,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN  = 0x00000006,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN  = 0x00000007,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN  = 0x00000008,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN  = 0x00000009,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN  = 0x0000000a,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1  = 0x0000000b,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2  = 0x0000000c,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN  = 0x0000000d,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL  = 0x0000000e,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK  = 0x0000000f,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP  = 0x00000010,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING  = 0x00000011,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF  = 0x00000012,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC  = 0x00000013,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC  = 0x00000014,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL  = 0x00000015,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL  = 0x00000016,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1  = 0x00000017,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING  = 0x00000018,
} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT;

/*
 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
 */

typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0  = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1  = 0x00000001,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2  = 0x00000002,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3  = 0x00000003,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4  = 0x00000004,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5  = 0x00000005,
} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT;

/*
 * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
 */

typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0  = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE  = 0x00000001,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA  = 0x00000002,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB  = 0x00000003,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA  = 0x00000004,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1  = 0x00000005,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC  = 0x00000006,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD  = 0x00000007,
} OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT;

/*
 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
 */

typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0  = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1  = 0x00000001,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2  = 0x00000002,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3  = 0x00000003,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4  = 0x00000004,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5  = 0x00000005,
} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT;

/*
 * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
 */

typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
} OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN;

/*
 * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
 */

typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE     = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE      = 0x00000001,
} OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR;

/*
 * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
 */

typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
} OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN;

/*
 * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
 */

typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE     = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE      = 0x00000001,
} OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR;

/*
 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
 */

typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE  = 0x00000000,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT  = 0x00000001,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT  = 0x00000002,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED  = 0x00000003,
} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE;

/*
 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
 */

typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE  = 0x00000000,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE  = 0x00000001,
} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK;

/*
 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
 */

typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE  = 0x00000000,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE  = 0x00000001,
} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL;

/*
 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
 */

typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE  = 0x00000001,
} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR;

/*
 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
 */

typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0  = 0x00000000,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1  = 0x00000001,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA  = 0x00000002,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB  = 0x00000003,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC  = 0x00000004,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD  = 0x00000005,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE  = 0x00000006,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF  = 0x00000007,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1  = 0x00000008,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2  = 0x00000009,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA  = 0x0000000a,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK  = 0x0000000b,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA  = 0x0000000c,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK  = 0x0000000d,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL  = 0x0000000e,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE  = 0x0000000f,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK  = 0x00000010,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC  = 0x00000011,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA  = 0x00000012,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB  = 0x00000013,
} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT;

/*
 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
 */

typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE  = 0x00000000,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE  = 0x00000001,
} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY;

/*
 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
 */

typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE  = 0x00000000,
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE  = 0x00000001,
} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY;

/*
 * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
 */

typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO  = 0x00000000,
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT  = 0x00000001,
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT  = 0x00000002,
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED  = 0x00000003,
} OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE;

/*
 * OTG_CONTROL_OTG_MASTER_EN enum
 */

typedef enum OTG_CONTROL_OTG_MASTER_EN {
OTG_CONTROL_OTG_MASTER_EN_FALSE          = 0x00000000,
OTG_CONTROL_OTG_MASTER_EN_TRUE           = 0x00000001,
} OTG_CONTROL_OTG_MASTER_EN;

/*
 * OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN enum
 */

typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN {
OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE  = 0x00000000,
OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE  = 0x00000001,
} OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN;

/*
 * OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE enum
 */

typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE {
OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE  = 0x00000000,
OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE  = 0x00000001,
} OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE;

/*
 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
 */

typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE  = 0x00000000,
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE  = 0x00000001,
} OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE;

/*
 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
 */

typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT  = 0x00000000,
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM  = 0x00000001,
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP  = 0x00000002,
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2  = 0x00000003,
} OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD;

/*
 * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY enum
 */

typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY {
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE  = 0x00000000,
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE  = 0x00000001,
} OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY;

/*
 * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT enum
 */

typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT {
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE  = 0x00000000,
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE  = 0x00000001,
} OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT;

/*
 * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
 */

typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE  = 0x00000000,
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE  = 0x00000001,
} OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN;

/*
 * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
 */

typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE  = 0x00000001,
} OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE;

/*
 * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
 */

typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE  = 0x00000001,
} OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;

/*
 * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
 */

typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE  = 0x00000000,
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA  = 0x00000001,
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB  = 0x00000002,
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED  = 0x00000003,
} OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE;

/*
 * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
 */

typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE  = 0x00000000,
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE  = 0x00000001,
} OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY;

/*
 * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
 */

typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE  = 0x00000000,
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE  = 0x00000001,
} OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY;

/*
 * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
 */

typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE   = 0x00000000,
OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE    = 0x00000001,
} OTG_STEREO_CONTROL_OTG_STEREO_EN;

/*
 * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
 */

typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000,
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE  = 0x00000001,
} OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR;

/*
 * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
 */

typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE  = 0x00000000,
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA  = 0x00000001,
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB  = 0x00000002,
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED  = 0x00000003,
} OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL;

/*
 * OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY enum
 */

typedef enum OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY {
OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE  = 0x00000001,
} OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY;

/*
 * OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY enum
 */

typedef enum OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY {
OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE  = 0x00000001,
} OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY;

/*
 * OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN enum
 */

typedef enum OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN {
OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE  = 0x00000000,
OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE  = 0x00000001,
} OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN;

/*
 * OTG_START_LINE_CONTROL_OTG_PREFETCH_EN enum
 */

typedef enum OTG_START_LINE_CONTROL_OTG_PREFETCH_EN {
OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE  = 0x00000000,
OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE  = 0x00000001,
} OTG_START_LINE_CONTROL_OTG_PREFETCH_EN;

/*
 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK;

/*
 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE;

/*
 * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK {
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK;

/*
 * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE {
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE;

/*
 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK;

/*
 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE;

/*
 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK;

/*
 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE;

/*
 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK;

/*
 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE;

/*
 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK;

/*
 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE;

/*
 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK;

/*
 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE;

/*
 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK;

/*
 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
 */

typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE  = 0x00000000,
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE  = 0x00000001,
} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE;

/*
 * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
 */

typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE    = 0x00000000,
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE     = 0x00000001,
} OTG_UPDATE_LOCK_OTG_UPDATE_LOCK;

/*
 * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
 */

typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE  = 0x00000000,
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE  = 0x00000001,
} OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY;

/*
 * OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN enum
 */

typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN {
OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE  = 0x00000000,
OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE  = 0x00000001,
} OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN;

/*
 * OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE enum
 */

typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE {
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0  = 0x00000000,
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1  = 0x00000001,
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2  = 0x00000002,
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3  = 0x00000003,
} OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE;

/*
 * OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE enum
 */

typedef enum OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE {
OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE  = 0x00000000,
OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE  = 0x00000001,
} OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE;

/*
 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
 */

typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;

/*
 * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
 */

typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME  = 0x00000000,
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME  = 0x00000001,
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME  = 0x00000002,
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME  = 0x00000003,
} OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME;

/*
 * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
 */

typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE  = 0x00000000,
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE  = 0x00000001,
} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;

/*
 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
 */

typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH  = 0x00000000,
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP  = 0x00000001,
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM  = 0x00000002,
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED  = 0x00000003,
} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;

/*
 * OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE enum
 */

typedef enum OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE {
OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE  = 0x00000000,
OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG  = 0x00000001,
OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL  = 0x00000002,
} OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE;

/*
 * OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR enum
 */

typedef enum OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR {
OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE  = 0x00000000,
OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE   = 0x00000001,
} OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR;

/*
 * OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR enum
 */

typedef enum OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR {
OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE  = 0x00000001,
} OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR;

/*
 * OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR enum
 */

typedef enum OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR {
OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE  = 0x00000001,
} OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR;

/*
 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
 */

typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE  = 0x00000000,
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;

/*
 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
 */

typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE;

/*
 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
 */

typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR;

/*
 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
 */

typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE  = 0x00000000,
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE;

/*
 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
 */

typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR;

/*
 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
 */

typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE;

/*
 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
 */

typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE  = 0x00000000,
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE;

/*
 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
 */

typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR;

/*
 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
 */

typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE;

/*
 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
 */

typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE  = 0x00000000,
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE  = 0x00000001,
} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE;

/*
 * OTG_CRC_CNTL_OTG_CRC_EN enum
 */

typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
OTG_CRC_CNTL_OTG_CRC_EN_FALSE            = 0x00000000,
OTG_CRC_CNTL_OTG_CRC_EN_TRUE             = 0x00000001,
} OTG_CRC_CNTL_OTG_CRC_EN;

/*
 * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
 */

typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE       = 0x00000000,
OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE        = 0x00000001,
} OTG_CRC_CNTL_OTG_CRC_CONT_EN;

/*
 * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
 */

typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT    = 0x00000000,
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT   = 0x00000001,
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES  = 0x00000002,
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS  = 0x00000003,
} OTG_CRC_CNTL_OTG_CRC_STEREO_MODE;

/*
 * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
 */

typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP  = 0x00000000,
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM  = 0x00000001,
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD  = 0x00000003,
} OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE;

/*
 * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
 */

typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE  = 0x00000001,
} OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS;

/*
 * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
 */

typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB     = 0x00000000,
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B    = 0x00000001,
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB    = 0x00000002,
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B   = 0x00000003,
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB     = 0x00000004,
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B    = 0x00000005,
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB    = 0x00000006,
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B   = 0x00000007,
} OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT;

/*
 * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
 */

typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB     = 0x00000000,
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B    = 0x00000001,
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB    = 0x00000002,
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B   = 0x00000003,
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB     = 0x00000004,
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B    = 0x00000005,
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB    = 0x00000006,
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B   = 0x00000007,
} OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT;

/*
 * OTG_CRC_CNTL2_OTG_CRC_DSC_MODE enum
 */

typedef enum OTG_CRC_CNTL2_OTG_CRC_DSC_MODE {
OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE     = 0x00000000,
OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE      = 0x00000001,
} OTG_CRC_CNTL2_OTG_CRC_DSC_MODE;

/*
 * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE enum
 */

typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE {
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE  = 0x00000000,
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE  = 0x00000001,
} OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE;

/*
 * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE enum
 */

typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE {
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE  = 0x00000000,
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1  = 0x00000001,
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2  = 0x00000002,
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3  = 0x00000003,
} OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE;

/*
 * OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT enum
 */

typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT {
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0      = 0x00000000,
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1      = 0x00000001,
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2      = 0x00000002,
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3      = 0x00000003,
} OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT;

/*
 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE {
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE  = 0x00000000,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT  = 0x00000001,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS  = 0x00000002,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED  = 0x00000003,
} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE;

/*
 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;

/*
 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;

/*
 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
 */

typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel  = 0x00000000,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel  = 0x00000001,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel  = 0x00000002,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel  = 0x00000003,
} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;

/*
 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE {
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE;

/*
 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE {
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE;

/*
 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY enum
 */

typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY {
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY;

/*
 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY enum
 */

typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY {
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY;

/*
 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE {
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE;

/*
 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE;

/*
 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR enum
 */

typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR {
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR;

/*
 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE {
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE;

/*
 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
 */

typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME  = 0x00000000,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME  = 0x00000001,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME  = 0x00000002,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME  = 0x00000003,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME  = 0x00000004,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME  = 0x00000005,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME  = 0x00000006,
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME  = 0x00000007,
} OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;

/*
 * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE {
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE;

/*
 * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR enum
 */

typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR {
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR;

/*
 * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE {
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE;

/*
 * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;

/*
 * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
 */

typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR {
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR;

/*
 * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
 */

typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE  = 0x00000000,
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE  = 0x00000001,
} OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;

/*
 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
 */

typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE  = 0x00000000,
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE  = 0x00000001,
} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE;

/*
 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
 */

typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE  = 0x00000001,
} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR;

/*
 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
 */

typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE  = 0x00000000,
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE  = 0x00000001,
} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE;

/*
 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
 */

typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE  = 0x00000000,
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE  = 0x00000001,
} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE;

/*
 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
 */

typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF  = 0x00000000,
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON  = 0x00000001,
} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE;

/*
 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
 */

typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE  = 0x00000000,
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE  = 0x00000001,
} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN;

/*
 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
 */

typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE  = 0x00000000,
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE  = 0x00000001,
} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB;

/*
 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
 */

typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH  = 0x00000000,
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE  = 0x00000001,
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE  = 0x00000002,
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED  = 0x00000003,
} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE;

/*
 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
 */

typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE  = 0x00000000,
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE  = 0x00000001,
} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR;

/*
 * OTG_V_SYNC_A_POL enum
 */

typedef enum OTG_V_SYNC_A_POL {
OTG_V_SYNC_A_POL_HIGH                    = 0x00000000,
OTG_V_SYNC_A_POL_LOW                     = 0x00000001,
} OTG_V_SYNC_A_POL;

/*
 * OTG_H_SYNC_A_POL enum
 */

typedef enum OTG_H_SYNC_A_POL {
OTG_H_SYNC_A_POL_HIGH                    = 0x00000000,
OTG_H_SYNC_A_POL_LOW                     = 0x00000001,
} OTG_H_SYNC_A_POL;

/*
 * OTG_HORZ_REPETITION_COUNT enum
 */

typedef enum OTG_HORZ_REPETITION_COUNT {
OTG_HORZ_REPETITION_COUNT_0              = 0x00000000,
OTG_HORZ_REPETITION_COUNT_1              = 0x00000001,
OTG_HORZ_REPETITION_COUNT_2              = 0x00000002,
OTG_HORZ_REPETITION_COUNT_3              = 0x00000003,
OTG_HORZ_REPETITION_COUNT_4              = 0x00000004,
OTG_HORZ_REPETITION_COUNT_5              = 0x00000005,
OTG_HORZ_REPETITION_COUNT_6              = 0x00000006,
OTG_HORZ_REPETITION_COUNT_7              = 0x00000007,
OTG_HORZ_REPETITION_COUNT_8              = 0x00000008,
OTG_HORZ_REPETITION_COUNT_9              = 0x00000009,
OTG_HORZ_REPETITION_COUNT_10             = 0x0000000a,
OTG_HORZ_REPETITION_COUNT_11             = 0x0000000b,
OTG_HORZ_REPETITION_COUNT_12             = 0x0000000c,
OTG_HORZ_REPETITION_COUNT_13             = 0x0000000d,
OTG_HORZ_REPETITION_COUNT_14             = 0x0000000e,
OTG_HORZ_REPETITION_COUNT_15             = 0x0000000f,
} OTG_HORZ_REPETITION_COUNT;

/*
 * MASTER_UPDATE_LOCK_SEL enum
 */

typedef enum MASTER_UPDATE_LOCK_SEL {
MASTER_UPDATE_LOCK_SEL_0                 = 0x00000000,
MASTER_UPDATE_LOCK_SEL_1                 = 0x00000001,
MASTER_UPDATE_LOCK_SEL_2                 = 0x00000002,
MASTER_UPDATE_LOCK_SEL_3                 = 0x00000003,
MASTER_UPDATE_LOCK_SEL_4                 = 0x00000004,
MASTER_UPDATE_LOCK_SEL_5                 = 0x00000005,
} MASTER_UPDATE_LOCK_SEL;

/*
 * DRR_UPDATE_LOCK_SEL enum
 */

typedef enum DRR_UPDATE_LOCK_SEL {
DRR_UPDATE_LOCK_SEL_0                    = 0x00000000,
DRR_UPDATE_LOCK_SEL_1                    = 0x00000001,
DRR_UPDATE_LOCK_SEL_2                    = 0x00000002,
DRR_UPDATE_LOCK_SEL_3                    = 0x00000003,
DRR_UPDATE_LOCK_SEL_4                    = 0x00000004,
DRR_UPDATE_LOCK_SEL_5                    = 0x00000005,
} DRR_UPDATE_LOCK_SEL;

/*
 * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
 */

typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0  = 0x00000000,
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1  = 0x00000001,
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2  = 0x00000002,
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3  = 0x00000003,
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4  = 0x00000004,
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5  = 0x00000005,
} OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL;

/*
 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
 */

typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
MASTER_UPDATE_LOCK_DB_FIELD_BOTH         = 0x00000000,
MASTER_UPDATE_LOCK_DB_FIELD_TOP          = 0x00000001,
MASTER_UPDATE_LOCK_DB_FIELD_RESERVED     = 0x00000002,
} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD;

/*
 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
 */

typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH    = 0x00000000,
MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT    = 0x00000001,
MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT   = 0x00000002,
MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED  = 0x00000003,
} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL;

/*
 * OTG_H_TIMING_DIV_BY2 enum
 */

typedef enum OTG_H_TIMING_DIV_BY2 {
OTG_H_TIMING_DIV_BY2_FALSE               = 0x00000000,
OTG_H_TIMING_DIV_BY2_TRUE                = 0x00000001,
} OTG_H_TIMING_DIV_BY2;

/*
 * OTG_H_TIMING_DIV_BY2_UPDATE_MODE enum
 */

typedef enum OTG_H_TIMING_DIV_BY2_UPDATE_MODE {
OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0       = 0x00000000,
OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1       = 0x00000001,
} OTG_H_TIMING_DIV_BY2_UPDATE_MODE;

/*
 * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
 */

typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0      = 0x00000000,
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1      = 0x00000001,
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2      = 0x00000002,
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3      = 0x00000003,
} OTG_TRIGA_RISING_EDGE_DETECT_CNTL;

/*
 * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
 */

typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0     = 0x00000000,
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1     = 0x00000001,
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2     = 0x00000002,
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3     = 0x00000003,
} OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;

/*
 * OTG_TRIGA_FREQUENCY_SELECT enum
 */

typedef enum OTG_TRIGA_FREQUENCY_SELECT {
OTG_TRIGA_FREQUENCY_SELECT_0             = 0x00000000,
OTG_TRIGA_FREQUENCY_SELECT_1             = 0x00000001,
OTG_TRIGA_FREQUENCY_SELECT_2             = 0x00000002,
OTG_TRIGA_FREQUENCY_SELECT_3             = 0x00000003,
} OTG_TRIGA_FREQUENCY_SELECT;

/*
 * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
 */

typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0      = 0x00000000,
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1      = 0x00000001,
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2      = 0x00000002,
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3      = 0x00000003,
} OTG_TRIGB_RISING_EDGE_DETECT_CNTL;

/*
 * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
 */

typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0     = 0x00000000,
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1     = 0x00000001,
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2     = 0x00000002,
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3     = 0x00000003,
} OTG_TRIGB_FALLING_EDGE_DETECT_CNTL;

/*
 * OTG_TRIGB_FREQUENCY_SELECT enum
 */

typedef enum OTG_TRIGB_FREQUENCY_SELECT {
OTG_TRIGB_FREQUENCY_SELECT_0             = 0x00000000,
OTG_TRIGB_FREQUENCY_SELECT_1             = 0x00000001,
OTG_TRIGB_FREQUENCY_SELECT_2             = 0x00000002,
OTG_TRIGB_FREQUENCY_SELECT_3             = 0x00000003,
} OTG_TRIGB_FREQUENCY_SELECT;

/*
 * OTG_PIPE_ABORT enum
 */

typedef enum OTG_PIPE_ABORT {
OTG_PIPE_ABORT_0                         = 0x00000000,
OTG_PIPE_ABORT_1                         = 0x00000001,
} OTG_PIPE_ABORT;

/*
 * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
 */

typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE      = 0x00000000,
OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE       = 0x00000001,
} OTG_MASTER_UPDATE_LOCK_GSL_EN;

/*
 * OTG_PTI_CONTROL_OTG_PIT_EN enum
 */

typedef enum OTG_PTI_CONTROL_OTG_PIT_EN {
OTG_PTI_CONTROL_OTG_PIT_EN_FALSE         = 0x00000000,
OTG_PTI_CONTROL_OTG_PIT_EN_TRUE          = 0x00000001,
} OTG_PTI_CONTROL_OTG_PIT_EN;

/*
 * OTG_GSL_MASTER_MODE enum
 */

typedef enum OTG_GSL_MASTER_MODE {
OTG_GSL_MASTER_MODE_0                    = 0x00000000,
OTG_GSL_MASTER_MODE_1                    = 0x00000001,
OTG_GSL_MASTER_MODE_2                    = 0x00000002,
OTG_GSL_MASTER_MODE_3                    = 0x00000003,
} OTG_GSL_MASTER_MODE;

/*******************************************************
 * DMCUB Enums
 *******************************************************/

/*
 * DC_DMCUB_TIMER_WINDOW enum
 */

typedef enum DC_DMCUB_TIMER_WINDOW {
BITS_31_0                                = 0x00000000,
BITS_32_1                                = 0x00000001,
BITS_33_2                                = 0x00000002,
BITS_34_3                                = 0x00000003,
BITS_35_4                                = 0x00000004,
BITS_36_5                                = 0x00000005,
BITS_37_6                                = 0x00000006,
BITS_38_7                                = 0x00000007,
} DC_DMCUB_TIMER_WINDOW;

/*
 * DC_DMCUB_INT_TYPE enum
 */

typedef enum DC_DMCUB_INT_TYPE {
INT_LEVEL                                = 0x00000000,
INT_PULSE                                = 0x00000001,
} DC_DMCUB_INT_TYPE;

/*******************************************************
 * RBBMIF Enums
 *******************************************************/

/*
 * INVALID_REG_ACCESS_TYPE enum
 */

typedef enum INVALID_REG_ACCESS_TYPE {
REG_UNALLOCATED_ADDR_WRITE               = 0x00000000,
REG_UNALLOCATED_ADDR_READ                = 0x00000001,
REG_VIRTUAL_WRITE                        = 0x00000002,
REG_VIRTUAL_READ                         = 0x00000003,
} INVALID_REG_ACCESS_TYPE;

/*******************************************************
 * IHC Enums
 *******************************************************/

/*
 * DMU_DC_GPU_TIMER_START_POSITION enum
 */

typedef enum DMU_DC_GPU_TIMER_START_POSITION {
DMU_GPU_TIMER_START_0_END_27             = 0x00000000,
DMU_GPU_TIMER_START_1_END_28             = 0x00000001,
DMU_GPU_TIMER_START_2_END_29             = 0x00000002,
DMU_GPU_TIMER_START_3_END_30             = 0x00000003,
DMU_GPU_TIMER_START_4_END_31             = 0x00000004,
DMU_GPU_TIMER_START_6_END_33             = 0x00000005,
DMU_GPU_TIMER_START_8_END_35             = 0x00000006,
DMU_GPU_TIMER_START_10_END_37            = 0x00000007,
} DMU_DC_GPU_TIMER_START_POSITION;

/*
 * DMU_DC_GPU_TIMER_READ_SELECT enum
 */

typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0  = 0x00000000,
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1  = 0x00000001,
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2  = 0x00000002,
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3  = 0x00000003,
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4  = 0x00000004,
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5  = 0x00000005,
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6  = 0x00000006,
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7  = 0x00000007,
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8  = 0x00000008,
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9  = 0x00000009,
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10  = 0x0000000a,
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11  = 0x0000000b,
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12  = 0x0000000c,
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13  = 0x0000000d,
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14  = 0x0000000e,
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15  = 0x0000000f,
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16  = 0x00000010,
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17  = 0x00000011,
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18  = 0x00000012,
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19  = 0x00000013,
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20  = 0x00000014,
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21  = 0x00000015,
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22  = 0x00000016,
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23  = 0x00000017,
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24  = 0x00000018,
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25  = 0x00000019,
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26  = 0x0000001a,
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27  = 0x0000001b,
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28  = 0x0000001c,
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29  = 0x0000001d,
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30  = 0x0000001e,
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31  = 0x0000001f,
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32  = 0x00000020,
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33  = 0x00000021,
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34  = 0x00000022,
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35  = 0x00000023,
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36  = 0x00000024,
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37  = 0x00000025,
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38  = 0x00000026,
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39  = 0x00000027,
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40  = 0x00000028,
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41  = 0x00000029,
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42  = 0x0000002a,
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43  = 0x0000002b,
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44  = 0x0000002c,
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45  = 0x0000002d,
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46  = 0x0000002e,
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47  = 0x0000002f,
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48  = 0x00000030,
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49  = 0x00000031,
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50  = 0x00000032,
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51  = 0x00000033,
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52  = 0x00000034,
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53  = 0x00000035,
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54  = 0x00000036,
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55  = 0x00000037,
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56  = 0x00000038,
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57  = 0x00000039,
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58  = 0x0000003a,
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59  = 0x0000003b,
RESERVED_60                              = 0x0000003c,
RESERVED_61                              = 0x0000003d,
RESERVED_62                              = 0x0000003e,
RESERVED_63                              = 0x0000003f,
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64  = 0x00000040,
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65  = 0x00000041,
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66  = 0x00000042,
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67  = 0x00000043,
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68  = 0x00000044,
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69  = 0x00000045,
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70  = 0x00000046,
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71  = 0x00000047,
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72  = 0x00000048,
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73  = 0x00000049,
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74  = 0x0000004a,
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75  = 0x0000004b,
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76  = 0x0000004c,
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77  = 0x0000004d,
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78  = 0x0000004e,
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79  = 0x0000004f,
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80  = 0x00000050,
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81  = 0x00000051,
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82  = 0x00000052,
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83  = 0x00000053,
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84  = 0x00000054,
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85  = 0x00000055,
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86  = 0x00000056,
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87  = 0x00000057,
RESERVED_88                              = 0x00000058,
RESERVED_89                              = 0x00000059,
RESERVED_90                              = 0x0000005a,
RESERVED_91                              = 0x0000005b,
} DMU_DC_GPU_TIMER_READ_SELECT;

/*
 * IHC_INTERRUPT_LINE_STATUS enum
 */

typedef enum IHC_INTERRUPT_LINE_STATUS {
INTERRUPT_LINE_NOT_ASSERTED              = 0x00000000,
INTERRUPT_LINE_ASSERTED                  = 0x00000001,
} IHC_INTERRUPT_LINE_STATUS;

/*******************************************************
 * DMU_MISC Enums
 *******************************************************/

/*
 * DMU_CLOCK_GATING_DISABLE enum
 */

typedef enum DMU_CLOCK_GATING_DISABLE {
DMU_ENABLE_CLOCK_GATING                  = 0x00000000,
DMU_DISABLE_CLOCK_GATING                 = 0x00000001,
} DMU_CLOCK_GATING_DISABLE;

/*
 * DMU_CLOCK_ON enum
 */

typedef enum DMU_CLOCK_ON {
DMU_CLOCK_STATUS_ON                      = 0x00000000,
DMU_CLOCK_STATUS_OFF                     = 0x00000001,
} DMU_CLOCK_ON;

/*
 * DC_SMU_INTERRUPT_ENABLE enum
 */

typedef enum DC_SMU_INTERRUPT_ENABLE {
DISABLE_THE_INTERRUPT                    = 0x00000000,
ENABLE_THE_INTERRUPT                     = 0x00000001,
} DC_SMU_INTERRUPT_ENABLE;

/*
 * STATIC_SCREEN_SMU_INTR enum
 */

typedef enum STATIC_SCREEN_SMU_INTR {
STATIC_SCREEN_SMU_INTR_NOOP              = 0x00000000,
SET_STATIC_SCREEN_SMU_INTR               = 0x00000001,
} STATIC_SCREEN_SMU_INTR;

/*******************************************************
 * DCCG Enums
 *******************************************************/

/*
 * ENABLE enum
 */

typedef enum ENABLE {
DISABLE_THE_FEATURE                      = 0x00000000,
ENABLE_THE_FEATURE                       = 0x00000001,
} ENABLE;

/*
 * DS_HW_CAL_ENABLE enum
 */

typedef enum DS_HW_CAL_ENABLE {
DS_HW_CAL_DIS                            = 0x00000000,
DS_HW_CAL_EN                             = 0x00000001,
} DS_HW_CAL_ENABLE;

/*
 * ENABLE_CLOCK enum
 */

typedef enum ENABLE_CLOCK {
DISABLE_THE_CLOCK                        = 0x00000000,
ENABLE_THE_CLOCK                         = 0x00000001,
} ENABLE_CLOCK;

/*
 * CLEAR_SMU_INTR enum
 */

typedef enum CLEAR_SMU_INTR {
SMU_INTR_STATUS_NOOP                     = 0x00000000,
SMU_INTR_STATUS_CLEAR                    = 0x00000001,
} CLEAR_SMU_INTR;

/*
 * JITTER_REMOVE_DISABLE enum
 */

typedef enum JITTER_REMOVE_DISABLE {
ENABLE_JITTER_REMOVAL                    = 0x00000000,
DISABLE_JITTER_REMOVAL                   = 0x00000001,
} JITTER_REMOVE_DISABLE;

/*
 * DS_REF_SRC enum
 */

typedef enum DS_REF_SRC {
DS_REF_IS_XTALIN                         = 0x00000000,
DS_REF_IS_EXT_GENLOCK                    = 0x00000001,
DS_REF_IS_PCIE                           = 0x00000002,
} DS_REF_SRC;

/*
 * DISABLE_CLOCK_GATING enum
 */

typedef enum DISABLE_CLOCK_GATING {
CLOCK_GATING_ENABLED                     = 0x00000000,
CLOCK_GATING_DISABLED                    = 0x00000001,
} DISABLE_CLOCK_GATING;

/*
 * DISABLE_CLOCK_GATING_IN_DCO enum
 */

typedef enum DISABLE_CLOCK_GATING_IN_DCO {
CLOCK_GATING_ENABLED_IN_DCO              = 0x00000000,
CLOCK_GATING_DISABLED_IN_DCO             = 0x00000001,
} DISABLE_CLOCK_GATING_IN_DCO;

/*
 * DCCG_DEEP_COLOR_CNTL enum
 */

typedef enum DCCG_DEEP_COLOR_CNTL {
DCCG_DEEP_COLOR_DTO_DISABLE              = 0x00000000,
DCCG_DEEP_COLOR_DTO_5_4_RATIO            = 0x00000001,
DCCG_DEEP_COLOR_DTO_3_2_RATIO            = 0x00000002,
DCCG_DEEP_COLOR_DTO_2_1_RATIO            = 0x00000003,
} DCCG_DEEP_COLOR_CNTL;

/*
 * REFCLK_CLOCK_EN enum
 */

typedef enum REFCLK_CLOCK_EN {
REFCLK_CLOCK_EN_XTALIN_CLK               = 0x00000000,
REFCLK_CLOCK_EN_ALLOW_SRC_SEL            = 0x00000001,
} REFCLK_CLOCK_EN;

/*
 * REFCLK_SRC_SEL enum
 */

typedef enum REFCLK_SRC_SEL {
REFCLK_SRC_SEL_PCIE_REFCLK               = 0x00000000,
REFCLK_SRC_SEL_CPL_REFCLK                = 0x00000001,
} REFCLK_SRC_SEL;

/*
 * DPREFCLK_SRC_SEL enum
 */

typedef enum DPREFCLK_SRC_SEL {
DPREFCLK_SRC_SEL_CK                      = 0x00000000,
DPREFCLK_SRC_SEL_P0PLL                   = 0x00000001,
DPREFCLK_SRC_SEL_P1PLL                   = 0x00000002,
DPREFCLK_SRC_SEL_P2PLL                   = 0x00000003,
} DPREFCLK_SRC_SEL;

/*
 * XTAL_REF_SEL enum
 */

typedef enum XTAL_REF_SEL {
XTAL_REF_SEL_1X                          = 0x00000000,
XTAL_REF_SEL_2X                          = 0x00000001,
} XTAL_REF_SEL;

/*
 * XTAL_REF_CLOCK_SOURCE_SEL enum
 */

typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
XTAL_REF_CLOCK_SOURCE_SEL_XTALIN         = 0x00000000,
XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK     = 0x00000001,
} XTAL_REF_CLOCK_SOURCE_SEL;

/*
 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
 */

typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK  = 0x00000001,
} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;

/*
 * ALLOW_SR_ON_TRANS_REQ enum
 */

typedef enum ALLOW_SR_ON_TRANS_REQ {
ALLOW_SR_ON_TRANS_REQ_ENABLE             = 0x00000000,
ALLOW_SR_ON_TRANS_REQ_DISABLE            = 0x00000001,
} ALLOW_SR_ON_TRANS_REQ;

/*
 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
 */

typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK  = 0x00000001,
} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;

/*
 * PIPE_PIXEL_RATE_SOURCE enum
 */

typedef enum PIPE_PIXEL_RATE_SOURCE {
PIPE_PIXEL_RATE_SOURCE_P0PLL             = 0x00000000,
PIPE_PIXEL_RATE_SOURCE_P1PLL             = 0x00000001,
PIPE_PIXEL_RATE_SOURCE_P2PLL             = 0x00000002,
} PIPE_PIXEL_RATE_SOURCE;

/*
 * TEST_CLK_DIV_SEL enum
 */

typedef enum TEST_CLK_DIV_SEL {
NO_DIV                                   = 0x00000000,
DIV_2                                    = 0x00000001,
DIV_4                                    = 0x00000002,
DIV_8                                    = 0x00000003,
} TEST_CLK_DIV_SEL;

/*
 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
 */

typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA    = 0x00000000,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB    = 0x00000001,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC    = 0x00000002,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD    = 0x00000003,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE    = 0x00000004,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF    = 0x00000005,
PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED   = 0x00000006,
} PIPE_PHYPLL_PIXEL_RATE_SOURCE;

/*
 * PIPE_PIXEL_RATE_PLL_SOURCE enum
 */

typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL        = 0x00000000,
PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL       = 0x00000001,
} PIPE_PIXEL_RATE_PLL_SOURCE;

/*
 * DP_DTO_DS_DISABLE enum
 */

typedef enum DP_DTO_DS_DISABLE {
DP_DTO_DESPREAD_DISABLE                  = 0x00000000,
DP_DTO_DESPREAD_ENABLE                   = 0x00000001,
} DP_DTO_DS_DISABLE;

/*
 * OTG_ADD_PIXEL enum
 */

typedef enum OTG_ADD_PIXEL {
OTG_ADD_PIXEL_NOOP                       = 0x00000000,
OTG_ADD_PIXEL_FORCE                      = 0x00000001,
} OTG_ADD_PIXEL;

/*
 * OTG_DROP_PIXEL enum
 */

typedef enum OTG_DROP_PIXEL {
OTG_DROP_PIXEL_NOOP                      = 0x00000000,
OTG_DROP_PIXEL_FORCE                     = 0x00000001,
} OTG_DROP_PIXEL;

/*
 * SYMCLK_FE_FORCE_EN enum
 */

typedef enum SYMCLK_FE_FORCE_EN {
SYMCLK_FE_FORCE_EN_DISABLE               = 0x00000000,
SYMCLK_FE_FORCE_EN_ENABLE                = 0x00000001,
} SYMCLK_FE_FORCE_EN;

/*
 * SYMCLK_FE_FORCE_SRC enum
 */

typedef enum SYMCLK_FE_FORCE_SRC {
SYMCLK_FE_FORCE_SRC_UNIPHYA              = 0x00000000,
SYMCLK_FE_FORCE_SRC_UNIPHYB              = 0x00000001,
SYMCLK_FE_FORCE_SRC_UNIPHYC              = 0x00000002,
SYMCLK_FE_FORCE_SRC_UNIPHYD              = 0x00000003,
SYMCLK_FE_FORCE_SRC_UNIPHYE              = 0x00000004,
SYMCLK_FE_FORCE_SRC_UNIPHYF              = 0x00000005,
SYMCLK_FE_FORCE_SRC_RESERVED             = 0x00000006,
} SYMCLK_FE_FORCE_SRC;

/*
 * DVOACLK_COARSE_SKEW_CNTL enum
 */

typedef enum DVOACLK_COARSE_SKEW_CNTL {
DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT   = 0x00000000,
DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP    = 0x00000001,
DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS   = 0x00000002,
DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS   = 0x00000003,
DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS   = 0x00000004,
DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS   = 0x00000005,
DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS   = 0x00000006,
DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS   = 0x00000007,
DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS   = 0x00000008,
DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS   = 0x00000009,
DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS  = 0x0000000a,
DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS  = 0x0000000b,
DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS  = 0x0000000c,
DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS  = 0x0000000d,
DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS  = 0x0000000e,
DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS  = 0x0000000f,
DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP    = 0x00000010,
DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS   = 0x00000011,
DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS   = 0x00000012,
DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS   = 0x00000013,
DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS   = 0x00000014,
DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS   = 0x00000015,
DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS   = 0x00000016,
DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS   = 0x00000017,
DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS   = 0x00000018,
DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS  = 0x00000019,
DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS  = 0x0000001a,
DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS  = 0x0000001b,
DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS  = 0x0000001c,
DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS  = 0x0000001d,
DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS  = 0x0000001e,
} DVOACLK_COARSE_SKEW_CNTL;

/*
 * DVOACLK_FINE_SKEW_CNTL enum
 */

typedef enum DVOACLK_FINE_SKEW_CNTL {
DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT     = 0x00000000,
DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP      = 0x00000001,
DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS     = 0x00000002,
DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS     = 0x00000003,
DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP      = 0x00000004,
DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS     = 0x00000005,
DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS     = 0x00000006,
DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS     = 0x00000007,
} DVOACLK_FINE_SKEW_CNTL;

/*
 * DVOACLKD_IN_PHASE enum
 */

typedef enum DVOACLKD_IN_PHASE {
DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
DVOACLKD_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
} DVOACLKD_IN_PHASE;

/*
 * DVOACLKC_IN_PHASE enum
 */

typedef enum DVOACLKC_IN_PHASE {
DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
DVOACLKC_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
} DVOACLKC_IN_PHASE;

/*
 * DVOACLKC_MVP_IN_PHASE enum
 */

typedef enum DVOACLKC_MVP_IN_PHASE {
DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO      = 0x00000001,
} DVOACLKC_MVP_IN_PHASE;

/*
 * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
 */

typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE  = 0x00000000,
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE  = 0x00000001,
} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;

/*
 * DCCG_AUDIO_DTO0_SOURCE_SEL enum
 */

typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0          = 0x00000000,
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1          = 0x00000001,
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2          = 0x00000002,
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3          = 0x00000003,
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4          = 0x00000004,
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5          = 0x00000005,
DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED      = 0x00000006,
} DCCG_AUDIO_DTO0_SOURCE_SEL;

/*
 * DCCG_AUDIO_DTO_SEL enum
 */

typedef enum DCCG_AUDIO_DTO_SEL {
DCCG_AUDIO_DTO_SEL_AUDIO_DTO0            = 0x00000000,
DCCG_AUDIO_DTO_SEL_AUDIO_DTO1            = 0x00000001,
DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO          = 0x00000002,
} DCCG_AUDIO_DTO_SEL;

/*
 * DCCG_AUDIO_DTO2_SOURCE_SEL enum
 */

typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0        = 0x00000000,
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1        = 0x00000001,
} DCCG_AUDIO_DTO2_SOURCE_SEL;

/*
 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
 */

typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
DCCG_AUDIO_DTO_USE_128FBR_FOR_DP         = 0x00000000,
DCCG_AUDIO_DTO_USE_512FBR_FOR_DP         = 0x00000001,
} DCCG_AUDIO_DTO_USE_512FBR_DTO;

/*
 * DISPCLK_FREQ_RAMP_DONE enum
 */

typedef enum DISPCLK_FREQ_RAMP_DONE {
DISPCLK_FREQ_RAMP_IN_PROGRESS            = 0x00000000,
DISPCLK_FREQ_RAMP_COMPLETED              = 0x00000001,
} DISPCLK_FREQ_RAMP_DONE;

/*
 * DCCG_FIFO_ERRDET_RESET enum
 */

typedef enum DCCG_FIFO_ERRDET_RESET {
DCCG_FIFO_ERRDET_RESET_NOOP              = 0x00000000,
DCCG_FIFO_ERRDET_RESET_FORCE             = 0x00000001,
} DCCG_FIFO_ERRDET_RESET;

/*
 * DCCG_FIFO_ERRDET_STATE enum
 */

typedef enum DCCG_FIFO_ERRDET_STATE {
DCCG_FIFO_ERRDET_STATE_CALIBRATION       = 0x00000000,
DCCG_FIFO_ERRDET_STATE_DETECTION         = 0x00000001,
} DCCG_FIFO_ERRDET_STATE;

/*
 * DCCG_FIFO_ERRDET_OVR_EN enum
 */

typedef enum DCCG_FIFO_ERRDET_OVR_EN {
DCCG_FIFO_ERRDET_OVR_DISABLE             = 0x00000000,
DCCG_FIFO_ERRDET_OVR_ENABLE              = 0x00000001,
} DCCG_FIFO_ERRDET_OVR_EN;

/*
 * DISPCLK_CHG_FWD_CORR_DISABLE enum
 */

typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING  = 0x00000000,
DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING  = 0x00000001,
} DISPCLK_CHG_FWD_CORR_DISABLE;

/*
 * DC_MEM_GLOBAL_PWR_REQ_DIS enum
 */

typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
DC_MEM_GLOBAL_PWR_REQ_ENABLE             = 0x00000000,
DC_MEM_GLOBAL_PWR_REQ_DISABLE            = 0x00000001,
} DC_MEM_GLOBAL_PWR_REQ_DIS;

/*
 * DCCG_PERF_RUN enum
 */

typedef enum DCCG_PERF_RUN {
DCCG_PERF_RUN_NOOP                       = 0x00000000,
DCCG_PERF_RUN_START                      = 0x00000001,
} DCCG_PERF_RUN;

/*
 * DCCG_PERF_MODE_VSYNC enum
 */

typedef enum DCCG_PERF_MODE_VSYNC {
DCCG_PERF_MODE_VSYNC_NOOP                = 0x00000000,
DCCG_PERF_MODE_VSYNC_START               = 0x00000001,
} DCCG_PERF_MODE_VSYNC;

/*
 * DCCG_PERF_MODE_HSYNC enum
 */

typedef enum DCCG_PERF_MODE_HSYNC {
DCCG_PERF_MODE_HSYNC_NOOP                = 0x00000000,
DCCG_PERF_MODE_HSYNC_START               = 0x00000001,
} DCCG_PERF_MODE_HSYNC;

/*
 * DCCG_PERF_OTG_SELECT enum
 */

typedef enum DCCG_PERF_OTG_SELECT {
DCCG_PERF_SEL_OTG0                       = 0x00000000,
DCCG_PERF_SEL_OTG1                       = 0x00000001,
DCCG_PERF_SEL_OTG2                       = 0x00000002,
DCCG_PERF_SEL_OTG3                       = 0x00000003,
DCCG_PERF_SEL_OTG4                       = 0x00000004,
DCCG_PERF_SEL_OTG5                       = 0x00000005,
DCCG_PERF_SEL_RESERVED                   = 0x00000006,
} DCCG_PERF_OTG_SELECT;

/*
 * CLOCK_BRANCH_SOFT_RESET enum
 */

typedef enum CLOCK_BRANCH_SOFT_RESET {
CLOCK_BRANCH_SOFT_RESET_NOOP             = 0x00000000,
CLOCK_BRANCH_SOFT_RESET_FORCE            = 0x00000001,
} CLOCK_BRANCH_SOFT_RESET;

/*
 * PLL_CFG_IF_SOFT_RESET enum
 */

typedef enum PLL_CFG_IF_SOFT_RESET {
PLL_CFG_IF_SOFT_RESET_NOOP               = 0x00000000,
PLL_CFG_IF_SOFT_RESET_FORCE              = 0x00000001,
} PLL_CFG_IF_SOFT_RESET;

/*
 * DVO_ENABLE_RST enum
 */

typedef enum DVO_ENABLE_RST {
DVO_ENABLE_RST_DISABLE                   = 0x00000000,
DVO_ENABLE_RST_ENABLE                    = 0x00000001,
} DVO_ENABLE_RST;

/*
 * DS_JITTER_COUNT_SRC_SEL enum
 */

typedef enum DS_JITTER_COUNT_SRC_SEL {
DS_JITTER_COUNT_SRC_SEL0                 = 0x00000000,
DS_JITTER_COUNT_SRC_SEL1                 = 0x00000001,
} DS_JITTER_COUNT_SRC_SEL;

/*
 * DIO_FIFO_ERROR enum
 */

typedef enum DIO_FIFO_ERROR {
DIO_FIFO_ERROR_00                        = 0x00000000,
DIO_FIFO_ERROR_01                        = 0x00000001,
DIO_FIFO_ERROR_10                        = 0x00000002,
DIO_FIFO_ERROR_11                        = 0x00000003,
} DIO_FIFO_ERROR;

/*
 * VSYNC_CNT_REFCLK_SEL enum
 */

typedef enum VSYNC_CNT_REFCLK_SEL {
VSYNC_CNT_REFCLK_SEL_0                   = 0x00000000,
VSYNC_CNT_REFCLK_SEL_1                   = 0x00000001,
} VSYNC_CNT_REFCLK_SEL;

/*
 * VSYNC_CNT_RESET_SEL enum
 */

typedef enum VSYNC_CNT_RESET_SEL {
VSYNC_CNT_RESET_SEL_0                    = 0x00000000,
VSYNC_CNT_RESET_SEL_1                    = 0x00000001,
} VSYNC_CNT_RESET_SEL;

/*
 * VSYNC_CNT_LATCH_MASK enum
 */

typedef enum VSYNC_CNT_LATCH_MASK {
VSYNC_CNT_LATCH_MASK_0                   = 0x00000000,
VSYNC_CNT_LATCH_MASK_1                   = 0x00000001,
} VSYNC_CNT_LATCH_MASK;

/*******************************************************
 * HPD Enums
 *******************************************************/

/*
 * HPD_INT_CONTROL_ACK enum
 */

typedef enum HPD_INT_CONTROL_ACK {
HPD_INT_CONTROL_ACK_0                    = 0x00000000,
HPD_INT_CONTROL_ACK_1                    = 0x00000001,
} HPD_INT_CONTROL_ACK;

/*
 * HPD_INT_CONTROL_POLARITY enum
 */

typedef enum HPD_INT_CONTROL_POLARITY {
HPD_INT_CONTROL_GEN_INT_ON_DISCON        = 0x00000000,
HPD_INT_CONTROL_GEN_INT_ON_CON           = 0x00000001,
} HPD_INT_CONTROL_POLARITY;

/*
 * HPD_INT_CONTROL_RX_INT_ACK enum
 */

typedef enum HPD_INT_CONTROL_RX_INT_ACK {
HPD_INT_CONTROL_RX_INT_ACK_0             = 0x00000000,
HPD_INT_CONTROL_RX_INT_ACK_1             = 0x00000001,
} HPD_INT_CONTROL_RX_INT_ACK;

/*******************************************************
 * DP Enums
 *******************************************************/

/*
 * DP_MSO_NUM_OF_SST_LINKS enum
 */

typedef enum DP_MSO_NUM_OF_SST_LINKS {
DP_MSO_ONE_SSTLINK                       = 0x00000000,
DP_MSO_TWO_SSTLINK                       = 0x00000001,
DP_MSO_FOUR_SSTLINK                      = 0x00000002,
} DP_MSO_NUM_OF_SST_LINKS;

/*
 * DP_SYNC_POLARITY enum
 */

typedef enum DP_SYNC_POLARITY {
DP_SYNC_POLARITY_ACTIVE_HIGH             = 0x00000000,
DP_SYNC_POLARITY_ACTIVE_LOW              = 0x00000001,
} DP_SYNC_POLARITY;

/*
 * DP_COMBINE_PIXEL_NUM enum
 */

typedef enum DP_COMBINE_PIXEL_NUM {
DP_COMBINE_ONE_PIXEL                     = 0x00000000,
DP_COMBINE_TWO_PIXEL                     = 0x00000001,
DP_COMBINE_FOUR_PIXEL                    = 0x00000002,
} DP_COMBINE_PIXEL_NUM;

/*
 * DP_LINK_TRAINING_COMPLETE enum
 */

typedef enum DP_LINK_TRAINING_COMPLETE {
DP_LINK_TRAINING_NOT_COMPLETE            = 0x00000000,
DP_LINK_TRAINING_ALREADY_COMPLETE        = 0x00000001,
} DP_LINK_TRAINING_COMPLETE;

/*
 * DP_EMBEDDED_PANEL_MODE enum
 */

typedef enum DP_EMBEDDED_PANEL_MODE {
DP_EXTERNAL_PANEL                        = 0x00000000,
DP_EMBEDDED_PANEL                        = 0x00000001,
} DP_EMBEDDED_PANEL_MODE;

/*
 * DP_PIXEL_ENCODING enum
 */

typedef enum DP_PIXEL_ENCODING {
DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
DP_PIXEL_ENCODING_RESERVED               = 0x00000006,
} DP_PIXEL_ENCODING;

/*
 * DP_COMPONENT_DEPTH enum
 */

typedef enum DP_COMPONENT_DEPTH {
DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
DP_COMPONENT_DEPTH_16BPC_RESERVED        = 0x00000004,
DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
} DP_COMPONENT_DEPTH;

/*
 * DP_UDI_LANES enum
 */

typedef enum DP_UDI_LANES {
DP_UDI_1_LANE                            = 0x00000000,
DP_UDI_2_LANES                           = 0x00000001,
DP_UDI_LANES_RESERVED                    = 0x00000002,
DP_UDI_4_LANES                           = 0x00000003,
} DP_UDI_LANES;

/*
 * DP_VID_STREAM_DIS_DEFER enum
 */

typedef enum DP_VID_STREAM_DIS_DEFER {
DP_VID_STREAM_DIS_NO_DEFER               = 0x00000000,
DP_VID_STREAM_DIS_DEFER_TO_HBLANK        = 0x00000001,
DP_VID_STREAM_DIS_DEFER_TO_VBLANK        = 0x00000002,
} DP_VID_STREAM_DIS_DEFER;

/*
 * DP_STEER_OVERFLOW_ACK enum
 */

typedef enum DP_STEER_OVERFLOW_ACK {
DP_STEER_OVERFLOW_ACK_NO_EFFECT          = 0x00000000,
DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT      = 0x00000001,
} DP_STEER_OVERFLOW_ACK;

/*
 * DP_STEER_OVERFLOW_MASK enum
 */

typedef enum DP_STEER_OVERFLOW_MASK {
DP_STEER_OVERFLOW_MASKED                 = 0x00000000,
DP_STEER_OVERFLOW_UNMASK                 = 0x00000001,
} DP_STEER_OVERFLOW_MASK;

/*
 * DP_TU_OVERFLOW_ACK enum
 */

typedef enum DP_TU_OVERFLOW_ACK {
DP_TU_OVERFLOW_ACK_NO_EFFECT             = 0x00000000,
DP_TU_OVERFLOW_ACK_CLR_INTERRUPT         = 0x00000001,
} DP_TU_OVERFLOW_ACK;

/*
 * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
 */

typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE  = 0x00000000,
DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START  = 0x00000001,
} DP_VID_M_N_DOUBLE_BUFFER_MODE;

/*
 * DP_VID_M_N_GEN_EN enum
 */

typedef enum DP_VID_M_N_GEN_EN {
DP_VID_M_N_PROGRAMMED_VIA_REG            = 0x00000000,
DP_VID_M_N_CALC_AUTO                     = 0x00000001,
} DP_VID_M_N_GEN_EN;

/*
 * DP_VID_N_MUL enum
 */

typedef enum DP_VID_N_MUL {
DP_VID_M_1X_INPUT_PIXEL_RATE             = 0x00000000,
DP_VID_M_2X_INPUT_PIXEL_RATE             = 0x00000001,
DP_VID_M_4X_INPUT_PIXEL_RATE             = 0x00000002,
DP_VID_M_8X_INPUT_PIXEL_RATE             = 0x00000003,
} DP_VID_N_MUL;

/*
 * DP_VID_ENHANCED_FRAME_MODE enum
 */

typedef enum DP_VID_ENHANCED_FRAME_MODE {
VID_NORMAL_FRAME_MODE                    = 0x00000000,
VID_ENHANCED_MODE                        = 0x00000001,
} DP_VID_ENHANCED_FRAME_MODE;

/*
 * DP_VID_VBID_FIELD_POL enum
 */

typedef enum DP_VID_VBID_FIELD_POL {
DP_VID_VBID_FIELD_POL_NORMAL             = 0x00000000,
DP_VID_VBID_FIELD_POL_INV                = 0x00000001,
} DP_VID_VBID_FIELD_POL;

/*
 * DP_VID_STREAM_DISABLE_ACK enum
 */

typedef enum DP_VID_STREAM_DISABLE_ACK {
ID_STREAM_DISABLE_NO_ACK                 = 0x00000000,
ID_STREAM_DISABLE_ACKED                  = 0x00000001,
} DP_VID_STREAM_DISABLE_ACK;

/*
 * DP_VID_STREAM_DISABLE_MASK enum
 */

typedef enum DP_VID_STREAM_DISABLE_MASK {
VID_STREAM_DISABLE_MASKED                = 0x00000000,
VID_STREAM_DISABLE_UNMASK                = 0x00000001,
} DP_VID_STREAM_DISABLE_MASK;

/*
 * DPHY_ATEST_SEL_LANE0 enum
 */

typedef enum DPHY_ATEST_SEL_LANE0 {
DPHY_ATEST_LANE0_PRBS_PATTERN            = 0x00000000,
DPHY_ATEST_LANE0_REG_PATTERN             = 0x00000001,
} DPHY_ATEST_SEL_LANE0;

/*
 * DPHY_ATEST_SEL_LANE1 enum
 */

typedef enum DPHY_ATEST_SEL_LANE1 {
DPHY_ATEST_LANE1_PRBS_PATTERN            = 0x00000000,
DPHY_ATEST_LANE1_REG_PATTERN             = 0x00000001,
} DPHY_ATEST_SEL_LANE1;

/*
 * DPHY_ATEST_SEL_LANE2 enum
 */

typedef enum DPHY_ATEST_SEL_LANE2 {
DPHY_ATEST_LANE2_PRBS_PATTERN            = 0x00000000,
DPHY_ATEST_LANE2_REG_PATTERN             = 0x00000001,
} DPHY_ATEST_SEL_LANE2;

/*
 * DPHY_ATEST_SEL_LANE3 enum
 */

typedef enum DPHY_ATEST_SEL_LANE3 {
DPHY_ATEST_LANE3_PRBS_PATTERN            = 0x00000000,
DPHY_ATEST_LANE3_REG_PATTERN             = 0x00000001,
} DPHY_ATEST_SEL_LANE3;

/*
 * DPHY_BYPASS enum
 */

typedef enum DPHY_BYPASS {
DPHY_8B10B_OUTPUT                        = 0x00000000,
DPHY_DBG_OUTPUT                          = 0x00000001,
} DPHY_BYPASS;

/*
 * DPHY_SKEW_BYPASS enum
 */

typedef enum DPHY_SKEW_BYPASS {
DPHY_WITH_SKEW                           = 0x00000000,
DPHY_NO_SKEW                             = 0x00000001,
} DPHY_SKEW_BYPASS;

/*
 * DPHY_TRAINING_PATTERN_SEL enum
 */

typedef enum DPHY_TRAINING_PATTERN_SEL {
DPHY_TRAINING_PATTERN_1                  = 0x00000000,
DPHY_TRAINING_PATTERN_2                  = 0x00000001,
DPHY_TRAINING_PATTERN_3                  = 0x00000002,
DPHY_TRAINING_PATTERN_4                  = 0x00000003,
} DPHY_TRAINING_PATTERN_SEL;

/*
 * DPHY_8B10B_RESET enum
 */

typedef enum DPHY_8B10B_RESET {
DPHY_8B10B_NOT_RESET                     = 0x00000000,
DPHY_8B10B_RESETET                       = 0x00000001,
} DPHY_8B10B_RESET;

/*
 * DP_DPHY_8B10B_EXT_DISP enum
 */

typedef enum DP_DPHY_8B10B_EXT_DISP {
DP_DPHY_8B10B_EXT_DISP_ZERO              = 0x00000000,
DP_DPHY_8B10B_EXT_DISP_ONE               = 0x00000001,
} DP_DPHY_8B10B_EXT_DISP;

/*
 * DPHY_8B10B_CUR_DISP enum
 */

typedef enum DPHY_8B10B_CUR_DISP {
DPHY_8B10B_CUR_DISP_ZERO                 = 0x00000000,
DPHY_8B10B_CUR_DISP_ONE                  = 0x00000001,
} DPHY_8B10B_CUR_DISP;

/*
 * DPHY_PRBS_EN enum
 */

typedef enum DPHY_PRBS_EN {
DPHY_PRBS_DISABLE                        = 0x00000000,
DPHY_PRBS_ENABLE                         = 0x00000001,
} DPHY_PRBS_EN;

/*
 * DPHY_PRBS_SEL enum
 */

typedef enum DPHY_PRBS_SEL {
DPHY_PRBS7_SELECTED                      = 0x00000000,
DPHY_PRBS23_SELECTED                     = 0x00000001,
DPHY_PRBS11_SELECTED                     = 0x00000002,
} DPHY_PRBS_SEL;

/*
 * DPHY_FEC_ENABLE enum
 */

typedef enum DPHY_FEC_ENABLE {
DPHY_FEC_DISABLED                        = 0x00000000,
DPHY_FEC_ENABLED                         = 0x00000001,
} DPHY_FEC_ENABLE;

/*
 * FEC_ACTIVE_STATUS enum
 */

typedef enum FEC_ACTIVE_STATUS {
DPHY_FEC_NOT_ACTIVE                      = 0x00000000,
DPHY_FEC_ACTIVE                          = 0x00000001,
} FEC_ACTIVE_STATUS;

/*
 * DPHY_FEC_READY enum
 */

typedef enum DPHY_FEC_READY {
DPHY_FEC_READY_EN                        = 0x00000000,
DPHY_FEC_READY_DIS                       = 0x00000001,
} DPHY_FEC_READY;

/*
 * DPHY_LOAD_BS_COUNT_START enum
 */

typedef enum DPHY_LOAD_BS_COUNT_START {
DPHY_LOAD_BS_COUNT_STARTED               = 0x00000000,
DPHY_LOAD_BS_COUNT_NOT_STARTED           = 0x00000001,
} DPHY_LOAD_BS_COUNT_START;

/*
 * DPHY_CRC_EN enum
 */

typedef enum DPHY_CRC_EN {
DPHY_CRC_DISABLED                        = 0x00000000,
DPHY_CRC_ENABLED                         = 0x00000001,
} DPHY_CRC_EN;

/*
 * DPHY_CRC_CONT_EN enum
 */

typedef enum DPHY_CRC_CONT_EN {
DPHY_CRC_ONE_SHOT                        = 0x00000000,
DPHY_CRC_CONTINUOUS                      = 0x00000001,
} DPHY_CRC_CONT_EN;

/*
 * DPHY_CRC_FIELD enum
 */

typedef enum DPHY_CRC_FIELD {
DPHY_CRC_START_FROM_TOP_FIELD            = 0x00000000,
DPHY_CRC_START_FROM_BOTTOM_FIELD         = 0x00000001,
} DPHY_CRC_FIELD;

/*
 * DPHY_CRC_SEL enum
 */

typedef enum DPHY_CRC_SEL {
DPHY_CRC_LANE0_SELECTED                  = 0x00000000,
DPHY_CRC_LANE1_SELECTED                  = 0x00000001,
DPHY_CRC_LANE2_SELECTED                  = 0x00000002,
DPHY_CRC_LANE3_SELECTED                  = 0x00000003,
} DPHY_CRC_SEL;

/*
 * DPHY_RX_FAST_TRAINING_CAPABLE enum
 */

typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
DPHY_FAST_TRAINING_NOT_CAPABLE_0         = 0x00000000,
DPHY_FAST_TRAINING_CAPABLE               = 0x00000001,
} DPHY_RX_FAST_TRAINING_CAPABLE;

/*
 * DP_SEC_COLLISION_ACK enum
 */

typedef enum DP_SEC_COLLISION_ACK {
DP_SEC_COLLISION_ACK_NO_EFFECT           = 0x00000000,
DP_SEC_COLLISION_ACK_CLR_FLAG            = 0x00000001,
} DP_SEC_COLLISION_ACK;

/*
 * DP_SEC_AUDIO_MUTE enum
 */

typedef enum DP_SEC_AUDIO_MUTE {
DP_SEC_AUDIO_MUTE_HW_CTRL                = 0x00000000,
DP_SEC_AUDIO_MUTE_SW_CTRL                = 0x00000001,
} DP_SEC_AUDIO_MUTE;

/*
 * DP_SEC_TIMESTAMP_MODE enum
 */

typedef enum DP_SEC_TIMESTAMP_MODE {
DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE       = 0x00000000,
DP_SEC_TIMESTAMP_AUTO_CALC_MODE          = 0x00000001,
} DP_SEC_TIMESTAMP_MODE;

/*
 * DP_SEC_ASP_PRIORITY enum
 */

typedef enum DP_SEC_ASP_PRIORITY {
DP_SEC_ASP_LOW_PRIORITY                  = 0x00000000,
DP_SEC_ASP_HIGH_PRIORITY                 = 0x00000001,
} DP_SEC_ASP_PRIORITY;

/*
 * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
 */

typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ         = 0x00000000,
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED  = 0x00000001,
} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;

/*
 * DP_MSE_SAT_UPDATE_ACT enum
 */

typedef enum DP_MSE_SAT_UPDATE_ACT {
DP_MSE_SAT_UPDATE_NO_ACTION              = 0x00000000,
DP_MSE_SAT_UPDATE_WITH_TRIGGER           = 0x00000001,
DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER        = 0x00000002,
} DP_MSE_SAT_UPDATE_ACT;

/*
 * DP_MSE_LINK_LINE enum
 */

typedef enum DP_MSE_LINK_LINE {
DP_MSE_LINK_LINE_32_MTP_LONG             = 0x00000000,
DP_MSE_LINK_LINE_64_MTP_LONG             = 0x00000001,
DP_MSE_LINK_LINE_128_MTP_LONG            = 0x00000002,
DP_MSE_LINK_LINE_256_MTP_LONG            = 0x00000003,
} DP_MSE_LINK_LINE;

/*
 * DP_MSE_BLANK_CODE enum
 */

typedef enum DP_MSE_BLANK_CODE {
DP_MSE_BLANK_CODE_SF_FILLED              = 0x00000000,
DP_MSE_BLANK_CODE_ZERO_FILLED            = 0x00000001,
} DP_MSE_BLANK_CODE;

/*
 * DP_MSE_TIMESTAMP_MODE enum
 */

typedef enum DP_MSE_TIMESTAMP_MODE {
DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE  = 0x00000000,
DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE   = 0x00000001,
} DP_MSE_TIMESTAMP_MODE;

/*
 * DP_MSE_ZERO_ENCODER enum
 */

typedef enum DP_MSE_ZERO_ENCODER {
DP_MSE_NOT_ZERO_FE_ENCODER               = 0x00000000,
DP_MSE_ZERO_FE_ENCODER                   = 0x00000001,
} DP_MSE_ZERO_ENCODER;

/*
 * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
 */

typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
DP_DPHY_HBR2_PASS_THROUGH                = 0x00000000,
DP_DPHY_HBR2_PATTERN_1                   = 0x00000001,
DP_DPHY_HBR2_PATTERN_2_NEG               = 0x00000002,
DP_DPHY_HBR2_PATTERN_3                   = 0x00000003,
DP_DPHY_HBR2_PATTERN_2_POS               = 0x00000006,
} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;

/*
 * DPHY_CRC_MST_PHASE_ERROR_ACK enum
 */

typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
DPHY_CRC_MST_PHASE_ERROR_NO_ACK          = 0x00000000,
DPHY_CRC_MST_PHASE_ERROR_ACKED           = 0x00000001,
} DPHY_CRC_MST_PHASE_ERROR_ACK;

/*
 * DPHY_SW_FAST_TRAINING_START enum
 */

typedef enum DPHY_SW_FAST_TRAINING_START {
DPHY_SW_FAST_TRAINING_NOT_STARTED        = 0x00000000,
DPHY_SW_FAST_TRAINING_STARTED            = 0x00000001,
} DPHY_SW_FAST_TRAINING_START;

/*
 * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
 */

typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED  = 0x00000000,
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED  = 0x00000001,
} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;

/*
 * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
 */

typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
DP_DPHY_FAST_TRAINING_COMPLETE_MASKED    = 0x00000000,
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED  = 0x00000001,
} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;

/*
 * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
 */

typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED  = 0x00000000,
DP_DPHY_FAST_TRAINING_COMPLETE_ACKED     = 0x00000001,
} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;

/*
 * DP_MSA_V_TIMING_OVERRIDE_EN enum
 */

typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
MSA_V_TIMING_OVERRIDE_DISABLED           = 0x00000000,
MSA_V_TIMING_OVERRIDE_ENABLED            = 0x00000001,
} DP_MSA_V_TIMING_OVERRIDE_EN;

/*
 * DP_SEC_GSP0_PRIORITY enum
 */

typedef enum DP_SEC_GSP0_PRIORITY {
SEC_GSP0_PRIORITY_LOW                    = 0x00000000,
SEC_GSP0_PRIORITY_HIGH                   = 0x00000001,
} DP_SEC_GSP0_PRIORITY;

/*
 * DP_SEC_GSP_SEND enum
 */

typedef enum DP_SEC_GSP_SEND {
NOT_SENT                                 = 0x00000000,
FORCE_SENT                               = 0x00000001,
} DP_SEC_GSP_SEND;

/*
 * DP_SEC_GSP_SEND_ANY_LINE enum
 */

typedef enum DP_SEC_GSP_SEND_ANY_LINE {
SEND_AT_LINK_NUMBER                      = 0x00000000,
SEND_AT_EARLIEST_TIME                    = 0x00000001,
} DP_SEC_GSP_SEND_ANY_LINE;

/*
 * DP_SEC_LINE_REFERENCE enum
 */

typedef enum DP_SEC_LINE_REFERENCE {
REFER_TO_DP_SOF                          = 0x00000000,
REFER_TO_OTG_SOF                         = 0x00000001,
} DP_SEC_LINE_REFERENCE;

/*
 * DP_SEC_GSP_SEND_PPS enum
 */

typedef enum DP_SEC_GSP_SEND_PPS {
SEND_NORMAL_PACKET                       = 0x00000000,
SEND_PPS_PACKET                          = 0x00000001,
} DP_SEC_GSP_SEND_PPS;

/*
 * DP_ML_PHY_SEQ_MODE enum
 */

typedef enum DP_ML_PHY_SEQ_MODE {
DP_ML_PHY_SEQ_LINE_NUM                   = 0x00000000,
DP_ML_PHY_SEQ_IMMEDIATE                  = 0x00000001,
} DP_ML_PHY_SEQ_MODE;

/*
 * DP_LINK_TRAINING_SWITCH_MODE enum
 */

typedef enum DP_LINK_TRAINING_SWITCH_MODE {
DP_LINK_TRAINING_SWITCH_TO_IDLE          = 0x00000000,
DP_LINK_TRAINING_SWITCH_TO_VIDEO         = 0x00000001,
} DP_LINK_TRAINING_SWITCH_MODE;

/*
 * DP_DSC_MODE enum
 */

typedef enum DP_DSC_MODE {
DP_DSC_DISABLE                           = 0x00000000,
DP_DSC_444_SIMPLE_422                    = 0x00000001,
DP_DSC_NATIVE_422_420                    = 0x00000002,
} DP_DSC_MODE;

/*******************************************************
 * DIG Enums
 *******************************************************/

/*
 * HDMI_KEEPOUT_MODE enum
 */

typedef enum HDMI_KEEPOUT_MODE {
HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC        = 0x00000000,
HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC      = 0x00000001,
} HDMI_KEEPOUT_MODE;

/*
 * HDMI_CLOCK_CHANNEL_RATE enum
 */

typedef enum HDMI_CLOCK_CHANNEL_RATE {
HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE  = 0x00000000,
HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE  = 0x00000001,
} HDMI_CLOCK_CHANNEL_RATE;

/*
 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
 */

typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE     = 0x00000000,
HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE    = 0x00000001,
} HDMI_NO_EXTRA_NULL_PACKET_FILLED;

/*
 * HDMI_PACKET_GEN_VERSION enum
 */

typedef enum HDMI_PACKET_GEN_VERSION {
HDMI_PACKET_GEN_VERSION_OLD              = 0x00000000,
HDMI_PACKET_GEN_VERSION_NEW              = 0x00000001,
} HDMI_PACKET_GEN_VERSION;

/*
 * HDMI_ERROR_ACK enum
 */

typedef enum HDMI_ERROR_ACK {
HDMI_ERROR_ACK_INT                       = 0x00000000,
HDMI_ERROR_NOT_ACK                       = 0x00000001,
} HDMI_ERROR_ACK;

/*
 * HDMI_ERROR_MASK enum
 */

typedef enum HDMI_ERROR_MASK {
HDMI_ERROR_MASK_INT                      = 0x00000000,
HDMI_ERROR_NOT_MASK                      = 0x00000001,
} HDMI_ERROR_MASK;

/*
 * HDMI_DEEP_COLOR_DEPTH enum
 */

typedef enum HDMI_DEEP_COLOR_DEPTH {
HDMI_DEEP_COLOR_DEPTH_24BPP              = 0x00000000,
HDMI_DEEP_COLOR_DEPTH_30BPP              = 0x00000001,
HDMI_DEEP_COLOR_DEPTH_36BPP              = 0x00000002,
HDMI_DEEP_COLOR_DEPTH_48BPP              = 0x00000003,
} HDMI_DEEP_COLOR_DEPTH;

/*
 * HDMI_AUDIO_DELAY_EN enum
 */

typedef enum HDMI_AUDIO_DELAY_EN {
HDMI_AUDIO_DELAY_DISABLE                 = 0x00000000,
HDMI_AUDIO_DELAY_58CLK                   = 0x00000001,
HDMI_AUDIO_DELAY_56CLK                   = 0x00000002,
HDMI_AUDIO_DELAY_RESERVED                = 0x00000003,
} HDMI_AUDIO_DELAY_EN;

/*
 * HDMI_AUDIO_SEND_MAX_PACKETS enum
 */

typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
HDMI_NOT_SEND_MAX_AUDIO_PACKETS          = 0x00000000,
HDMI_SEND_MAX_AUDIO_PACKETS              = 0x00000001,
} HDMI_AUDIO_SEND_MAX_PACKETS;

/*
 * HDMI_ACR_SEND enum
 */

typedef enum HDMI_ACR_SEND {
HDMI_ACR_NOT_SEND                        = 0x00000000,
HDMI_ACR_PKT_SEND                        = 0x00000001,
} HDMI_ACR_SEND;

/*
 * HDMI_ACR_CONT enum
 */

typedef enum HDMI_ACR_CONT {
HDMI_ACR_CONT_DISABLE                    = 0x00000000,
HDMI_ACR_CONT_ENABLE                     = 0x00000001,
} HDMI_ACR_CONT;

/*
 * HDMI_ACR_SELECT enum
 */

typedef enum HDMI_ACR_SELECT {
HDMI_ACR_SELECT_HW                       = 0x00000000,
HDMI_ACR_SELECT_32K                      = 0x00000001,
HDMI_ACR_SELECT_44K                      = 0x00000002,
HDMI_ACR_SELECT_48K                      = 0x00000003,
} HDMI_ACR_SELECT;

/*
 * HDMI_ACR_SOURCE enum
 */

typedef enum HDMI_ACR_SOURCE {
HDMI_ACR_SOURCE_HW                       = 0x00000000,
HDMI_ACR_SOURCE_SW                       = 0x00000001,
} HDMI_ACR_SOURCE;

/*
 * HDMI_ACR_N_MULTIPLE enum
 */

typedef enum HDMI_ACR_N_MULTIPLE {
HDMI_ACR_0_MULTIPLE_RESERVED             = 0x00000000,
HDMI_ACR_1_MULTIPLE                      = 0x00000001,
HDMI_ACR_2_MULTIPLE                      = 0x00000002,
HDMI_ACR_3_MULTIPLE_RESERVED             = 0x00000003,
HDMI_ACR_4_MULTIPLE                      = 0x00000004,
HDMI_ACR_5_MULTIPLE_RESERVED             = 0x00000005,
HDMI_ACR_6_MULTIPLE_RESERVED             = 0x00000006,
HDMI_ACR_7_MULTIPLE_RESERVED             = 0x00000007,
} HDMI_ACR_N_MULTIPLE;

/*
 * HDMI_ACR_AUDIO_PRIORITY enum
 */

typedef enum HDMI_ACR_AUDIO_PRIORITY {
HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE  = 0x00000000,
HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT  = 0x00000001,
} HDMI_ACR_AUDIO_PRIORITY;

/*
 * HDMI_NULL_SEND enum
 */

typedef enum HDMI_NULL_SEND {
HDMI_NULL_NOT_SEND                       = 0x00000000,
HDMI_NULL_PKT_SEND                       = 0x00000001,
} HDMI_NULL_SEND;

/*
 * HDMI_GC_SEND enum
 */

typedef enum HDMI_GC_SEND {
HDMI_GC_NOT_SEND                         = 0x00000000,
HDMI_GC_PKT_SEND                         = 0x00000001,
} HDMI_GC_SEND;

/*
 * HDMI_GC_CONT enum
 */

typedef enum HDMI_GC_CONT {
HDMI_GC_CONT_DISABLE                     = 0x00000000,
HDMI_GC_CONT_ENABLE                      = 0x00000001,
} HDMI_GC_CONT;

/*
 * HDMI_ISRC_SEND enum
 */

typedef enum HDMI_ISRC_SEND {
HDMI_ISRC_NOT_SEND                       = 0x00000000,
HDMI_ISRC_PKT_SEND                       = 0x00000001,
} HDMI_ISRC_SEND;

/*
 * HDMI_ISRC_CONT enum
 */

typedef enum HDMI_ISRC_CONT {
HDMI_ISRC_CONT_DISABLE                   = 0x00000000,
HDMI_ISRC_CONT_ENABLE                    = 0x00000001,
} HDMI_ISRC_CONT;

/*
 * HDMI_AUDIO_INFO_SEND enum
 */

typedef enum HDMI_AUDIO_INFO_SEND {
HDMI_AUDIO_INFO_NOT_SEND                 = 0x00000000,
HDMI_AUDIO_INFO_PKT_SEND                 = 0x00000001,
} HDMI_AUDIO_INFO_SEND;

/*
 * HDMI_AUDIO_INFO_CONT enum
 */

typedef enum HDMI_AUDIO_INFO_CONT {
HDMI_AUDIO_INFO_CONT_DISABLE             = 0x00000000,
HDMI_AUDIO_INFO_CONT_ENABLE              = 0x00000001,
} HDMI_AUDIO_INFO_CONT;

/*
 * HDMI_MPEG_INFO_SEND enum
 */

typedef enum HDMI_MPEG_INFO_SEND {
HDMI_MPEG_INFO_NOT_SEND                  = 0x00000000,
HDMI_MPEG_INFO_PKT_SEND                  = 0x00000001,
} HDMI_MPEG_INFO_SEND;

/*
 * HDMI_MPEG_INFO_CONT enum
 */

typedef enum HDMI_MPEG_INFO_CONT {
HDMI_MPEG_INFO_CONT_DISABLE              = 0x00000000,
HDMI_MPEG_INFO_CONT_ENABLE               = 0x00000001,
} HDMI_MPEG_INFO_CONT;

/*
 * HDMI_GENERIC_SEND enum
 */

typedef enum HDMI_GENERIC_SEND {
HDMI_GENERIC_NOT_SEND                    = 0x00000000,
HDMI_GENERIC_PKT_SEND                    = 0x00000001,
} HDMI_GENERIC_SEND;

/*
 * HDMI_GENERIC_CONT enum
 */

typedef enum HDMI_GENERIC_CONT {
HDMI_GENERIC_CONT_DISABLE                = 0x00000000,
HDMI_GENERIC_CONT_ENABLE                 = 0x00000001,
} HDMI_GENERIC_CONT;

/*
 * HDMI_GC_AVMUTE_CONT enum
 */

typedef enum HDMI_GC_AVMUTE_CONT {
HDMI_GC_AVMUTE_CONT_DISABLE              = 0x00000000,
HDMI_GC_AVMUTE_CONT_ENABLE               = 0x00000001,
} HDMI_GC_AVMUTE_CONT;

/*
 * HDMI_PACKING_PHASE_OVERRIDE enum
 */

typedef enum HDMI_PACKING_PHASE_OVERRIDE {
HDMI_PACKING_PHASE_SET_BY_HW             = 0x00000000,
HDMI_PACKING_PHASE_SET_BY_SW             = 0x00000001,
} HDMI_PACKING_PHASE_OVERRIDE;

/*
 * TMDS_PIXEL_ENCODING enum
 */

typedef enum TMDS_PIXEL_ENCODING {
TMDS_PIXEL_ENCODING_444_OR_420           = 0x00000000,
TMDS_PIXEL_ENCODING_422                  = 0x00000001,
} TMDS_PIXEL_ENCODING;

/*
 * TMDS_COLOR_FORMAT enum
 */

typedef enum TMDS_COLOR_FORMAT {
TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP  = 0x00000000,
TMDS_COLOR_FORMAT_TWIN30BPP_LSB          = 0x00000001,
TMDS_COLOR_FORMAT_DUAL30BPP              = 0x00000002,
TMDS_COLOR_FORMAT_RESERVED               = 0x00000003,
} TMDS_COLOR_FORMAT;

/*
 * TMDS_STEREOSYNC_CTL_SEL_REG enum
 */

typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
TMDS_STEREOSYNC_CTL0                     = 0x00000000,
TMDS_STEREOSYNC_CTL1                     = 0x00000001,
TMDS_STEREOSYNC_CTL2                     = 0x00000002,
TMDS_STEREOSYNC_CTL3                     = 0x00000003,
} TMDS_STEREOSYNC_CTL_SEL_REG;

/*
 * TMDS_CTL0_DATA_SEL enum
 */

typedef enum TMDS_CTL0_DATA_SEL {
TMDS_CTL0_DATA_SEL0_RESERVED             = 0x00000000,
TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
TMDS_CTL0_DATA_SEL2_VSYNC                = 0x00000002,
TMDS_CTL0_DATA_SEL3_RESERVED             = 0x00000003,
TMDS_CTL0_DATA_SEL4_HSYNC                = 0x00000004,
TMDS_CTL0_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
TMDS_CTL0_DATA_SEL8_RANDOM_DATA          = 0x00000006,
TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA    = 0x00000007,
} TMDS_CTL0_DATA_SEL;

/*
 * TMDS_CTL0_DATA_INVERT enum
 */

typedef enum TMDS_CTL0_DATA_INVERT {
TMDS_CTL0_DATA_NORMAL                    = 0x00000000,
TMDS_CTL0_DATA_INVERT_EN                 = 0x00000001,
} TMDS_CTL0_DATA_INVERT;

/*
 * TMDS_CTL0_DATA_MODULATION enum
 */

typedef enum TMDS_CTL0_DATA_MODULATION {
TMDS_CTL0_DATA_MODULATION_DISABLE        = 0x00000000,
TMDS_CTL0_DATA_MODULATION_BIT0           = 0x00000001,
TMDS_CTL0_DATA_MODULATION_BIT1           = 0x00000002,
TMDS_CTL0_DATA_MODULATION_BIT2           = 0x00000003,
} TMDS_CTL0_DATA_MODULATION;

/*
 * TMDS_CTL0_PATTERN_OUT_EN enum
 */

typedef enum TMDS_CTL0_PATTERN_OUT_EN {
TMDS_CTL0_PATTERN_OUT_DISABLE            = 0x00000000,
TMDS_CTL0_PATTERN_OUT_ENABLE             = 0x00000001,
} TMDS_CTL0_PATTERN_OUT_EN;

/*
 * TMDS_CTL1_DATA_SEL enum
 */

typedef enum TMDS_CTL1_DATA_SEL {
TMDS_CTL1_DATA_SEL0_RESERVED             = 0x00000000,
TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
TMDS_CTL1_DATA_SEL2_VSYNC                = 0x00000002,
TMDS_CTL1_DATA_SEL3_RESERVED             = 0x00000003,
TMDS_CTL1_DATA_SEL4_HSYNC                = 0x00000004,
TMDS_CTL1_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
TMDS_CTL1_DATA_SEL8_BLANK_TIME           = 0x00000006,
TMDS_CTL1_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
} TMDS_CTL1_DATA_SEL;

/*
 * TMDS_CTL1_DATA_INVERT enum
 */

typedef enum TMDS_CTL1_DATA_INVERT {
TMDS_CTL1_DATA_NORMAL                    = 0x00000000,
TMDS_CTL1_DATA_INVERT_EN                 = 0x00000001,
} TMDS_CTL1_DATA_INVERT;

/*
 * TMDS_CTL1_DATA_MODULATION enum
 */

typedef enum TMDS_CTL1_DATA_MODULATION {
TMDS_CTL1_DATA_MODULATION_DISABLE        = 0x00000000,
TMDS_CTL1_DATA_MODULATION_BIT0           = 0x00000001,
TMDS_CTL1_DATA_MODULATION_BIT1           = 0x00000002,
TMDS_CTL1_DATA_MODULATION_BIT2           = 0x00000003,
} TMDS_CTL1_DATA_MODULATION;

/*
 * TMDS_CTL1_PATTERN_OUT_EN enum
 */

typedef enum TMDS_CTL1_PATTERN_OUT_EN {
TMDS_CTL1_PATTERN_OUT_DISABLE            = 0x00000000,
TMDS_CTL1_PATTERN_OUT_ENABLE             = 0x00000001,
} TMDS_CTL1_PATTERN_OUT_EN;

/*
 * TMDS_CTL2_DATA_SEL enum
 */

typedef enum TMDS_CTL2_DATA_SEL {
TMDS_CTL2_DATA_SEL0_RESERVED             = 0x00000000,
TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
TMDS_CTL2_DATA_SEL2_VSYNC                = 0x00000002,
TMDS_CTL2_DATA_SEL3_RESERVED             = 0x00000003,
TMDS_CTL2_DATA_SEL4_HSYNC                = 0x00000004,
TMDS_CTL2_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
TMDS_CTL2_DATA_SEL8_BLANK_TIME           = 0x00000006,
TMDS_CTL2_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
} TMDS_CTL2_DATA_SEL;

/*
 * TMDS_CTL2_DATA_INVERT enum
 */

typedef enum TMDS_CTL2_DATA_INVERT {
TMDS_CTL2_DATA_NORMAL                    = 0x00000000,
TMDS_CTL2_DATA_INVERT_EN                 = 0x00000001,
} TMDS_CTL2_DATA_INVERT;

/*
 * TMDS_CTL2_DATA_MODULATION enum
 */

typedef enum TMDS_CTL2_DATA_MODULATION {
TMDS_CTL2_DATA_MODULATION_DISABLE        = 0x00000000,
TMDS_CTL2_DATA_MODULATION_BIT0           = 0x00000001,
TMDS_CTL2_DATA_MODULATION_BIT1           = 0x00000002,
TMDS_CTL2_DATA_MODULATION_BIT2           = 0x00000003,
} TMDS_CTL2_DATA_MODULATION;

/*
 * TMDS_CTL2_PATTERN_OUT_EN enum
 */

typedef enum TMDS_CTL2_PATTERN_OUT_EN {
TMDS_CTL2_PATTERN_OUT_DISABLE            = 0x00000000,
TMDS_CTL2_PATTERN_OUT_ENABLE             = 0x00000001,
} TMDS_CTL2_PATTERN_OUT_EN;

/*
 * TMDS_CTL3_DATA_INVERT enum
 */

typedef enum TMDS_CTL3_DATA_INVERT {
TMDS_CTL3_DATA_NORMAL                    = 0x00000000,
TMDS_CTL3_DATA_INVERT_EN                 = 0x00000001,
} TMDS_CTL3_DATA_INVERT;

/*
 * TMDS_CTL3_DATA_MODULATION enum
 */

typedef enum TMDS_CTL3_DATA_MODULATION {
TMDS_CTL3_DATA_MODULATION_DISABLE        = 0x00000000,
TMDS_CTL3_DATA_MODULATION_BIT0           = 0x00000001,
TMDS_CTL3_DATA_MODULATION_BIT1           = 0x00000002,
TMDS_CTL3_DATA_MODULATION_BIT2           = 0x00000003,
} TMDS_CTL3_DATA_MODULATION;

/*
 * TMDS_CTL3_PATTERN_OUT_EN enum
 */

typedef enum TMDS_CTL3_PATTERN_OUT_EN {
TMDS_CTL3_PATTERN_OUT_DISABLE            = 0x00000000,
TMDS_CTL3_PATTERN_OUT_ENABLE             = 0x00000001,
} TMDS_CTL3_PATTERN_OUT_EN;

/*
 * TMDS_CTL3_DATA_SEL enum
 */

typedef enum TMDS_CTL3_DATA_SEL {
TMDS_CTL3_DATA_SEL0_RESERVED             = 0x00000000,
TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
TMDS_CTL3_DATA_SEL2_VSYNC                = 0x00000002,
TMDS_CTL3_DATA_SEL3_RESERVED             = 0x00000003,
TMDS_CTL3_DATA_SEL4_HSYNC                = 0x00000004,
TMDS_CTL3_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
TMDS_CTL3_DATA_SEL8_BLANK_TIME           = 0x00000006,
TMDS_CTL3_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
} TMDS_CTL3_DATA_SEL;

/*
 * DIG_FE_CNTL_SOURCE_SELECT enum
 */

typedef enum DIG_FE_CNTL_SOURCE_SELECT {
DIG_FE_SOURCE_FROM_OTG0                  = 0x00000000,
DIG_FE_SOURCE_FROM_OTG1                  = 0x00000001,
DIG_FE_SOURCE_FROM_OTG2                  = 0x00000002,
DIG_FE_SOURCE_FROM_OTG3                  = 0x00000003,
DIG_FE_SOURCE_FROM_OTG4                  = 0x00000004,
DIG_FE_SOURCE_FROM_OTG5                  = 0x00000005,
DIG_FE_SOURCE_RESERVED                   = 0x00000006,
} DIG_FE_CNTL_SOURCE_SELECT;

/*
 * DIG_FE_CNTL_STEREOSYNC_SELECT enum
 */

typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
DIG_FE_STEREOSYNC_FROM_OTG0              = 0x00000000,
DIG_FE_STEREOSYNC_FROM_OTG1              = 0x00000001,
DIG_FE_STEREOSYNC_FROM_OTG2              = 0x00000002,
DIG_FE_STEREOSYNC_FROM_OTG3              = 0x00000003,
DIG_FE_STEREOSYNC_FROM_OTG4              = 0x00000004,
DIG_FE_STEREOSYNC_FROM_OTG5              = 0x00000005,
DIG_FE_STEREOSYNC_RESERVED               = 0x00000006,
} DIG_FE_CNTL_STEREOSYNC_SELECT;

/*
 * DIG_FIFO_READ_CLOCK_SRC enum
 */

typedef enum DIG_FIFO_READ_CLOCK_SRC {
DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG        = 0x00000000,
DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE  = 0x00000001,
} DIG_FIFO_READ_CLOCK_SRC;

/*
 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
 */

typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
DIG_OUTPUT_CRC_ON_LINK0                  = 0x00000000,
DIG_OUTPUT_CRC_ON_LINK1                  = 0x00000001,
} DIG_OUTPUT_CRC_CNTL_LINK_SEL;

/*
 * DIG_OUTPUT_CRC_DATA_SEL enum
 */

typedef enum DIG_OUTPUT_CRC_DATA_SEL {
DIG_OUTPUT_CRC_FOR_FULLFRAME             = 0x00000000,
DIG_OUTPUT_CRC_FOR_ACTIVEONLY            = 0x00000001,
DIG_OUTPUT_CRC_FOR_VBI                   = 0x00000002,
DIG_OUTPUT_CRC_FOR_AUDIO                 = 0x00000003,
} DIG_OUTPUT_CRC_DATA_SEL;

/*
 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
 */

typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
DIG_IN_NORMAL_OPERATION                  = 0x00000000,
DIG_IN_DEBUG_MODE                        = 0x00000001,
} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;

/*
 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
 */

typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
DIG_10BIT_TEST_PATTERN                   = 0x00000000,
DIG_ALTERNATING_TEST_PATTERN             = 0x00000001,
} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;

/*
 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
 */

typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
DIG_TEST_PATTERN_NORMAL                  = 0x00000000,
DIG_TEST_PATTERN_RANDOM                  = 0x00000001,
} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;

/*
 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
 */

typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
DIG_RANDOM_PATTERN_ENABLED               = 0x00000000,
DIG_RANDOM_PATTERN_RESETED               = 0x00000001,
} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;

/*
 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
 */

typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE   = 0x00000000,
DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG  = 0x00000001,
} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;

/*
 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
 */

typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS  = 0x00000000,
DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH  = 0x00000001,
} DIG_RANDOM_PATTERN_SEED_RAN_PAT;

/*
 * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
 */

typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
DIG_FIFO_USE_OVERWRITE_LEVEL             = 0x00000000,
DIG_FIFO_USE_CAL_AVERAGE_LEVEL           = 0x00000001,
} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;

/*
 * DIG_FIFO_ERROR_ACK enum
 */

typedef enum DIG_FIFO_ERROR_ACK {
DIG_FIFO_ERROR_ACK_INT                   = 0x00000000,
DIG_FIFO_ERROR_NOT_ACK                   = 0x00000001,
} DIG_FIFO_ERROR_ACK;

/*
 * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
 */

typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
DIG_FIFO_NOT_FORCE_RECAL_AVERAGE         = 0x00000000,
DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL       = 0x00000001,
} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;

/*
 * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
 */

typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
DIG_FIFO_NOT_FORCE_RECOMP_MINMAX         = 0x00000000,
DIG_FIFO_FORCE_RECOMP_MINMAX             = 0x00000001,
} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;

/*
 * AFMT_INTERRUPT_STATUS_CHG_MASK enum
 */

typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
AFMT_INTERRUPT_DISABLE                   = 0x00000000,
AFMT_INTERRUPT_ENABLE                    = 0x00000001,
} AFMT_INTERRUPT_STATUS_CHG_MASK;

/*
 * HDMI_GC_AVMUTE enum
 */

typedef enum HDMI_GC_AVMUTE {
HDMI_GC_AVMUTE_SET                       = 0x00000000,
HDMI_GC_AVMUTE_UNSET                     = 0x00000001,
} HDMI_GC_AVMUTE;

/*
 * HDMI_DEFAULT_PAHSE enum
 */

typedef enum HDMI_DEFAULT_PAHSE {
HDMI_DEFAULT_PHASE_IS_0                  = 0x00000000,
HDMI_DEFAULT_PHASE_IS_1                  = 0x00000001,
} HDMI_DEFAULT_PAHSE;

/*
 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
 */

typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS  = 0x00000000,
AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER       = 0x00000001,
} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;

/*
 * AUDIO_LAYOUT_SELECT enum
 */

typedef enum AUDIO_LAYOUT_SELECT {
AUDIO_LAYOUT_0                           = 0x00000000,
AUDIO_LAYOUT_1                           = 0x00000001,
} AUDIO_LAYOUT_SELECT;

/*
 * AFMT_AUDIO_CRC_CONTROL_CONT enum
 */

typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
AFMT_AUDIO_CRC_ONESHOT                   = 0x00000000,
AFMT_AUDIO_CRC_AUTO_RESTART              = 0x00000001,
} AFMT_AUDIO_CRC_CONTROL_CONT;

/*
 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
 */

typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT    = 0x00000000,
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT   = 0x00000001,
} AFMT_AUDIO_CRC_CONTROL_SOURCE;

/*
 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
 */

typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
AFMT_AUDIO_CRC_CH0_SIG                   = 0x00000000,
AFMT_AUDIO_CRC_CH1_SIG                   = 0x00000001,
AFMT_AUDIO_CRC_CH2_SIG                   = 0x00000002,
AFMT_AUDIO_CRC_CH3_SIG                   = 0x00000003,
AFMT_AUDIO_CRC_CH4_SIG                   = 0x00000004,
AFMT_AUDIO_CRC_CH5_SIG                   = 0x00000005,
AFMT_AUDIO_CRC_CH6_SIG                   = 0x00000006,
AFMT_AUDIO_CRC_CH7_SIG                   = 0x00000007,
AFMT_AUDIO_CRC_RESERVED_8                = 0x00000008,
AFMT_AUDIO_CRC_RESERVED_9                = 0x00000009,
AFMT_AUDIO_CRC_RESERVED_10               = 0x0000000a,
AFMT_AUDIO_CRC_RESERVED_11               = 0x0000000b,
AFMT_AUDIO_CRC_RESERVED_12               = 0x0000000c,
AFMT_AUDIO_CRC_RESERVED_13               = 0x0000000d,
AFMT_AUDIO_CRC_RESERVED_14               = 0x0000000e,
AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT        = 0x0000000f,
} AFMT_AUDIO_CRC_CONTROL_CH_SEL;

/*
 * AFMT_RAMP_CONTROL0_SIGN enum
 */

typedef enum AFMT_RAMP_CONTROL0_SIGN {
AFMT_RAMP_SIGNED                         = 0x00000000,
AFMT_RAMP_UNSIGNED                       = 0x00000001,
} AFMT_RAMP_CONTROL0_SIGN;

/*
 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
 */

typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
AFMT_AUDIO_PACKET_SENT_DISABLED          = 0x00000000,
AFMT_AUDIO_PACKET_SENT_ENABLED           = 0x00000001,
} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;

/*
 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
 */

typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED  = 0x00000000,
AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED  = 0x00000001,
} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;

/*
 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
 */

typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK  = 0x00000000,
AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS  = 0x00000001,
} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;

/*
 * AFMT_AUDIO_SRC_CONTROL_SELECT enum
 */

typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
AFMT_AUDIO_SRC_FROM_AZ_STREAM0           = 0x00000000,
AFMT_AUDIO_SRC_FROM_AZ_STREAM1           = 0x00000001,
AFMT_AUDIO_SRC_FROM_AZ_STREAM2           = 0x00000002,
AFMT_AUDIO_SRC_FROM_AZ_STREAM3           = 0x00000003,
AFMT_AUDIO_SRC_FROM_AZ_STREAM4           = 0x00000004,
AFMT_AUDIO_SRC_FROM_AZ_STREAM5           = 0x00000005,
AFMT_AUDIO_SRC_RESERVED                  = 0x00000006,
} AFMT_AUDIO_SRC_CONTROL_SELECT;

/*
 * DIG_BE_CNTL_MODE enum
 */

typedef enum DIG_BE_CNTL_MODE {
DIG_BE_DP_SST_MODE                       = 0x00000000,
DIG_BE_RESERVED1                         = 0x00000001,
DIG_BE_TMDS_DVI_MODE                     = 0x00000002,
DIG_BE_TMDS_HDMI_MODE                    = 0x00000003,
DIG_BE_RESERVED4                         = 0x00000004,
DIG_BE_DP_MST_MODE                       = 0x00000005,
DIG_BE_RESERVED2                         = 0x00000006,
DIG_BE_RESERVED3                         = 0x00000007,
} DIG_BE_CNTL_MODE;

/*
 * DIG_BE_CNTL_HPD_SELECT enum
 */

typedef enum DIG_BE_CNTL_HPD_SELECT {
DIG_BE_CNTL_HPD1                         = 0x00000000,
DIG_BE_CNTL_HPD2                         = 0x00000001,
DIG_BE_CNTL_HPD3                         = 0x00000002,
DIG_BE_CNTL_HPD4                         = 0x00000003,
DIG_BE_CNTL_HPD5                         = 0x00000004,
DIG_BE_CNTL_HPD6                         = 0x00000005,
DIG_BE_CNTL_NO_HPD                       = 0x00000006,
} DIG_BE_CNTL_HPD_SELECT;

/*
 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
 */

typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS     = 0x00000000,
LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH   = 0x00000001,
} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;

/*
 * TMDS_SYNC_PHASE enum
 */

typedef enum TMDS_SYNC_PHASE {
TMDS_NOT_SYNC_PHASE_ON_FRAME_START       = 0x00000000,
TMDS_SYNC_PHASE_ON_FRAME_START           = 0x00000001,
} TMDS_SYNC_PHASE;

/*
 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
 */

typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS  = 0x00000000,
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL  = 0x00000001,
} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;

/*
 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
 */

typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE   = 0x00000000,
TMDS_TRANSMITTER_HPD_MASK_OVERRIDE       = 0x00000001,
} TMDS_TRANSMITTER_ENABLE_HPD_MASK;

/*
 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
 */

typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE  = 0x00000001,
} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;

/*
 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
 */

typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE  = 0x00000001,
} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;

/*
 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE  = 0x00000000,
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON  = 0x00000001,
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x00000002,
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE  = 0x00000003,
} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;

/*
 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK   = 0x00000000,
TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK     = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;

/*
 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK   = 0x00000000,
TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK     = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;

/*
 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE   = 0x00000000,
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE    = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;

/*
 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD      = 0x00000000,
TMDS_TRANSMITTER_PLL_RST_ON_HPD          = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;

/*
 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK   = 0x00000000,
TMDS_TRANSMITTER_TMCLK_FROM_PADS         = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;

/*
 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK   = 0x00000000,
TMDS_TRANSMITTER_TDCLK_FROM_PADS         = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;

/*
 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
TMDS_TRANSMITTER_PLLSEL_BY_HW            = 0x00000000,
TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW  = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;

/*
 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT    = 0x00000000,
TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT  = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;

/*
 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
 */

typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT    = 0x00000000,
TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT  = 0x00000001,
} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;

/*
 * TMDS_REG_TEST_OUTPUTA_CNTLA enum
 */

typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0      = 0x00000000,
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1      = 0x00000001,
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2      = 0x00000002,
TMDS_REG_TEST_OUTPUTA_CNTLA_NA           = 0x00000003,
} TMDS_REG_TEST_OUTPUTA_CNTLA;

/*
 * TMDS_REG_TEST_OUTPUTB_CNTLB enum
 */

typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0      = 0x00000000,
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1      = 0x00000001,
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2      = 0x00000002,
TMDS_REG_TEST_OUTPUTB_CNTLB_NA           = 0x00000003,
} TMDS_REG_TEST_OUTPUTB_CNTLB;

/*
 * AFMT_VBI_GSP_INDEX enum
 */

typedef enum AFMT_VBI_GSP_INDEX {
AFMT_VBI_GSP0_INDEX                      = 0x00000000,
AFMT_VBI_GSP1_INDEX                      = 0x00000001,
AFMT_VBI_GSP2_INDEX                      = 0x00000002,
AFMT_VBI_GSP3_INDEX                      = 0x00000003,
AFMT_VBI_GSP4_INDEX                      = 0x00000004,
AFMT_VBI_GSP5_INDEX                      = 0x00000005,
AFMT_VBI_GSP6_INDEX                      = 0x00000006,
AFMT_VBI_GSP7_INDEX                      = 0x00000007,
AFMT_VBI_GSP8_INDEX                      = 0x00000008,
AFMT_VBI_GSP9_INDEX                      = 0x00000009,
AFMT_VBI_GSP10_INDEX                     = 0x0000000a,
} AFMT_VBI_GSP_INDEX;

/*
 * DIG_DIGITAL_BYPASS_SEL enum
 */

typedef enum DIG_DIGITAL_BYPASS_SEL {
DIG_DIGITAL_BYPASS_SEL_BYPASS            = 0x00000000,
DIG_DIGITAL_BYPASS_SEL_36BPP             = 0x00000001,
DIG_DIGITAL_BYPASS_SEL_48BPP_LSB         = 0x00000002,
DIG_DIGITAL_BYPASS_SEL_48BPP_MSB         = 0x00000003,
DIG_DIGITAL_BYPASS_SEL_10BPP_LSB         = 0x00000004,
DIG_DIGITAL_BYPASS_SEL_12BPC_LSB         = 0x00000005,
DIG_DIGITAL_BYPASS_SEL_ALPHA             = 0x00000006,
} DIG_DIGITAL_BYPASS_SEL;

/*
 * DIG_INPUT_PIXEL_SEL enum
 */

typedef enum DIG_INPUT_PIXEL_SEL {
DIG_ALL_PIXEL                            = 0x00000000,
DIG_EVEN_PIXEL_ONLY                      = 0x00000001,
DIG_ODD_PIXEL_ONLY                       = 0x00000002,
} DIG_INPUT_PIXEL_SEL;

/*
 * DOLBY_VISION_ENABLE enum
 */

typedef enum DOLBY_VISION_ENABLE {
DOLBY_VISION_ENABLED                     = 0x00000000,
DOLBY_VISION_DISABLED                    = 0x00000001,
} DOLBY_VISION_ENABLE;

/*
 * METADATA_HUBP_SEL enum
 */

typedef enum METADATA_HUBP_SEL {
METADATA_HUBP_SEL_0                      = 0x00000000,
METADATA_HUBP_SEL_1                      = 0x00000001,
METADATA_HUBP_SEL_2                      = 0x00000002,
METADATA_HUBP_SEL_3                      = 0x00000003,
METADATA_HUBP_SEL_4                      = 0x00000004,
METADATA_HUBP_SEL_5                      = 0x00000005,
METADATA_HUBP_SEL_RESERVED               = 0x00000006,
} METADATA_HUBP_SEL;

/*
 * METADATA_STREAM_TYPE_SEL enum
 */

typedef enum METADATA_STREAM_TYPE_SEL {
METADATA_STREAM_DP                       = 0x00000000,
METADATA_STREAM_DVE                      = 0x00000001,
} METADATA_STREAM_TYPE_SEL;

/*
 * HDMI_METADATA_ENABLE enum
 */

typedef enum HDMI_METADATA_ENABLE {
HDMI_METADATA_NOT_SEND                   = 0x00000000,
HDMI_METADATA_PKT_SEND                   = 0x00000001,
} HDMI_METADATA_ENABLE;

/*
 * HDMI_PACKET_LINE_REFERENCE enum
 */

typedef enum HDMI_PACKET_LINE_REFERENCE {
HDMI_PKT_LINE_REF_VSYNC                  = 0x00000000,
HDMI_PKT_LINE_REF_OTGSOF                 = 0x00000001,
} HDMI_PACKET_LINE_REFERENCE;

/*******************************************************
 * DP_AUX Enums
 *******************************************************/

/*
 * DP_AUX_CONTROL_HPD_SEL enum
 */

typedef enum DP_AUX_CONTROL_HPD_SEL {
DP_AUX_CONTROL_HPD1_SELECTED             = 0x00000000,
DP_AUX_CONTROL_HPD2_SELECTED             = 0x00000001,
DP_AUX_CONTROL_HPD3_SELECTED             = 0x00000002,
DP_AUX_CONTROL_HPD4_SELECTED             = 0x00000003,
DP_AUX_CONTROL_HPD5_SELECTED             = 0x00000004,
DP_AUX_CONTROL_HPD6_SELECTED             = 0x00000005,
DP_AUX_CONTROL_NO_HPD_SELECTED           = 0x00000006,
} DP_AUX_CONTROL_HPD_SEL;

/*
 * DP_AUX_CONTROL_TEST_MODE enum
 */

typedef enum DP_AUX_CONTROL_TEST_MODE {
DP_AUX_CONTROL_TEST_MODE_DISABLE         = 0x00000000,
DP_AUX_CONTROL_TEST_MODE_ENABLE          = 0x00000001,
} DP_AUX_CONTROL_TEST_MODE;

/*
 * DP_AUX_SW_CONTROL_SW_GO enum
 */

typedef enum DP_AUX_SW_CONTROL_SW_GO {
DP_AUX_SW_CONTROL_SW__NOT_GO             = 0x00000000,
DP_AUX_SW_CONTROL_SW__GO                 = 0x00000001,
} DP_AUX_SW_CONTROL_SW_GO;

/*
 * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
 */

typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG      = 0x00000000,
DP_AUX_SW_CONTROL_LS_READ__TRIG          = 0x00000001,
} DP_AUX_SW_CONTROL_LS_READ_TRIG;

/*
 * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
 */

typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW  = 0x00000000,
DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW  = 0x00000001,
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC  = 0x00000002,
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS  = 0x00000003,
} DP_AUX_ARB_CONTROL_ARB_PRIORITY;

/*
 * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
 */

typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ  = 0x00000000,
DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ      = 0x00000001,
} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;

/*
 * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
 */

typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG   = 0x00000001,
} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;

/*
 * DP_AUX_INT_ACK enum
 */

typedef enum DP_AUX_INT_ACK {
DP_AUX_INT__NOT_ACK                      = 0x00000000,
DP_AUX_INT__ACK                          = 0x00000001,
} DP_AUX_INT_ACK;

/*
 * DP_AUX_LS_UPDATE_ACK enum
 */

typedef enum DP_AUX_LS_UPDATE_ACK {
DP_AUX_INT_LS_UPDATE_NOT_ACK             = 0x00000000,
DP_AUX_INT_LS_UPDATE_ACK                 = 0x00000001,
} DP_AUX_LS_UPDATE_ACK;

/*
 * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
 */

typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK  = 0x00000000,
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF  = 0x00000001,
} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;

/*
 * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
 */

typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;

/*
 * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
 */

typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;

/*
 * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
 */

typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD  = 0x00000000,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD  = 0x00000001,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD  = 0x00000002,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD  = 0x00000003,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD  = 0x00000004,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD  = 0x00000005,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD  = 0x00000006,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD  = 0x00000007,
} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;

/*
 * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
 */

typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD  = 0x00000000,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD  = 0x00000001,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD  = 0x00000002,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD  = 0x00000003,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD  = 0x00000004,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD  = 0x00000005,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD  = 0x00000006,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD  = 0x00000007,
} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;

/*
 * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
 */

typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;

/*
 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
 */

typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;

/*
 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
 */

typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;

/*
 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
 */

typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;

/*
 * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
 */

typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;

/*
 * DP_AUX_RX_TIMEOUT_LEN_MUL enum
 */

typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL {
DP_AUX_RX_TIMEOUT_LEN_NO_MUL             = 0x00000000,
DP_AUX_RX_TIMEOUT_LEN_MUL_2              = 0x00000001,
DP_AUX_RX_TIMEOUT_LEN_MUL_4              = 0x00000002,
DP_AUX_RX_TIMEOUT_LEN_MUL_8              = 0x00000003,
} DP_AUX_RX_TIMEOUT_LEN_MUL;

/*
 * DP_AUX_TX_PRECHARGE_LEN_MUL enum
 */

typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL {
DP_AUX_TX_PRECHARGE_LEN_NO_MUL           = 0x00000000,
DP_AUX_TX_PRECHARGE_LEN_MUL_2            = 0x00000001,
DP_AUX_TX_PRECHARGE_LEN_MUL_4            = 0x00000002,
DP_AUX_TX_PRECHARGE_LEN_MUL_8            = 0x00000003,
} DP_AUX_TX_PRECHARGE_LEN_MUL;

/*
 * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
 */

typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2  = 0x00000000,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4  = 0x00000001,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8  = 0x00000002,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16  = 0x00000003,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32  = 0x00000004,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64  = 0x00000005,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128  = 0x00000006,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256  = 0x00000007,
} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;

/*
 * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
 */

typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX  = 0x00000000,
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX  = 0x00000001,
} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;

/*
 * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
 */

typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;

/*
 * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
 */

typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;

/*
 * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
 */

typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0  = 0x00000000,
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64  = 0x00000001,
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128  = 0x00000002,
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256  = 0x00000003,
} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;

/*
 * DP_AUX_ERR_OCCURRED_ACK enum
 */

typedef enum DP_AUX_ERR_OCCURRED_ACK {
DP_AUX_ERR_OCCURRED__NOT_ACK             = 0x00000000,
DP_AUX_ERR_OCCURRED__ACK                 = 0x00000001,
} DP_AUX_ERR_OCCURRED_ACK;

/*
 * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
 */

typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK    = 0x00000000,
DP_AUX_POTENTIAL_ERR_REACHED__ACK        = 0x00000001,
} DP_AUX_POTENTIAL_ERR_REACHED_ACK;

/*
 * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
 */

typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK    = 0x00000001,
} DP_AUX_DEFINITE_ERR_REACHED_ACK;

/*
 * DP_AUX_RESET enum
 */

typedef enum DP_AUX_RESET {
DP_AUX_RESET_DEASSERTED                  = 0x00000000,
DP_AUX_RESET_ASSERTED                    = 0x00000001,
} DP_AUX_RESET;

/*
 * DP_AUX_RESET_DONE enum
 */

typedef enum DP_AUX_RESET_DONE {
DP_AUX_RESET_SEQUENCE_NOT_DONE           = 0x00000000,
DP_AUX_RESET_SEQUENCE_DONE               = 0x00000001,
} DP_AUX_RESET_DONE;

/*
 * DP_AUX_PHY_WAKE_PRIORITY enum
 */

typedef enum DP_AUX_PHY_WAKE_PRIORITY {
DP_AUX_PHY_WAKE_HIGH_PRIORITY            = 0x00000000,
DP_AUX_PHY_WAKE_LOW_PRIORITY             = 0x00000001,
} DP_AUX_PHY_WAKE_PRIORITY;

/*******************************************************
 * DOUT_I2C Enums
 *******************************************************/

/*
 * DOUT_I2C_CONTROL_GO enum
 */

typedef enum DOUT_I2C_CONTROL_GO {
DOUT_I2C_CONTROL_STOP_TRANSFER           = 0x00000000,
DOUT_I2C_CONTROL_START_TRANSFER          = 0x00000001,
} DOUT_I2C_CONTROL_GO;

/*
 * DOUT_I2C_CONTROL_SOFT_RESET enum
 */

typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER    = 0x00000001,
} DOUT_I2C_CONTROL_SOFT_RESET;

/*
 * DOUT_I2C_CONTROL_SEND_RESET enum
 */

typedef enum DOUT_I2C_CONTROL_SEND_RESET {
DOUT_I2C_CONTROL__NOT_SEND_RESET         = 0x00000000,
DOUT_I2C_CONTROL__SEND_RESET             = 0x00000001,
} DOUT_I2C_CONTROL_SEND_RESET;

/*
 * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum
 */

typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH {
DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9    = 0x00000000,
DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10   = 0x00000001,
} DOUT_I2C_CONTROL_SEND_RESET_LENGTH;

/*
 * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
 */

typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS     = 0x00000000,
DOUT_I2C_CONTROL_RESET_SW_STATUS         = 0x00000001,
} DOUT_I2C_CONTROL_SW_STATUS_RESET;

/*
 * DOUT_I2C_CONTROL_DDC_SELECT enum
 */

typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
DOUT_I2C_CONTROL_SELECT_DDC1             = 0x00000000,
DOUT_I2C_CONTROL_SELECT_DDC2             = 0x00000001,
DOUT_I2C_CONTROL_SELECT_DDC3             = 0x00000002,
DOUT_I2C_CONTROL_SELECT_DDC4             = 0x00000003,
DOUT_I2C_CONTROL_SELECT_DDC5             = 0x00000004,
DOUT_I2C_CONTROL_SELECT_DDC6             = 0x00000005,
DOUT_I2C_CONTROL_SELECT_DDCVGA           = 0x00000006,
} DOUT_I2C_CONTROL_DDC_SELECT;

/*
 * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
 */

typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
DOUT_I2C_CONTROL_TRANS0                  = 0x00000000,
DOUT_I2C_CONTROL_TRANS0_TRANS1           = 0x00000001,
DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2    = 0x00000002,
DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3  = 0x00000003,
} DOUT_I2C_CONTROL_TRANSACTION_COUNT;

/*
 * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
 */

typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL  = 0x00000000,
DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH    = 0x00000001,
DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
} DOUT_I2C_ARBITRATION_SW_PRIORITY;

/*
 * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
 */

typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED    = 0x00000000,
DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED   = 0x00000001,
} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;

/*
 * DOUT_I2C_ARBITRATION_ABORT_XFER enum
 */

typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER  = 0x00000001,
} DOUT_I2C_ARBITRATION_ABORT_XFER;

/*
 * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
 */

typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ    = 0x00000001,
} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;

/*
 * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
 */

typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG  = 0x00000001,
} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;

/*
 * DOUT_I2C_ACK enum
 */

typedef enum DOUT_I2C_ACK {
DOUT_I2C_NO_ACK                          = 0x00000000,
DOUT_I2C_ACK_TO_CLEAN                    = 0x00000001,
} DOUT_I2C_ACK;

/*
 * DOUT_I2C_DDC_SPEED_THRESHOLD enum
 */

typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO  = 0x00000000,
DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE  = 0x00000001,
DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE  = 0x00000002,
DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE  = 0x00000003,
} DOUT_I2C_DDC_SPEED_THRESHOLD;

/*
 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
 */

typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA     = 0x00000001,
} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;

/*
 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
 */

typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS  = 0x00000000,
DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS  = 0x00000001,
} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;

/*
 * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
 */

typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT   = 0x00000000,
DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT  = 0x00000001,
} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;

/*
 * DOUT_I2C_DDC_EDID_DETECT_STATUS enum
 */

typedef enum DOUT_I2C_DDC_EDID_DETECT_STATUS {
DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED  = 0x00000000,
DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED  = 0x00000001,
} DOUT_I2C_DDC_EDID_DETECT_STATUS;

/*
 * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
 */

typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL     = 0x00000001,
} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;

/*
 * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
 */

typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS  = 0x00000000,
DOUT_I2C_TRANSACTION_STOP_ALL_TRANS      = 0x00000001,
} DOUT_I2C_TRANSACTION_STOP_ON_NACK;

/*
 * DOUT_I2C_DATA_INDEX_WRITE enum
 */

typedef enum DOUT_I2C_DATA_INDEX_WRITE {
DOUT_I2C_DATA__NOT_INDEX_WRITE           = 0x00000000,
DOUT_I2C_DATA__INDEX_WRITE               = 0x00000001,
} DOUT_I2C_DATA_INDEX_WRITE;

/*
 * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
 */

typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION  = 0x00000001,
} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;

/*
 * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
 */

typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL  = 0x00000000,
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE  = 0x00000001,
} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;

/*******************************************************
 * DIO_MISC Enums
 *******************************************************/

/*
 * DIOMEM_PWR_FORCE_CTRL enum
 */

typedef enum DIOMEM_PWR_FORCE_CTRL {
DIOMEM_NO_FORCE_REQUEST                  = 0x00000000,
DIOMEM_FORCE_LIGHT_SLEEP_REQUEST         = 0x00000001,
DIOMEM_FORCE_DEEP_SLEEP_REQUEST          = 0x00000002,
DIOMEM_FORCE_SHUT_DOWN_REQUEST           = 0x00000003,
} DIOMEM_PWR_FORCE_CTRL;

/*
 * DIOMEM_PWR_FORCE_CTRL2 enum
 */

typedef enum DIOMEM_PWR_FORCE_CTRL2 {
DIOMEM_NO_FORCE_REQ                      = 0x00000000,
DIOMEM_FORCE_LIGHT_SLEEP_REQ             = 0x00000001,
} DIOMEM_PWR_FORCE_CTRL2;

/*
 * DIOMEM_PWR_DIS_CTRL enum
 */

typedef enum DIOMEM_PWR_DIS_CTRL {
DIOMEM_ENABLE_MEM_PWR_CTRL               = 0x00000000,
DIOMEM_DISABLE_MEM_PWR_CTRL              = 0x00000001,
} DIOMEM_PWR_DIS_CTRL;

/*
 * CLOCK_GATING_EN enum
 */

typedef enum CLOCK_GATING_EN {
CLOCK_GATING_ENABLE                      = 0x00000000,
CLOCK_GATING_DISABLE                     = 0x00000001,
} CLOCK_GATING_EN;

/*
 * DIOMEM_PWR_SEL_CTRL enum
 */

typedef enum DIOMEM_PWR_SEL_CTRL {
DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE          = 0x00000000,
DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE         = 0x00000001,
DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE        = 0x00000002,
} DIOMEM_PWR_SEL_CTRL;

/*
 * DIOMEM_PWR_SEL_CTRL2 enum
 */

typedef enum DIOMEM_PWR_SEL_CTRL2 {
DIOMEM_DYNAMIC_DEEP_SLEEP_EN             = 0x00000000,
DIOMEM_DYNAMIC_LIGHT_SLEEP_EN            = 0x00000001,
} DIOMEM_PWR_SEL_CTRL2;

/*
 * PM_ASSERT_RESET enum
 */

typedef enum PM_ASSERT_RESET {
PM_ASSERT_RESET_0                        = 0x00000000,
PM_ASSERT_RESET_1                        = 0x00000001,
} PM_ASSERT_RESET;

/*
 * DAC_MUX_SELECT enum
 */

typedef enum DAC_MUX_SELECT {
DAC_MUX_SELECT_DACA                      = 0x00000000,
DAC_MUX_SELECT_DACB                      = 0x00000001,
} DAC_MUX_SELECT;

/*
 * TMDS_MUX_SELECT enum
 */

typedef enum TMDS_MUX_SELECT {
TMDS_MUX_SELECT_B                        = 0x00000000,
TMDS_MUX_SELECT_G                        = 0x00000001,
TMDS_MUX_SELECT_R                        = 0x00000002,
TMDS_MUX_SELECT_RESERVED                 = 0x00000003,
} TMDS_MUX_SELECT;

/*
 * SOFT_RESET enum
 */

typedef enum SOFT_RESET {
SOFT_RESET_0                             = 0x00000000,
SOFT_RESET_1                             = 0x00000001,
} SOFT_RESET;

/*
 * GENERIC_STEREOSYNC_SEL enum
 */

typedef enum GENERIC_STEREOSYNC_SEL {
GENERIC_STEREOSYNC_SEL_D1                = 0x00000000,
GENERIC_STEREOSYNC_SEL_D2                = 0x00000001,
GENERIC_STEREOSYNC_SEL_D3                = 0x00000002,
GENERIC_STEREOSYNC_SEL_D4                = 0x00000003,
GENERIC_STEREOSYNC_SEL_D5                = 0x00000004,
GENERIC_STEREOSYNC_SEL_D6                = 0x00000005,
GENERIC_STEREOSYNC_SEL_RESERVED          = 0x00000006,
} GENERIC_STEREOSYNC_SEL;

/*
 * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum
 */

typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE {
DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL       = 0x00000000,
DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE       = 0x00000001,
} DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE;

/*
 * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum
 */

typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE {
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0  = 0x00000000,
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1  = 0x00000001,
} DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE;

/*******************************************************
 * DCIO Enums
 *******************************************************/

/*
 * DCIO_DC_GENERICA_SEL enum
 */

typedef enum DCIO_DC_GENERICA_SEL {
DCIO_GENERICA_SEL_DACA_STEREOSYNC        = 0x00000000,
DCIO_GENERICA_SEL_STEREOSYNC             = 0x00000001,
DCIO_GENERICA_SEL_DACA_PIXCLK            = 0x00000002,
DCIO_GENERICA_SEL_DACB_PIXCLK            = 0x00000003,
DCIO_GENERICA_SEL_DVOA_CTL3              = 0x00000004,
DCIO_GENERICA_SEL_P1_PLLCLK              = 0x00000005,
DCIO_GENERICA_SEL_P2_PLLCLK              = 0x00000006,
DCIO_GENERICA_SEL_DVOA_STEREOSYNC        = 0x00000007,
DCIO_GENERICA_SEL_DACA_FIELD_NUMBER      = 0x00000008,
DCIO_GENERICA_SEL_DACB_FIELD_NUMBER      = 0x00000009,
DCIO_GENERICA_SEL_GENERICA_DCCG          = 0x0000000a,
DCIO_GENERICA_SEL_SYNCEN                 = 0x0000000b,
DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
DCIO_GENERICA_SEL_GENERICA_DPRX          = 0x00000010,
DCIO_GENERICA_SEL_GENERICB_DPRX          = 0x00000011,
} DCIO_DC_GENERICA_SEL;

/*
 * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
 */

typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
DCIO_UNIPHYA_TEST_REFDIV_CLK             = 0x00000000,
DCIO_UNIPHYB_TEST_REFDIV_CLK             = 0x00000001,
DCIO_UNIPHYC_TEST_REFDIV_CLK             = 0x00000002,
DCIO_UNIPHYD_TEST_REFDIV_CLK             = 0x00000003,
DCIO_UNIPHYE_TEST_REFDIV_CLK             = 0x00000004,
DCIO_UNIPHYF_TEST_REFDIV_CLK             = 0x00000005,
DCIO_UNIPHYG_TEST_REFDIV_CLK             = 0x00000006,
} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;

/*
 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
 */

typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
DCIO_UNIPHYA_FBDIV_CLK                   = 0x00000000,
DCIO_UNIPHYB_FBDIV_CLK                   = 0x00000001,
DCIO_UNIPHYC_FBDIV_CLK                   = 0x00000002,
DCIO_UNIPHYD_FBDIV_CLK                   = 0x00000003,
DCIO_UNIPHYE_FBDIV_CLK                   = 0x00000004,
DCIO_UNIPHYF_FBDIV_CLK                   = 0x00000005,
DCIO_UNIPHYG_FBDIV_CLK                   = 0x00000006,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;

/*
 * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
 */

typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
DCIO_UNIPHYA_FBDIV_SSC_CLK               = 0x00000000,
DCIO_UNIPHYB_FBDIV_SSC_CLK               = 0x00000001,
DCIO_UNIPHYC_FBDIV_SSC_CLK               = 0x00000002,
DCIO_UNIPHYD_FBDIV_SSC_CLK               = 0x00000003,
DCIO_UNIPHYE_FBDIV_SSC_CLK               = 0x00000004,
DCIO_UNIPHYF_FBDIV_SSC_CLK               = 0x00000005,
DCIO_UNIPHYG_FBDIV_SSC_CLK               = 0x00000006,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;

/*
 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
 */

typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2         = 0x00000000,
DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2         = 0x00000001,
DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2         = 0x00000002,
DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2         = 0x00000003,
DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2         = 0x00000004,
DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2         = 0x00000005,
DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2         = 0x00000006,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;

/*
 * DCIO_DC_GENERICB_SEL enum
 */

typedef enum DCIO_DC_GENERICB_SEL {
DCIO_GENERICB_SEL_DACA_STEREOSYNC        = 0x00000000,
DCIO_GENERICB_SEL_STEREOSYNC             = 0x00000001,
DCIO_GENERICB_SEL_DACA_PIXCLK            = 0x00000002,
DCIO_GENERICB_SEL_DACB_PIXCLK            = 0x00000003,
DCIO_GENERICB_SEL_DVOA_CTL3              = 0x00000004,
DCIO_GENERICB_SEL_P1_PLLCLK              = 0x00000005,
DCIO_GENERICB_SEL_P2_PLLCLK              = 0x00000006,
DCIO_GENERICB_SEL_DVOA_STEREOSYNC        = 0x00000007,
DCIO_GENERICB_SEL_DACA_FIELD_NUMBER      = 0x00000008,
DCIO_GENERICB_SEL_DACB_FIELD_NUMBER      = 0x00000009,
DCIO_GENERICB_SEL_GENERICB_DCCG          = 0x0000000a,
DCIO_GENERICB_SEL_SYNCEN                 = 0x0000000b,
DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
} DCIO_DC_GENERICB_SEL;

/*
 * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
 */

typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
DCIO_HSYNCA_OUTPUT_SEL_DISABLE           = 0x00000000,
DCIO_HSYNCA_OUTPUT_SEL_PPLL1             = 0x00000001,
DCIO_HSYNCA_OUTPUT_SEL_PPLL2             = 0x00000002,
DCIO_HSYNCA_OUTPUT_SEL_RESERVED          = 0x00000003,
} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;

/*
 * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
 */

typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE        = 0x00000000,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1          = 0x00000001,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2          = 0x00000002,
DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3  = 0x00000003,
} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;

/*
 * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
 */

typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007,
} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;

/*
 * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
 */

typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
DCIO_UNIPHY_CHANNEL_NO_INVERSION         = 0x00000000,
DCIO_UNIPHY_CHANNEL_INVERTED             = 0x00000001,
} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;

/*
 * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
 */

typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW  = 0x00000000,
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW   = 0x00000001,
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED  = 0x00000002,
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED  = 0x00000003,
} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;

/*
 * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
 */

typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0      = 0x00000000,
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1      = 0x00000001,
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2      = 0x00000002,
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3      = 0x00000003,
} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;

/*
 * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
 */

typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
DCIO_VIP_MUX_EN_DVO                      = 0x00000000,
DCIO_VIP_MUX_EN_VIP                      = 0x00000001,
} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;

/*
 * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
 */

typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
DCIO_VIP_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;

/*
 * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
 */

typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
DCIO_DVO_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;

/*
 * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
 */

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE  = 0x00000000,
DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE  = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;

/*
 * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
 */

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF   = 0x00000000,
DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON    = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;

/*
 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
 */

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
DCIO_LVTMA_SYNCEN_POL_NON_INVERT         = 0x00000000,
DCIO_LVTMA_SYNCEN_POL_INVERT             = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;

/*
 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
 */

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
DCIO_LVTMA_DIGON_OFF                     = 0x00000000,
DCIO_LVTMA_DIGON_ON                      = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;

/*
 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
 */

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
DCIO_LVTMA_DIGON_POL_NON_INVERT          = 0x00000000,
DCIO_LVTMA_DIGON_POL_INVERT              = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;

/*
 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
 */

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
DCIO_LVTMA_BLON_OFF                      = 0x00000000,
DCIO_LVTMA_BLON_ON                       = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;

/*
 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
 */

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
DCIO_LVTMA_BLON_POL_NON_INVERT           = 0x00000000,
DCIO_LVTMA_BLON_POL_INVERT               = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;

/*
 * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
 */

typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON      = 0x00000000,
DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE  = 0x00000001,
} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;

/*
 * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
 */

typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
DCIO_BL_PWM_FRACTIONAL_DISABLE           = 0x00000000,
DCIO_BL_PWM_FRACTIONAL_ENABLE            = 0x00000001,
} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;

/*
 * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
 */

typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
DCIO_BL_PWM_DISABLE                      = 0x00000000,
DCIO_BL_PWM_ENABLE                       = 0x00000001,
} DCIO_BL_PWM_CNTL_BL_PWM_EN;

/*
 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
 */

typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE      = 0x00000000,
DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE       = 0x00000001,
} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;

/*
 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
 */

typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL  = 0x00000000,
DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM  = 0x00000001,
} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;

/*
 * DCIO_BL_PWM_GRP1_REG_LOCK enum
 */

typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE        = 0x00000000,
DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE         = 0x00000001,
} DCIO_BL_PWM_GRP1_REG_LOCK;

/*
 * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
 */

typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE  = 0x00000000,
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE  = 0x00000001,
} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;

/*
 * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
 */

typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1  = 0x00000000,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2  = 0x00000001,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3  = 0x00000002,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4  = 0x00000003,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5  = 0x00000004,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6  = 0x00000005,
} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;

/*
 * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
 */

typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM  = 0x00000000,
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM  = 0x00000001,
} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;

/*
 * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
 */

typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE  = 0x00000000,
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE  = 0x00000001,
} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;

/*
 * DCIO_GSL_SEL enum
 */

typedef enum DCIO_GSL_SEL {
DCIO_GSL_SEL_GROUP_0                     = 0x00000000,
DCIO_GSL_SEL_GROUP_1                     = 0x00000001,
DCIO_GSL_SEL_GROUP_2                     = 0x00000002,
} DCIO_GSL_SEL;

/*
 * DCIO_GENLK_CLK_GSL_MASK enum
 */

typedef enum DCIO_GENLK_CLK_GSL_MASK {
DCIO_GENLK_CLK_GSL_MASK_NO               = 0x00000000,
DCIO_GENLK_CLK_GSL_MASK_TIMING           = 0x00000001,
DCIO_GENLK_CLK_GSL_MASK_STEREO           = 0x00000002,
} DCIO_GENLK_CLK_GSL_MASK;

/*
 * DCIO_GENLK_VSYNC_GSL_MASK enum
 */

typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
DCIO_GENLK_VSYNC_GSL_MASK_NO             = 0x00000000,
DCIO_GENLK_VSYNC_GSL_MASK_TIMING         = 0x00000001,
DCIO_GENLK_VSYNC_GSL_MASK_STEREO         = 0x00000002,
} DCIO_GENLK_VSYNC_GSL_MASK;

/*
 * DCIO_SWAPLOCK_A_GSL_MASK enum
 */

typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
DCIO_SWAPLOCK_A_GSL_MASK_NO              = 0x00000000,
DCIO_SWAPLOCK_A_GSL_MASK_TIMING          = 0x00000001,
DCIO_SWAPLOCK_A_GSL_MASK_STEREO          = 0x00000002,
} DCIO_SWAPLOCK_A_GSL_MASK;

/*
 * DCIO_SWAPLOCK_B_GSL_MASK enum
 */

typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
DCIO_SWAPLOCK_B_GSL_MASK_NO              = 0x00000000,
DCIO_SWAPLOCK_B_GSL_MASK_TIMING          = 0x00000001,
DCIO_SWAPLOCK_B_GSL_MASK_STEREO          = 0x00000002,
} DCIO_SWAPLOCK_B_GSL_MASK;

/*
 * DCIO_DC_GPU_TIMER_START_POSITION enum
 */

typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
DCIO_GPU_TIMER_START_0_END_27            = 0x00000000,
DCIO_GPU_TIMER_START_1_END_28            = 0x00000001,
DCIO_GPU_TIMER_START_2_END_29            = 0x00000002,
DCIO_GPU_TIMER_START_3_END_30            = 0x00000003,
DCIO_GPU_TIMER_START_4_END_31            = 0x00000004,
DCIO_GPU_TIMER_START_6_END_33            = 0x00000005,
DCIO_GPU_TIMER_START_8_END_35            = 0x00000006,
DCIO_GPU_TIMER_START_10_END_37           = 0x00000007,
} DCIO_DC_GPU_TIMER_START_POSITION;

/*
 * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
 */

typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
DCIO_TEST_CLK_SEL_DISPCLK                = 0x00000000,
DCIO_TEST_CLK_SEL_GATED_DISPCLK          = 0x00000001,
DCIO_TEST_CLK_SEL_SOCCLK                 = 0x00000002,
} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;

/*
 * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
 */

typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
DCIO_DISPCLK_R_DCIO_GATE_DISABLE         = 0x00000000,
DCIO_DISPCLK_R_DCIO_GATE_ENABLE          = 0x00000001,
} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;

/*
 * DCIO_DIO_OTG_EXT_VSYNC_MUX enum
 */

typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX {
DCIO_EXT_VSYNC_MUX_SWAPLOCKB             = 0x00000000,
DCIO_EXT_VSYNC_MUX_OTG0                  = 0x00000001,
DCIO_EXT_VSYNC_MUX_OTG1                  = 0x00000002,
DCIO_EXT_VSYNC_MUX_OTG2                  = 0x00000003,
DCIO_EXT_VSYNC_MUX_OTG3                  = 0x00000004,
DCIO_EXT_VSYNC_MUX_OTG4                  = 0x00000005,
DCIO_EXT_VSYNC_MUX_OTG5                  = 0x00000006,
DCIO_EXT_VSYNC_MUX_GENERICB              = 0x00000007,
} DCIO_DIO_OTG_EXT_VSYNC_MUX;

/*
 * DCIO_DIO_EXT_VSYNC_MASK enum
 */

typedef enum DCIO_DIO_EXT_VSYNC_MASK {
DCIO_EXT_VSYNC_MASK_NONE                 = 0x00000000,
DCIO_EXT_VSYNC_MASK_PIPE0                = 0x00000001,
DCIO_EXT_VSYNC_MASK_PIPE1                = 0x00000002,
DCIO_EXT_VSYNC_MASK_PIPE2                = 0x00000003,
DCIO_EXT_VSYNC_MASK_PIPE3                = 0x00000004,
DCIO_EXT_VSYNC_MASK_PIPE4                = 0x00000005,
DCIO_EXT_VSYNC_MASK_PIPE5                = 0x00000006,
DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE       = 0x00000007,
} DCIO_DIO_EXT_VSYNC_MASK;

/*
 * DCIO_DSYNC_SOFT_RESET enum
 */

typedef enum DCIO_DSYNC_SOFT_RESET {
DCIO_DSYNC_SOFT_RESET_DEASSERT           = 0x00000000,
DCIO_DSYNC_SOFT_RESET_ASSERT             = 0x00000001,
} DCIO_DSYNC_SOFT_RESET;

/*
 * DCIO_DACA_SOFT_RESET enum
 */

typedef enum DCIO_DACA_SOFT_RESET {
DCIO_DACA_SOFT_RESET_DEASSERT            = 0x00000000,
DCIO_DACA_SOFT_RESET_ASSERT              = 0x00000001,
} DCIO_DACA_SOFT_RESET;

/*
 * DCIO_DCRXPHY_SOFT_RESET enum
 */

typedef enum DCIO_DCRXPHY_SOFT_RESET {
DCIO_DCRXPHY_SOFT_RESET_DEASSERT         = 0x00000000,
DCIO_DCRXPHY_SOFT_RESET_ASSERT           = 0x00000001,
} DCIO_DCRXPHY_SOFT_RESET;

/*
 * DCIO_DPHY_LANE_SEL enum
 */

typedef enum DCIO_DPHY_LANE_SEL {
DCIO_DPHY_LANE_SEL_LANE0                 = 0x00000000,
DCIO_DPHY_LANE_SEL_LANE1                 = 0x00000001,
DCIO_DPHY_LANE_SEL_LANE2                 = 0x00000002,
DCIO_DPHY_LANE_SEL_LANE3                 = 0x00000003,
} DCIO_DPHY_LANE_SEL;

/*
 * DCIO_DPCS_INTERRUPT_TYPE enum
 */

typedef enum DCIO_DPCS_INTERRUPT_TYPE {
DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED     = 0x00000000,
DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED     = 0x00000001,
} DCIO_DPCS_INTERRUPT_TYPE;

/*
 * DCIO_DPCS_INTERRUPT_MASK enum
 */

typedef enum DCIO_DPCS_INTERRUPT_MASK {
DCIO_DPCS_INTERRUPT_DISABLE              = 0x00000000,
DCIO_DPCS_INTERRUPT_ENABLE               = 0x00000001,
} DCIO_DPCS_INTERRUPT_MASK;

/*
 * DCIO_DC_GPU_TIMER_READ_SELECT enum
 */

typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE  = 0x00000000,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE  = 0x00000001,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP  = 0x00000002,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP  = 0x00000003,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM  = 0x00000004,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM  = 0x00000005,
} DCIO_DC_GPU_TIMER_READ_SELECT;

/*
 * DCIO_IMPCAL_STEP_DELAY enum
 */

typedef enum DCIO_IMPCAL_STEP_DELAY {
DCIO_IMPCAL_STEP_DELAY_1us               = 0x00000000,
DCIO_IMPCAL_STEP_DELAY_2us               = 0x00000001,
DCIO_IMPCAL_STEP_DELAY_3us               = 0x00000002,
DCIO_IMPCAL_STEP_DELAY_4us               = 0x00000003,
DCIO_IMPCAL_STEP_DELAY_5us               = 0x00000004,
DCIO_IMPCAL_STEP_DELAY_6us               = 0x00000005,
DCIO_IMPCAL_STEP_DELAY_7us               = 0x00000006,
DCIO_IMPCAL_STEP_DELAY_8us               = 0x00000007,
DCIO_IMPCAL_STEP_DELAY_9us               = 0x00000008,
DCIO_IMPCAL_STEP_DELAY_10us              = 0x00000009,
DCIO_IMPCAL_STEP_DELAY_11us              = 0x0000000a,
DCIO_IMPCAL_STEP_DELAY_12us              = 0x0000000b,
DCIO_IMPCAL_STEP_DELAY_13us              = 0x0000000c,
DCIO_IMPCAL_STEP_DELAY_14us              = 0x0000000d,
DCIO_IMPCAL_STEP_DELAY_15us              = 0x0000000e,
DCIO_IMPCAL_STEP_DELAY_16us              = 0x0000000f,
} DCIO_IMPCAL_STEP_DELAY;

/*
 * DCIO_UNIPHY_IMPCAL_SEL enum
 */

typedef enum DCIO_UNIPHY_IMPCAL_SEL {
DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE       = 0x00000000,
DCIO_UNIPHY_IMPCAL_SEL_BINARY            = 0x00000001,
} DCIO_UNIPHY_IMPCAL_SEL;

/*******************************************************
 * DCIO_CHIP Enums
 *******************************************************/

/*
 * DCIOCHIP_HPD_SEL enum
 */

typedef enum DCIOCHIP_HPD_SEL {
DCIOCHIP_HPD_SEL_ASYNC                   = 0x00000000,
DCIOCHIP_HPD_SEL_CLOCKED                 = 0x00000001,
} DCIOCHIP_HPD_SEL;

/*
 * DCIOCHIP_PAD_MODE enum
 */

typedef enum DCIOCHIP_PAD_MODE {
DCIOCHIP_PAD_MODE_DDC                    = 0x00000000,
DCIOCHIP_PAD_MODE_DP                     = 0x00000001,
} DCIOCHIP_PAD_MODE;

/*
 * DCIOCHIP_AUXSLAVE_PAD_MODE enum
 */

typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
DCIOCHIP_AUXSLAVE_PAD_MODE_I2C           = 0x00000000,
DCIOCHIP_AUXSLAVE_PAD_MODE_AUX           = 0x00000001,
} DCIOCHIP_AUXSLAVE_PAD_MODE;

/*
 * DCIOCHIP_INVERT enum
 */

typedef enum DCIOCHIP_INVERT {
DCIOCHIP_POL_NON_INVERT                  = 0x00000000,
DCIOCHIP_POL_INVERT                      = 0x00000001,
} DCIOCHIP_INVERT;

/*
 * DCIOCHIP_PD_EN enum
 */

typedef enum DCIOCHIP_PD_EN {
DCIOCHIP_PD_EN_NOTALLOW                  = 0x00000000,
DCIOCHIP_PD_EN_ALLOW                     = 0x00000001,
} DCIOCHIP_PD_EN;

/*
 * DCIOCHIP_GPIO_MASK_EN enum
 */

typedef enum DCIOCHIP_GPIO_MASK_EN {
DCIOCHIP_GPIO_MASK_EN_HARDWARE           = 0x00000000,
DCIOCHIP_GPIO_MASK_EN_SOFTWARE           = 0x00000001,
} DCIOCHIP_GPIO_MASK_EN;

/*
 * DCIOCHIP_MASK enum
 */

typedef enum DCIOCHIP_MASK {
DCIOCHIP_MASK_DISABLE                    = 0x00000000,
DCIOCHIP_MASK_ENABLE                     = 0x00000001,
} DCIOCHIP_MASK;

/*
 * DCIOCHIP_GPIO_I2C_MASK enum
 */

typedef enum DCIOCHIP_GPIO_I2C_MASK {
DCIOCHIP_GPIO_I2C_MASK_DISABLE           = 0x00000000,
DCIOCHIP_GPIO_I2C_MASK_ENABLE            = 0x00000001,
} DCIOCHIP_GPIO_I2C_MASK;

/*
 * DCIOCHIP_GPIO_I2C_DRIVE enum
 */

typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
DCIOCHIP_GPIO_I2C_DRIVE_LOW              = 0x00000000,
DCIOCHIP_GPIO_I2C_DRIVE_HIGH             = 0x00000001,
} DCIOCHIP_GPIO_I2C_DRIVE;

/*
 * DCIOCHIP_GPIO_I2C_EN enum
 */

typedef enum DCIOCHIP_GPIO_I2C_EN {
DCIOCHIP_GPIO_I2C_DISABLE                = 0x00000000,
DCIOCHIP_GPIO_I2C_ENABLE                 = 0x00000001,
} DCIOCHIP_GPIO_I2C_EN;

/*
 * DCIOCHIP_MASK_4BIT enum
 */

typedef enum DCIOCHIP_MASK_4BIT {
DCIOCHIP_MASK_4BIT_DISABLE               = 0x00000000,
DCIOCHIP_MASK_4BIT_ENABLE                = 0x0000000f,
} DCIOCHIP_MASK_4BIT;

/*
 * DCIOCHIP_ENABLE_4BIT enum
 */

typedef enum DCIOCHIP_ENABLE_4BIT {
DCIOCHIP_4BIT_DISABLE                    = 0x00000000,
DCIOCHIP_4BIT_ENABLE                     = 0x0000000f,
} DCIOCHIP_ENABLE_4BIT;

/*
 * DCIOCHIP_MASK_5BIT enum
 */

typedef enum DCIOCHIP_MASK_5BIT {
DCIOCHIP_MASIK_5BIT_DISABLE              = 0x00000000,
DCIOCHIP_MASIK_5BIT_ENABLE               = 0x0000001f,
} DCIOCHIP_MASK_5BIT;

/*
 * DCIOCHIP_ENABLE_5BIT enum
 */

typedef enum DCIOCHIP_ENABLE_5BIT {
DCIOCHIP_5BIT_DISABLE                    = 0x00000000,
DCIOCHIP_5BIT_ENABLE                     = 0x0000001f,
} DCIOCHIP_ENABLE_5BIT;

/*
 * DCIOCHIP_MASK_2BIT enum
 */

typedef enum DCIOCHIP_MASK_2BIT {
DCIOCHIP_MASK_2BIT_DISABLE               = 0x00000000,
DCIOCHIP_MASK_2BIT_ENABLE                = 0x00000003,
} DCIOCHIP_MASK_2BIT;

/*
 * DCIOCHIP_ENABLE_2BIT enum
 */

typedef enum DCIOCHIP_ENABLE_2BIT {
DCIOCHIP_2BIT_DISABLE                    = 0x00000000,
DCIOCHIP_2BIT_ENABLE                     = 0x00000003,
} DCIOCHIP_ENABLE_2BIT;

/*
 * DCIOCHIP_REF_27_SRC_SEL enum
 */

typedef enum DCIOCHIP_REF_27_SRC_SEL {
DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER     = 0x00000000,
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER  = 0x00000001,
DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS      = 0x00000002,
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS  = 0x00000003,
} DCIOCHIP_REF_27_SRC_SEL;

/*
 * DCIOCHIP_DVO_VREFPON enum
 */

typedef enum DCIOCHIP_DVO_VREFPON {
DCIOCHIP_DVO_VREFPON_DISABLE             = 0x00000000,
DCIOCHIP_DVO_VREFPON_ENABLE              = 0x00000001,
} DCIOCHIP_DVO_VREFPON;

/*
 * DCIOCHIP_DVO_VREFSEL enum
 */

typedef enum DCIOCHIP_DVO_VREFSEL {
DCIOCHIP_DVO_VREFSEL_ONCHIP              = 0x00000000,
DCIOCHIP_DVO_VREFSEL_EXTERNAL            = 0x00000001,
} DCIOCHIP_DVO_VREFSEL;

/*
 * DCIOCHIP_SPDIF1_IMODE enum
 */

typedef enum DCIOCHIP_SPDIF1_IMODE {
DCIOCHIP_SPDIF1_IMODE_OE_A               = 0x00000000,
DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO          = 0x00000001,
} DCIOCHIP_SPDIF1_IMODE;

/*
 * DCIOCHIP_AUX_FALLSLEWSEL enum
 */

typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
DCIOCHIP_AUX_FALLSLEWSEL_LOW             = 0x00000000,
DCIOCHIP_AUX_FALLSLEWSEL_HIGH0           = 0x00000001,
DCIOCHIP_AUX_FALLSLEWSEL_HIGH1           = 0x00000002,
DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH       = 0x00000003,
} DCIOCHIP_AUX_FALLSLEWSEL;

/*
 * DCIOCHIP_I2C_FALLSLEWSEL enum
 */

typedef enum DCIOCHIP_I2C_FALLSLEWSEL {
DCIOCHIP_I2C_FALLSLEWSEL_00              = 0x00000000,
DCIOCHIP_I2C_FALLSLEWSEL_01              = 0x00000001,
DCIOCHIP_I2C_FALLSLEWSEL_10              = 0x00000002,
DCIOCHIP_I2C_FALLSLEWSEL_11              = 0x00000003,
} DCIOCHIP_I2C_FALLSLEWSEL;

/*
 * DCIOCHIP_AUX_SPIKESEL enum
 */

typedef enum DCIOCHIP_AUX_SPIKESEL {
DCIOCHIP_AUX_SPIKESEL_50NS               = 0x00000000,
DCIOCHIP_AUX_SPIKESEL_10NS               = 0x00000001,
} DCIOCHIP_AUX_SPIKESEL;

/*
 * DCIOCHIP_AUX_CSEL0P9 enum
 */

typedef enum DCIOCHIP_AUX_CSEL0P9 {
DCIOCHIP_AUX_CSEL_DEC1P0                 = 0x00000000,
DCIOCHIP_AUX_CSEL_DEC0P9                 = 0x00000001,
} DCIOCHIP_AUX_CSEL0P9;

/*
 * DCIOCHIP_AUX_CSEL1P1 enum
 */

typedef enum DCIOCHIP_AUX_CSEL1P1 {
DCIOCHIP_AUX_CSEL_INC1P0                 = 0x00000000,
DCIOCHIP_AUX_CSEL_INC1P1                 = 0x00000001,
} DCIOCHIP_AUX_CSEL1P1;

/*
 * DCIOCHIP_AUX_RSEL0P9 enum
 */

typedef enum DCIOCHIP_AUX_RSEL0P9 {
DCIOCHIP_AUX_RSEL_DEC1P0                 = 0x00000000,
DCIOCHIP_AUX_RSEL_DEC0P9                 = 0x00000001,
} DCIOCHIP_AUX_RSEL0P9;

/*
 * DCIOCHIP_AUX_RSEL1P1 enum
 */

typedef enum DCIOCHIP_AUX_RSEL1P1 {
DCIOCHIP_AUX_RSEL_INC1P0                 = 0x00000000,
DCIOCHIP_AUX_RSEL_INC1P1                 = 0x00000001,
} DCIOCHIP_AUX_RSEL1P1;

/*
 * DCIOCHIP_AUX_HYS_TUNE enum
 */

typedef enum DCIOCHIP_AUX_HYS_TUNE {
DCIOCHIP_AUX_HYS_TUNE_0                  = 0x00000000,
DCIOCHIP_AUX_HYS_TUNE_1                  = 0x00000001,
DCIOCHIP_AUX_HYS_TUNE_2                  = 0x00000002,
DCIOCHIP_AUX_HYS_TUNE_3                  = 0x00000003,
} DCIOCHIP_AUX_HYS_TUNE;

/*
 * DCIOCHIP_AUX_VOD_TUNE enum
 */

typedef enum DCIOCHIP_AUX_VOD_TUNE {
DCIOCHIP_AUX_VOD_TUNE_0                  = 0x00000000,
DCIOCHIP_AUX_VOD_TUNE_1                  = 0x00000001,
DCIOCHIP_AUX_VOD_TUNE_2                  = 0x00000002,
DCIOCHIP_AUX_VOD_TUNE_3                  = 0x00000003,
} DCIOCHIP_AUX_VOD_TUNE;

/*
 * DCIOCHIP_I2C_VPH_1V2_EN enum
 */

typedef enum DCIOCHIP_I2C_VPH_1V2_EN {
DCIOCHIP_I2C_VPH_1V2_EN_0                = 0x00000000,
DCIOCHIP_I2C_VPH_1V2_EN_1                = 0x00000001,
} DCIOCHIP_I2C_VPH_1V2_EN;

/*
 * DCIOCHIP_I2C_COMPSEL enum
 */

typedef enum DCIOCHIP_I2C_COMPSEL {
DCIOCHIP_I2C_REC_SCHMIT                  = 0x00000000,
DCIOCHIP_I2C_REC_COMPARATOR              = 0x00000001,
} DCIOCHIP_I2C_COMPSEL;

/*
 * DCIOCHIP_AUX_ALL_PWR_OK enum
 */

typedef enum DCIOCHIP_AUX_ALL_PWR_OK {
DCIOCHIP_AUX_ALL_PWR_OK_0                = 0x00000000,
DCIOCHIP_AUX_ALL_PWR_OK_1                = 0x00000001,
} DCIOCHIP_AUX_ALL_PWR_OK;

/*
 * DCIOCHIP_I2C_RECEIVER_SEL enum
 */

typedef enum DCIOCHIP_I2C_RECEIVER_SEL {
DCIOCHIP_I2C_RECEIVER_SEL_0              = 0x00000000,
DCIOCHIP_I2C_RECEIVER_SEL_1              = 0x00000001,
DCIOCHIP_I2C_RECEIVER_SEL_2              = 0x00000002,
DCIOCHIP_I2C_RECEIVER_SEL_3              = 0x00000003,
} DCIOCHIP_I2C_RECEIVER_SEL;

/*
 * DCIOCHIP_AUX_RECEIVER_SEL enum
 */

typedef enum DCIOCHIP_AUX_RECEIVER_SEL {
DCIOCHIP_AUX_RECEIVER_SEL_0              = 0x00000000,
DCIOCHIP_AUX_RECEIVER_SEL_1              = 0x00000001,
DCIOCHIP_AUX_RECEIVER_SEL_2              = 0x00000002,
DCIOCHIP_AUX_RECEIVER_SEL_3              = 0x00000003,
} DCIOCHIP_AUX_RECEIVER_SEL;

/*******************************************************
 * AZCONTROLLER Enums
 *******************************************************/

/*
 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
 */

typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE   = 0x00000000,
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE    = 0x00000001,
} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;

/*
 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
 */

typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED  = 0x00000000,
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED  = 0x00000001,
} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;

/*
 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
 */

typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET  = 0x00000000,
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET  = 0x00000001,
} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;

/*
 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
 */

typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED  = 0x00000000,
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED  = 0x00000001,
} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;

/*
 * AZ_GLOBAL_CAPABILITIES enum
 */

typedef enum AZ_GLOBAL_CAPABILITIES {
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED  = 0x00000000,
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED  = 0x00000001,
} AZ_GLOBAL_CAPABILITIES;

/*
 * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
 */

typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE   = 0x00000000,
ACCEPT_UNSOLICITED_RESPONSE_ENABLE       = 0x00000001,
} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;

/*
 * GLOBAL_CONTROL_FLUSH_CONTROL enum
 */

typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
FLUSH_CONTROL_FLUSH_NOT_STARTED          = 0x00000000,
FLUSH_CONTROL_FLUSH_STARTED              = 0x00000001,
} GLOBAL_CONTROL_FLUSH_CONTROL;

/*
 * GLOBAL_CONTROL_CONTROLLER_RESET enum
 */

typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET  = 0x00000000,
CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET  = 0x00000001,
} GLOBAL_CONTROL_CONTROLLER_RESET;

/*
 * AZ_STATE_CHANGE_STATUS enum
 */

typedef enum AZ_STATE_CHANGE_STATUS {
AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT  = 0x00000000,
AZ_STATE_CHANGE_STATUS_CODEC_PRESENT     = 0x00000001,
} AZ_STATE_CHANGE_STATUS;

/*
 * GLOBAL_STATUS_FLUSH_STATUS enum
 */

typedef enum GLOBAL_STATUS_FLUSH_STATUS {
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED  = 0x00000000,
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED   = 0x00000001,
} GLOBAL_STATUS_FLUSH_STATUS;

/*
 * STREAM_0_SYNCHRONIZATION enum
 */

typedef enum STREAM_0_SYNCHRONIZATION {
STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
STREAM_0_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
} STREAM_0_SYNCHRONIZATION;

/*
 * STREAM_1_SYNCHRONIZATION enum
 */

typedef enum STREAM_1_SYNCHRONIZATION {
STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
STREAM_1_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
} STREAM_1_SYNCHRONIZATION;

/*
 * STREAM_2_SYNCHRONIZATION enum
 */

typedef enum STREAM_2_SYNCHRONIZATION {
STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
STREAM_2_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
} STREAM_2_SYNCHRONIZATION;

/*
 * STREAM_3_SYNCHRONIZATION enum
 */

typedef enum STREAM_3_SYNCHRONIZATION {
STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
STREAM_3_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
} STREAM_3_SYNCHRONIZATION;

/*
 * STREAM_4_SYNCHRONIZATION enum
 */

typedef enum STREAM_4_SYNCHRONIZATION {
STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
STREAM_4_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
} STREAM_4_SYNCHRONIZATION;

/*
 * STREAM_5_SYNCHRONIZATION enum
 */

typedef enum STREAM_5_SYNCHRONIZATION {
STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
STREAM_5_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
} STREAM_5_SYNCHRONIZATION;

/*
 * STREAM_6_SYNCHRONIZATION enum
 */

typedef enum STREAM_6_SYNCHRONIZATION {
STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_6_SYNCHRONIZATION;

/*
 * STREAM_7_SYNCHRONIZATION enum
 */

typedef enum STREAM_7_SYNCHRONIZATION {
STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_7_SYNCHRONIZATION;

/*
 * STREAM_8_SYNCHRONIZATION enum
 */

typedef enum STREAM_8_SYNCHRONIZATION {
STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_8_SYNCHRONIZATION;

/*
 * STREAM_9_SYNCHRONIZATION enum
 */

typedef enum STREAM_9_SYNCHRONIZATION {
STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_9_SYNCHRONIZATION;

/*
 * STREAM_10_SYNCHRONIZATION enum
 */

typedef enum STREAM_10_SYNCHRONIZATION {
STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_10_SYNCHRONIZATION;

/*
 * STREAM_11_SYNCHRONIZATION enum
 */

typedef enum STREAM_11_SYNCHRONIZATION {
STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_11_SYNCHRONIZATION;

/*
 * STREAM_12_SYNCHRONIZATION enum
 */

typedef enum STREAM_12_SYNCHRONIZATION {
STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_12_SYNCHRONIZATION;

/*
 * STREAM_13_SYNCHRONIZATION enum
 */

typedef enum STREAM_13_SYNCHRONIZATION {
STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_13_SYNCHRONIZATION;

/*
 * STREAM_14_SYNCHRONIZATION enum
 */

typedef enum STREAM_14_SYNCHRONIZATION {
STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_14_SYNCHRONIZATION;

/*
 * STREAM_15_SYNCHRONIZATION enum
 */

typedef enum STREAM_15_SYNCHRONIZATION {
STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
} STREAM_15_SYNCHRONIZATION;

/*
 * CORB_READ_POINTER_RESET enum
 */

typedef enum CORB_READ_POINTER_RESET {
CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET  = 0x00000000,
CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET  = 0x00000001,
} CORB_READ_POINTER_RESET;

/*
 * AZ_CORB_SIZE enum
 */

typedef enum AZ_CORB_SIZE {
AZ_CORB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
AZ_CORB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
AZ_CORB_SIZE_256ENTRIES                  = 0x00000002,
AZ_CORB_SIZE_RESERVED                    = 0x00000003,
} AZ_CORB_SIZE;

/*
 * AZ_RIRB_WRITE_POINTER_RESET enum
 */

typedef enum AZ_RIRB_WRITE_POINTER_RESET {
AZ_RIRB_WRITE_POINTER_NOT_RESET          = 0x00000000,
AZ_RIRB_WRITE_POINTER_DO_RESET           = 0x00000001,
} AZ_RIRB_WRITE_POINTER_RESET;

/*
 * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
 */

typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;

/*
 * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
 */

typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;

/*
 * AZ_RIRB_SIZE enum
 */

typedef enum AZ_RIRB_SIZE {
AZ_RIRB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
AZ_RIRB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
AZ_RIRB_SIZE_256ENTRIES                  = 0x00000002,
AZ_RIRB_SIZE_UNDEFINED                   = 0x00000003,
} AZ_RIRB_SIZE;

/*
 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
 */

typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID  = 0x00000000,
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID  = 0x00000001,
} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;

/*
 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
 */

typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY  = 0x00000000,
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY  = 0x00000001,
} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;

/*
 * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
 */

typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE  = 0x00000000,
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE  = 0x00000001,
} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;

/*******************************************************
 * AZENDPOINT Enums
 *******************************************************/

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;

/*
 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
 */

typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE  = 0x00000000,
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE  = 0x00000001,
} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;

/*
 * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum
 */

typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE {
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0  = 0x00000000,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1  = 0x00000001,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2  = 0x00000002,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3  = 0x00000003,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4  = 0x00000004,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5  = 0x00000005,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6  = 0x00000006,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7  = 0x00000007,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8  = 0x00000008,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9  = 0x00000009,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10  = 0x0000000a,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11  = 0x0000000b,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12  = 0x0000000c,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13  = 0x0000000d,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14  = 0x0000000e,
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15  = 0x0000000f,
} AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE;

/*******************************************************
 * AZF0CONTROLLER Enums
 *******************************************************/

/*
 * MEM_PWR_FORCE_CTRL enum
 */

typedef enum MEM_PWR_FORCE_CTRL {
NO_FORCE_REQUEST                         = 0x00000000,
FORCE_LIGHT_SLEEP_REQUEST                = 0x00000001,
FORCE_DEEP_SLEEP_REQUEST                 = 0x00000002,
FORCE_SHUT_DOWN_REQUEST                  = 0x00000003,
} MEM_PWR_FORCE_CTRL;

/*
 * MEM_PWR_FORCE_CTRL2 enum
 */

typedef enum MEM_PWR_FORCE_CTRL2 {
NO_FORCE_REQ                             = 0x00000000,
FORCE_LIGHT_SLEEP_REQ                    = 0x00000001,
} MEM_PWR_FORCE_CTRL2;

/*
 * MEM_PWR_DIS_CTRL enum
 */

typedef enum MEM_PWR_DIS_CTRL {
ENABLE_MEM_PWR_CTRL                      = 0x00000000,
DISABLE_MEM_PWR_CTRL                     = 0x00000001,
} MEM_PWR_DIS_CTRL;

/*
 * MEM_PWR_SEL_CTRL enum
 */

typedef enum MEM_PWR_SEL_CTRL {
DYNAMIC_SHUT_DOWN_ENABLE                 = 0x00000000,
DYNAMIC_DEEP_SLEEP_ENABLE                = 0x00000001,
DYNAMIC_LIGHT_SLEEP_ENABLE               = 0x00000002,
} MEM_PWR_SEL_CTRL;

/*
 * MEM_PWR_SEL_CTRL2 enum
 */

typedef enum MEM_PWR_SEL_CTRL2 {
DYNAMIC_DEEP_SLEEP_EN                    = 0x00000000,
DYNAMIC_LIGHT_SLEEP_EN                   = 0x00000001,
} MEM_PWR_SEL_CTRL2;

/*
 * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
 */

typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET  = 0x00000000,
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC  = 0x00000001,
} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;

/*******************************************************
 * AZF0ROOT Enums
 *******************************************************/

/*
 * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
 */

typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL  = 0x00000000,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6  = 0x00000001,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5  = 0x00000002,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4  = 0x00000003,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3  = 0x00000004,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2  = 0x00000005,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1  = 0x00000006,
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0  = 0x00000007,
} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;

/*
 * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
 */

typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL  = 0x00000000,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6  = 0x00000001,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5  = 0x00000002,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4  = 0x00000003,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3  = 0x00000004,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2  = 0x00000005,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1  = 0x00000006,
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0  = 0x00000007,
} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;

/*******************************************************
 * AZINPUTENDPOINT Enums
 *******************************************************/

/*
 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;

/*
 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;

/*
 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;

/*
 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;

/*
 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;

/*
 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;

/*
 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;

/*
 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
 */

typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;

/*******************************************************
 * AZROOT Enums
 *******************************************************/

/*
 * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
 */

typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET  = 0x00000000,
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET  = 0x00000001,
} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;

/*******************************************************
 * AZF0STREAM Enums
 *******************************************************/

/*
 * AZ_LATENCY_COUNTER_CONTROL enum
 */

typedef enum AZ_LATENCY_COUNTER_CONTROL {
AZ_LATENCY_COUNTER_NO_RESET              = 0x00000000,
AZ_LATENCY_COUNTER_RESET_DONE            = 0x00000001,
} AZ_LATENCY_COUNTER_CONTROL;

/*******************************************************
 * AZSTREAM Enums
 *******************************************************/

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
 */

typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED  = 0x00000008,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED  = 0x00000009,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED  = 0x0000000a,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED  = 0x0000000b,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED  = 0x0000000c,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED  = 0x0000000d,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED  = 0x0000000e,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED  = 0x0000000f,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;

/*******************************************************
 * AZF0ENDPOINT Enums
 *******************************************************/

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;

/*
 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
 */

typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;

/*
 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;

/*
 * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;

/*
 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY  = 0x00000000,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY  = 0x00000001,
} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;

/*******************************************************
 * AZF0INPUTENDPOINT Enums
 *******************************************************/

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;

/*
 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;

/*
 * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
 */

typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY  = 0x00000000,
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY  = 0x00000001,
} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;

/*******************************************************
 * DSCC Enums
 *******************************************************/

/*
 * DSCC_ICH_RESET_ENUM enum
 */

typedef enum DSCC_ICH_RESET_ENUM {
DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET     = 0x00000001,
DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET     = 0x00000002,
DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET     = 0x00000004,
DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET     = 0x00000008,
} DSCC_ICH_RESET_ENUM;

/*
 * DSCC_DSC_VERSION_MINOR_ENUM enum
 */

typedef enum DSCC_DSC_VERSION_MINOR_ENUM {
DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION  = 0x00000001,
DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION  = 0x00000002,
} DSCC_DSC_VERSION_MINOR_ENUM;

/*
 * DSCC_DSC_VERSION_MAJOR_ENUM enum
 */

typedef enum DSCC_DSC_VERSION_MAJOR_ENUM {
DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION  = 0x00000001,
} DSCC_DSC_VERSION_MAJOR_ENUM;

/*
 * DSCC_LINEBUF_DEPTH_ENUM enum
 */

typedef enum DSCC_LINEBUF_DEPTH_ENUM {
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT  = 0x00000008,
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT  = 0x00000009,
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT  = 0x0000000a,
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT  = 0x0000000b,
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT  = 0x0000000c,
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT  = 0x0000000d,
} DSCC_LINEBUF_DEPTH_ENUM;

/*
 * DSCC_BITS_PER_COMPONENT_ENUM enum
 */

typedef enum DSCC_BITS_PER_COMPONENT_ENUM {
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT  = 0x00000008,
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT  = 0x0000000a,
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT  = 0x0000000c,
} DSCC_BITS_PER_COMPONENT_ENUM;

/*
 * DSCC_ENABLE_ENUM enum
 */

typedef enum DSCC_ENABLE_ENUM {
DSCC_ENABLE_ENUM_DISABLED                = 0x00000000,
DSCC_ENABLE_ENUM_ENABLED                 = 0x00000001,
} DSCC_ENABLE_ENUM;

/*
 * DSCC_MEM_PWR_FORCE_ENUM enum
 */

typedef enum DSCC_MEM_PWR_FORCE_ENUM {
DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST  = 0x00000000,
DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST  = 0x00000001,
DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST  = 0x00000002,
DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST  = 0x00000003,
} DSCC_MEM_PWR_FORCE_ENUM;

/*
 * POWER_STATE_ENUM enum
 */

typedef enum POWER_STATE_ENUM {
POWER_STATE_ENUM_ON                      = 0x00000000,
POWER_STATE_ENUM_LS                      = 0x00000001,
POWER_STATE_ENUM_DS                      = 0x00000002,
POWER_STATE_ENUM_SD                      = 0x00000003,
} POWER_STATE_ENUM;

/*
 * DSCC_MEM_PWR_DIS_ENUM enum
 */

typedef enum DSCC_MEM_PWR_DIS_ENUM {
DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN         = 0x00000000,
DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS        = 0x00000001,
} DSCC_MEM_PWR_DIS_ENUM;

/*******************************************************
 * DSCCIF Enums
 *******************************************************/

/*
 * DSCCIF_ENABLE_ENUM enum
 */

typedef enum DSCCIF_ENABLE_ENUM {
DSCCIF_ENABLE_ENUM_DISABLED              = 0x00000000,
DSCCIF_ENABLE_ENUM_ENABLED               = 0x00000001,
} DSCCIF_ENABLE_ENUM;

/*
 * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum
 */

typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM {
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB       = 0x00000000,
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444  = 0x00000001,
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422  = 0x00000002,
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422  = 0x00000003,
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420  = 0x00000004,
} DSCCIF_INPUT_PIXEL_FORMAT_ENUM;

/*
 * DSCCIF_BITS_PER_COMPONENT_ENUM enum
 */

typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM {
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT  = 0x00000008,
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT  = 0x0000000a,
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT  = 0x0000000c,
} DSCCIF_BITS_PER_COMPONENT_ENUM;

/*******************************************************
 * DSC_TOP Enums
 *******************************************************/

/*
 * ENABLE_ENUM enum
 */

typedef enum ENABLE_ENUM {
ENABLE_ENUM_DISABLED                     = 0x00000000,
ENABLE_ENUM_ENABLED                      = 0x00000001,
} ENABLE_ENUM;

/*
 * CLOCK_GATING_DISABLE_ENUM enum
 */

typedef enum CLOCK_GATING_DISABLE_ENUM {
CLOCK_GATING_DISABLE_ENUM_ENABLED        = 0x00000000,
CLOCK_GATING_DISABLE_ENUM_DISABLED       = 0x00000001,
} CLOCK_GATING_DISABLE_ENUM;

/*
 * TEST_CLOCK_MUX_SELECT_ENUM enum
 */

typedef enum TEST_CLOCK_MUX_SELECT_ENUM {
TEST_CLOCK_MUX_SELECT_DISPCLK_P          = 0x00000000,
TEST_CLOCK_MUX_SELECT_DISPCLK_G          = 0x00000001,
TEST_CLOCK_MUX_SELECT_DISPCLK_R          = 0x00000002,
TEST_CLOCK_MUX_SELECT_DSCCLK_P           = 0x00000003,
TEST_CLOCK_MUX_SELECT_DSCCLK_G           = 0x00000004,
TEST_CLOCK_MUX_SELECT_DSCCLK_R           = 0x00000005,
} TEST_CLOCK_MUX_SELECT_ENUM;

/*******************************************************
 * CNV Enums
 *******************************************************/

/*
 * WB_ENABLE_ENUM enum
 */

typedef enum WB_ENABLE_ENUM {
WB_EN_DISABLE                            = 0x00000000,
WB_EN_ENABLE                             = 0x00000001,
} WB_ENABLE_ENUM;

/*
 * WB_CLK_GATE_DIS_ENUM enum
 */

typedef enum WB_CLK_GATE_DIS_ENUM {
WB_CLK_GATE_ENABLE                       = 0x00000000,
WB_CLK_GATE_DISABLE                      = 0x00000001,
} WB_CLK_GATE_DIS_ENUM;

/*
 * WB_MEM_PWR_DIS_ENUM enum
 */

typedef enum WB_MEM_PWR_DIS_ENUM {
WB_MEM_PWR_ENABLE                        = 0x00000000,
WB_MEM_PWR_DISABLE                       = 0x00000001,
} WB_MEM_PWR_DIS_ENUM;

/*
 * WB_TEST_CLK_SEL_ENUM enum
 */

typedef enum WB_TEST_CLK_SEL_ENUM {
WB_TEST_CLK_SEL_REG                      = 0x00000000,
WB_TEST_CLK_SEL_WB                       = 0x00000001,
WB_TEST_CLK_SEL_WBSCL                    = 0x00000002,
WB_TEST_CLK_SEL_PERM                     = 0x00000003,
} WB_TEST_CLK_SEL_ENUM;

/*
 * WBSCL_LB_MEM_PWR_MODE_SEL_ENUM enum
 */

typedef enum WBSCL_LB_MEM_PWR_MODE_SEL_ENUM {
WBSCL_LB_MEM_PWR_MODE_SEL_SD             = 0x00000000,
WBSCL_LB_MEM_PWR_MODE_SEL_DS             = 0x00000001,
WBSCL_LB_MEM_PWR_MODE_SEL_LS             = 0x00000002,
WBSCL_LB_MEM_PWR_MODE_SEL_ON             = 0x00000003,
} WBSCL_LB_MEM_PWR_MODE_SEL_ENUM;

/*
 * WBSCL_LB_MEM_PWR_FORCE_ENUM enum
 */

typedef enum WBSCL_LB_MEM_PWR_FORCE_ENUM {
WBSCL_LB_MEM_PWR_FORCE_NO                = 0x00000000,
WBSCL_LB_MEM_PWR_FORCE_LS                = 0x00000001,
WBSCL_LB_MEM_PWR_FORCE_DS                = 0x00000002,
WBSCL_LB_MEM_PWR_FORCE_SD                = 0x00000003,
} WBSCL_LB_MEM_PWR_FORCE_ENUM;

/*
 * WBSCL_MEM_PWR_STATE_ENUM enum
 */

typedef enum WBSCL_MEM_PWR_STATE_ENUM {
WBSCL_MEM_PWR_STATE_ON                   = 0x00000000,
WBSCL_MEM_PWR_STATE_LS                   = 0x00000001,
WBSCL_MEM_PWR_STATE_DS                   = 0x00000002,
WBSCL_MEM_PWR_STATE_SD                   = 0x00000003,
} WBSCL_MEM_PWR_STATE_ENUM;

/*
 * WBSCL_LUT_MEM_PWR_STATE_ENUM enum
 */

typedef enum WBSCL_LUT_MEM_PWR_STATE_ENUM {
WBSCL_LUT_MEM_PWR_STATE_ON               = 0x00000000,
WBSCL_LUT_MEM_PWR_STATE_LS               = 0x00000001,
WBSCL_LUT_MEM_PWR_STATE_RESERVED2        = 0x00000002,
WBSCL_LUT_MEM_PWR_STATE_RESERVED3        = 0x00000003,
} WBSCL_LUT_MEM_PWR_STATE_ENUM;

/*
 * WB_RAM_PW_SAVE_MODE_ENUM enum
 */

typedef enum WB_RAM_PW_SAVE_MODE_ENUM {
WB_RAM_PW_SAVE_MODE_LS                   = 0x00000000,
WB_RAM_PW_SAVE_MODE_SD                   = 0x00000001,
} WB_RAM_PW_SAVE_MODE_ENUM;

/*
 * CNV_OUT_BPC_ENUM enum
 */

typedef enum CNV_OUT_BPC_ENUM {
CNV_OUT_BPC_8BPC                         = 0x00000000,
CNV_OUT_BPC_10BPC                        = 0x00000001,
} CNV_OUT_BPC_ENUM;

/*
 * CNV_FRAME_CAPTURE_RATE_ENUM enum
 */

typedef enum CNV_FRAME_CAPTURE_RATE_ENUM {
CNV_FRAME_CAPTURE_RATE_0                 = 0x00000000,
CNV_FRAME_CAPTURE_RATE_1                 = 0x00000001,
CNV_FRAME_CAPTURE_RATE_2                 = 0x00000002,
CNV_FRAME_CAPTURE_RATE_3                 = 0x00000003,
} CNV_FRAME_CAPTURE_RATE_ENUM;

/*
 * CNV_WINDOW_CROP_EN_ENUM enum
 */

typedef enum CNV_WINDOW_CROP_EN_ENUM {
CNV_WINDOW_CROP_DISABLE                  = 0x00000000,
CNV_WINDOW_CROP_ENABLE                   = 0x00000001,
} CNV_WINDOW_CROP_EN_ENUM;

/*
 * CNV_INTERLACED_MODE_ENUM enum
 */

typedef enum CNV_INTERLACED_MODE_ENUM {
CNV_INTERLACED_MODE_PROGRESSIVE          = 0x00000000,
CNV_INTERLACED_MODE_INTERLACED           = 0x00000001,
} CNV_INTERLACED_MODE_ENUM;

/*
 * CNV_EYE_SELECT enum
 */

typedef enum CNV_EYE_SELECT {
STEREO_DISABLED                          = 0x00000000,
LEFT_EYE                                 = 0x00000001,
RIGHT_EYE                                = 0x00000002,
BOTH_EYE                                 = 0x00000003,
} CNV_EYE_SELECT;

/*
 * CNV_STEREO_TYPE_ENUM enum
 */

typedef enum CNV_STEREO_TYPE_ENUM {
CNV_STEREO_TYPE_RESERVED0                = 0x00000000,
CNV_STEREO_TYPE_RESERVED1                = 0x00000001,
CNV_STEREO_TYPE_RESERVED2                = 0x00000002,
CNV_STEREO_TYPE_FRAME_SEQUENTIAL         = 0x00000003,
} CNV_STEREO_TYPE_ENUM;

/*
 * CNV_STEREO_POLARITY_ENUM enum
 */

typedef enum CNV_STEREO_POLARITY_ENUM {
CNV_STEREO_POLARITY_LEFT                 = 0x00000000,
CNV_STEREO_POLARITY_RIGHT                = 0x00000001,
} CNV_STEREO_POLARITY_ENUM;

/*
 * CNV_INTERLACED_FIELD_ORDER_ENUM enum
 */

typedef enum CNV_INTERLACED_FIELD_ORDER_ENUM {
CNV_INTERLACED_FIELD_ORDER_TOP           = 0x00000000,
CNV_INTERLACED_FIELD_ORDER_BOT           = 0x00000001,
} CNV_INTERLACED_FIELD_ORDER_ENUM;

/*
 * CNV_STEREO_SPLIT_ENUM enum
 */

typedef enum CNV_STEREO_SPLIT_ENUM {
CNV_STEREO_SPLIT_DISABLE                 = 0x00000000,
CNV_STEREO_SPLIT_ENABLE                  = 0x00000001,
} CNV_STEREO_SPLIT_ENUM;

/*
 * CNV_NEW_CONTENT_ENUM enum
 */

typedef enum CNV_NEW_CONTENT_ENUM {
CNV_NEW_CONTENT_NEG                      = 0x00000000,
CNV_NEW_CONTENT_POS                      = 0x00000001,
} CNV_NEW_CONTENT_ENUM;

/*
 * CNV_FRAME_CAPTURE_EN_ENUM enum
 */

typedef enum CNV_FRAME_CAPTURE_EN_ENUM {
CNV_FRAME_CAPTURE_DISABLE                = 0x00000000,
CNV_FRAME_CAPTURE_ENABLE                 = 0x00000001,
} CNV_FRAME_CAPTURE_EN_ENUM;

/*
 * CNV_UPDATE_PENDING_ENUM enum
 */

typedef enum CNV_UPDATE_PENDING_ENUM {
CNV_UPDATE_PENDING_NEG                   = 0x00000000,
CNV_UPDATE_PENDING_POS                   = 0x00000001,
} CNV_UPDATE_PENDING_ENUM;

/*
 * CNV_UPDATE_LOCK_ENUM enum
 */

typedef enum CNV_UPDATE_LOCK_ENUM {
CNV_UPDATE_UNLOCK                        = 0x00000000,
CNV_UPDATE_LOCK                          = 0x00000001,
} CNV_UPDATE_LOCK_ENUM;

/*
 * CNV_CSC_BYPASS_ENUM enum
 */

typedef enum CNV_CSC_BYPASS_ENUM {
CNV_CSC_BYPASS_NEG                       = 0x00000000,
CNV_CSC_BYPASS_POS                       = 0x00000001,
} CNV_CSC_BYPASS_ENUM;

/*
 * CNV_TEST_CRC_EN_ENUM enum
 */

typedef enum CNV_TEST_CRC_EN_ENUM {
CNV_TEST_CRC_DISABLE                     = 0x00000000,
CNV_TEST_CRC_ENABLE                      = 0x00000001,
} CNV_TEST_CRC_EN_ENUM;

/*
 * CNV_TEST_CRC_CONT_EN_ENUM enum
 */

typedef enum CNV_TEST_CRC_CONT_EN_ENUM {
CNV_TEST_CRC_CONT_DISABLE                = 0x00000000,
CNV_TEST_CRC_CONT_ENABLE                 = 0x00000001,
} CNV_TEST_CRC_CONT_EN_ENUM;

/*
 * WB_SOFT_RESET_ENUM enum
 */

typedef enum WB_SOFT_RESET_ENUM {
WB_SOFT_RESET_NEG                        = 0x00000000,
WB_SOFT_RESET_POS                        = 0x00000001,
} WB_SOFT_RESET_ENUM;

/*
 * DWB_GMC_WARM_UP_ENABLE_ENUM enum
 */

typedef enum DWB_GMC_WARM_UP_ENABLE_ENUM {
DWB_GMC_WARM_UP_DISABLE                  = 0x00000000,
DWB_GMC_WARM_UP_ENABLE                   = 0x00000001,
} DWB_GMC_WARM_UP_ENABLE_ENUM;

/*
 * DWB_MODE_WARMUP_ENUM enum
 */

typedef enum DWB_MODE_WARMUP_ENUM {
DWB_MODE_WARMUP_420                      = 0x00000000,
DWB_MODE_WARMUP_444                      = 0x00000001,
} DWB_MODE_WARMUP_ENUM;

/*
 * DWB_DATA_DEPTH_WARMUP_ENUM enum
 */

typedef enum DWB_DATA_DEPTH_WARMUP_ENUM {
DWB_DATA_DEPTH_WARMUP_8BPC               = 0x00000000,
DWB_DATA_DEPTH_WARMUP_10BPC              = 0x00000001,
} DWB_DATA_DEPTH_WARMUP_ENUM;

/*******************************************************
 * WBSCL Enums
 *******************************************************/

/*
 * WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM enum
 */

typedef enum WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM {
WBSCL_COEF_RAM_TAP_PAIR_IDX0             = 0x00000000,
WBSCL_COEF_RAM_TAP_PAIR_IDX1             = 0x00000001,
WBSCL_COEF_RAM_TAP_PAIR_IDX2             = 0x00000002,
WBSCL_COEF_RAM_TAP_PAIR_IDX3             = 0x00000003,
WBSCL_COEF_RAM_TAP_PAIR_IDX4             = 0x00000004,
WBSCL_COEF_RAM_TAP_PAIR_IDX5             = 0x00000005,
} WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM;

/*
 * WBSCL_COEF_RAM_PHASE_ENUM enum
 */

typedef enum WBSCL_COEF_RAM_PHASE_ENUM {
WBSCL_COEF_RAM_PHASE0                    = 0x00000000,
WBSCL_COEF_RAM_PHASE1                    = 0x00000001,
WBSCL_COEF_RAM_PHASE2                    = 0x00000002,
WBSCL_COEF_RAM_PHASE3                    = 0x00000003,
WBSCL_COEF_RAM_PHASE4                    = 0x00000004,
WBSCL_COEF_RAM_PHASE5                    = 0x00000005,
WBSCL_COEF_RAM_PHASE6                    = 0x00000006,
WBSCL_COEF_RAM_PHASE7                    = 0x00000007,
WBSCL_COEF_RAM_PHASE8                    = 0x00000008,
} WBSCL_COEF_RAM_PHASE_ENUM;

/*
 * WBSCL_COEF_RAM_FILTER_TYPE_ENUM enum
 */

typedef enum WBSCL_COEF_RAM_FILTER_TYPE_ENUM {
WBSCL_COEF_RAM_FILTER_TYPE_VL            = 0x00000000,
WBSCL_COEF_RAM_FILTER_TYPE_VC            = 0x00000001,
WBSCL_COEF_RAM_FILTER_TYPE_HL            = 0x00000002,
WBSCL_COEF_RAM_FILTER_TYPE_HC            = 0x00000003,
} WBSCL_COEF_RAM_FILTER_TYPE_ENUM;

/*
 * WBSCL_COEF_FILTER_TYPE_SEL enum
 */

typedef enum WBSCL_COEF_FILTER_TYPE_SEL {
WBSCL_COEF_LUMA_VERT_FILTER              = 0x00000000,
WBSCL_COEF_CHROMA_VERT_FILTER            = 0x00000001,
WBSCL_COEF_LUMA_HORZ_FILTER              = 0x00000002,
WBSCL_COEF_CHROMA_HORZ_FILTER            = 0x00000003,
} WBSCL_COEF_FILTER_TYPE_SEL;

/*
 * WBSCL_MODE_SEL enum
 */

typedef enum WBSCL_MODE_SEL {
WBSCL_MODE_SCALING_444_BYPASS            = 0x00000000,
WBSCL_MODE_SCALING_444_RGB_ENABLE        = 0x00000001,
WBSCL_MODE_SCALING_444_YCBCR_ENABLE      = 0x00000002,
WBSCL_MODE_SCALING_YCBCR_ENABLE          = 0x00000003,
} WBSCL_MODE_SEL;

/*
 * WBSCL_PIXEL_DEPTH enum
 */

typedef enum WBSCL_PIXEL_DEPTH {
PIXEL_DEPTH_8BPC                         = 0x00000000,
PIXEL_DEPTH_10BPC                        = 0x00000001,
} WBSCL_PIXEL_DEPTH;

/*
 * WBSCL_COEF_RAM_SEL_ENUM enum
 */

typedef enum WBSCL_COEF_RAM_SEL_ENUM {
WBSCL_COEF_RAM_SEL_0                     = 0x00000000,
WBSCL_COEF_RAM_SEL_1                     = 0x00000001,
} WBSCL_COEF_RAM_SEL_ENUM;

/*
 * WBSCL_COEF_RAM_RD_SEL_ENUM enum
 */

typedef enum WBSCL_COEF_RAM_RD_SEL_ENUM {
WBSCL_COEF_RAM_RD_SEL_0                  = 0x00000000,
WBSCL_COEF_RAM_RD_SEL_1                  = 0x00000001,
} WBSCL_COEF_RAM_RD_SEL_ENUM;

/*
 * WBSCL_COEF_RAM_TAP_COEF_EN_ENUM enum
 */

typedef enum WBSCL_COEF_RAM_TAP_COEF_EN_ENUM {
WBSCL_COEF_RAM_TAP_COEF_DISABLE          = 0x00000000,
WBSCL_COEF_RAM_TAP_COEF_ENABLE           = 0x00000001,
} WBSCL_COEF_RAM_TAP_COEF_EN_ENUM;

/*
 * WBSCL_NUM_OF_TAPS_ENUM enum
 */

typedef enum WBSCL_NUM_OF_TAPS_ENUM {
WBSCL_NUM_OF_TAPS0                       = 0x00000000,
WBSCL_NUM_OF_TAPS1                       = 0x00000001,
WBSCL_NUM_OF_TAPS2                       = 0x00000002,
WBSCL_NUM_OF_TAPS3                       = 0x00000003,
WBSCL_NUM_OF_TAPS4                       = 0x00000004,
WBSCL_NUM_OF_TAPS5                       = 0x00000005,
WBSCL_NUM_OF_TAPS6                       = 0x00000006,
WBSCL_NUM_OF_TAPS7                       = 0x00000007,
WBSCL_NUM_OF_TAPS8                       = 0x00000008,
WBSCL_NUM_OF_TAPS9                       = 0x00000009,
WBSCL_NUM_OF_TAPS10                      = 0x0000000a,
WBSCL_NUM_OF_TAPS11                      = 0x0000000b,
} WBSCL_NUM_OF_TAPS_ENUM;

/*
 * WBSCL_STATUS_ACK_ENUM enum
 */

typedef enum WBSCL_STATUS_ACK_ENUM {
WBSCL_STATUS_ACK_NCLR                    = 0x00000000,
WBSCL_STATUS_ACK_CLR                     = 0x00000001,
} WBSCL_STATUS_ACK_ENUM;

/*
 * WBSCL_STATUS_MASK_ENUM enum
 */

typedef enum WBSCL_STATUS_MASK_ENUM {
WBSCL_STATUS_MASK_DISABLE                = 0x00000000,
WBSCL_STATUS_MASK_ENABLE                 = 0x00000001,
} WBSCL_STATUS_MASK_ENUM;

/*
 * WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM enum
 */

typedef enum WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM {
WBSCL_DATA_OVERFLOW_INT_TYPE_REG         = 0x00000000,
WBSCL_DATA_OVERFLOW_INT_TYPE_HW          = 0x00000001,
} WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM;

/*
 * WBSCL_HOST_CONFLICT_INT_TYPE_ENUM enum
 */

typedef enum WBSCL_HOST_CONFLICT_INT_TYPE_ENUM {
WBSCL_HOST_CONFLICT_INT_TYPE_REG         = 0x00000000,
WBSCL_HOST_CONFLICT_INT_TYPE_HW          = 0x00000001,
} WBSCL_HOST_CONFLICT_INT_TYPE_ENUM;

/*
 * WBSCL_TEST_CRC_EN_ENUM enum
 */

typedef enum WBSCL_TEST_CRC_EN_ENUM {
WBSCL_TEST_CRC_DISABLE                   = 0x00000000,
WBSCL_TEST_CRC_ENABLE                    = 0x00000001,
} WBSCL_TEST_CRC_EN_ENUM;

/*
 * WBSCL_TEST_CRC_CONT_EN_ENUM enum
 */

typedef enum WBSCL_TEST_CRC_CONT_EN_ENUM {
WBSCL_TEST_CRC_CONT_DISABLE              = 0x00000000,
WBSCL_TEST_CRC_CONT_ENABLE               = 0x00000001,
} WBSCL_TEST_CRC_CONT_EN_ENUM;

/*
 * WBSCL_TEST_CRC_MASK_ENUM enum
 */

typedef enum WBSCL_TEST_CRC_MASK_ENUM {
WBSCL_TEST_CRC_MASKED                    = 0x00000000,
WBSCL_TEST_CRC_UNMASKED                  = 0x00000001,
} WBSCL_TEST_CRC_MASK_ENUM;

/*
 * WBSCL_BACKPRESSURE_CNT_EN_ENUM enum
 */

typedef enum WBSCL_BACKPRESSURE_CNT_EN_ENUM {
WBSCL_BACKPRESSURE_CNT_DISABLE           = 0x00000000,
WBSCL_BACKPRESSURE_CNT_ENABLE            = 0x00000001,
} WBSCL_BACKPRESSURE_CNT_EN_ENUM;

/*
 * WBSCL_OUTSIDE_PIX_STRATEGY_ENUM enum
 */

typedef enum WBSCL_OUTSIDE_PIX_STRATEGY_ENUM {
WBSCL_OUTSIDE_PIX_STRATEGY_BLACK         = 0x00000000,
WBSCL_OUTSIDE_PIX_STRATEGY_EDGE          = 0x00000001,
} WBSCL_OUTSIDE_PIX_STRATEGY_ENUM;

/*******************************************************
 * DPCSRX Enums
 *******************************************************/

/*
 * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
 */

typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
DPCSRX_BPHY_PCS_RX0_CLK                  = 0x00000000,
DPCSRX_BPHY_PCS_RX1_CLK                  = 0x00000001,
DPCSRX_BPHY_PCS_RX2_CLK                  = 0x00000002,
DPCSRX_BPHY_PCS_RX3_CLK                  = 0x00000003,
} DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL;

/*******************************************************
 * DPCSTX Enums
 *******************************************************/

/*
 * DPCSTX_DVI_LINK_MODE enum
 */

typedef enum DPCSTX_DVI_LINK_MODE {
DPCSTX_DVI_LINK_MODE_NORMAL              = 0x00000000,
DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER    = 0x00000001,
DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER    = 0x00000002,
} DPCSTX_DVI_LINK_MODE;

/*******************************************************
 * RDPCSTX Enums
 *******************************************************/

/*
 * RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET enum
 */

typedef enum RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET {
RDPCS_CBUS_SOFT_RESET_DISABLE            = 0x00000000,
RDPCS_CBUS_SOFT_RESET_ENABLE             = 0x00000001,
} RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET;

/*
 * RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET enum
 */

typedef enum RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET {
RDPCS_SRAM_SRAM_RESET_DISABLE            = 0x00000000,
} RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET;

/*
 * RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN enum
 */

typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN {
RDPCS_TX_FIFO_LANE_DISABLE               = 0x00000000,
RDPCS_TX_FIFO_LANE_ENABLE                = 0x00000001,
} RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN;

/*
 * RDPCSTX_CNTL_RDPCS_TX_FIFO_EN enum
 */

typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_EN {
RDPCS_TX_FIFO_DISABLE                    = 0x00000000,
RDPCS_TX_FIFO_ENABLE                     = 0x00000001,
} RDPCSTX_CNTL_RDPCS_TX_FIFO_EN;

/*
 * RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET enum
 */

typedef enum RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET {
RDPCS_TX_SOFT_RESET_DISABLE              = 0x00000000,
RDPCS_TX_SOFT_RESET_ENABLE               = 0x00000001,
} RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET;

/*
 * RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN enum
 */

typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN {
RDPCS_EXT_REFCLK_DISABLE                 = 0x00000000,
RDPCS_EXT_REFCLK_ENABLE                  = 0x00000001,
} RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN;

/*
 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN enum
 */

typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN {
RDPCS_EXT_REFCLK_EN_DISABLE              = 0x00000000,
RDPCS_EXT_REFCLK_EN_ENABLE               = 0x00000001,
} RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN;

/*
 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS enum
 */

typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS {
RDPCS_SYMCLK_DIV2_GATE_ENABLE            = 0x00000000,
RDPCS_SYMCLK_DIV2_GATE_DISABLE           = 0x00000001,
} RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS;

/*
 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN enum
 */

typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN {
RDPCS_SYMCLK_DIV2_DISABLE                = 0x00000000,
RDPCS_SYMCLK_DIV2_ENABLE                 = 0x00000001,
} RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN;

/*
 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON enum
 */

typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON {
RDPCS_SYMCLK_DIV2_CLOCK_OFF              = 0x00000000,
RDPCS_SYMCLK_DIV2_CLOCK_ON               = 0x00000001,
} RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON;

/*
 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum
 */

typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS {
RDPCS_SRAMCLK_GATE_ENABLE                = 0x00000000,
RDPCS_SRAMCLK_GATE_DISABLE               = 0x00000001,
} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS;

/*
 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum
 */

typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN {
RDPCS_SRAMCLK_DISABLE                    = 0x00000000,
RDPCS_SRAMCLK_ENABLE                     = 0x00000001,
} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN;

/*
 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS enum
 */

typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS {
RDPCS_SRAMCLK_NOT_BYPASS                 = 0x00000000,
RDPCS_SRAMCLK_BYPASS                     = 0x00000001,
} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS;

/*
 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum
 */

typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON {
RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF           = 0x00000000,
RDPCS_SYMCLK_SRAMCLK_CLOCK_ON            = 0x00000001,
} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON;

/*
 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum
 */

typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE {
RDPCS_DPALT_DISABLE_TOGGLE_ENABLE        = 0x00000000,
RDPCS_DPALT_DISABLE_TOGGLE_DISABLE       = 0x00000001,
} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE;

/*
 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum
 */

typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE {
RDPCS_DPALT_4LANE_TOGGLE_2LANE           = 0x00000000,
RDPCS_DPALT_4LANE_TOGGLE_4LANE           = 0x00000001,
} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE;

/*
 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum
 */

typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK {
RDPCS_REG_FIFO_ERROR_MASK_DISABLE        = 0x00000000,
RDPCS_REG_FIFO_ERROR_MASK_ENABLE         = 0x00000001,
} RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK;

/*
 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum
 */

typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK {
RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE  = 0x00000000,
RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE   = 0x00000001,
} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK;

/*
 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum
 */

typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK {
RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE    = 0x00000000,
RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE     = 0x00000001,
} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK;

/*
 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK enum
 */

typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK {
RDPCS_TX_FIFO_ERROR_MASK_DISABLE         = 0x00000000,
RDPCS_TX_FIFO_ERROR_MASK_ENABLE          = 0x00000001,
} RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK;

/*
 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum
 */

typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE {
RDPCS_MEM_PWR_NO_FORCE                   = 0x00000000,
RDPCS_MEM_PWR_LIGHT_SLEEP                = 0x00000001,
RDPCS_MEM_PWR_DEEP_SLEEP                 = 0x00000002,
RDPCS_MEM_PWR_SHUT_DOWN                  = 0x00000003,
} RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE;

/*
 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum
 */

typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE {
RDPCS_MEM_PWR_PWR_STATE_ON               = 0x00000000,
RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP      = 0x00000001,
RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP       = 0x00000002,
RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN        = 0x00000003,
} RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE;

/*
 * RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF enum
 */

typedef enum RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF {
RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY  = 0x00000000,
RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD   = 0x00000001,
RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3        = 0x00000002,
RDPCS_MEM_POWER_CTRL_POFF_FOR_SD         = 0x00000003,
} RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF;

/*
 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum
 */

typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE {
RDPCS_PHY_REF_RANGE_0                    = 0x00000000,
RDPCS_PHY_REF_RANGE_1                    = 0x00000001,
RDPCS_PHY_REF_RANGE_2                    = 0x00000002,
RDPCS_PHY_REF_RANGE_3                    = 0x00000003,
RDPCS_PHY_REF_RANGE_4                    = 0x00000004,
RDPCS_PHY_REF_RANGE_5                    = 0x00000005,
RDPCS_PHY_REF_RANGE_6                    = 0x00000006,
RDPCS_PHY_REF_RANGE_7                    = 0x00000007,
} RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE;

/*
 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum
 */

typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL {
RDPCS_PHY_CR_PARA_SEL_JTAG               = 0x00000000,
RDPCS_PHY_CR_PARA_SEL_CR                 = 0x00000001,
} RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL;

/*
 *