Symbol: _d

function parameter

Defined...

• drivers/virtio/virtio.c:14:28-14:43: static ssize_t device_show(struct device *_d,
• drivers/virtio/virtio.c:22:28-22:43: static ssize_t vendor_show(struct device *_d,
• drivers/virtio/virtio.c:30:28-30:43: static ssize_t status_show(struct device *_d,
• drivers/virtio/virtio.c:38:30-38:45: static ssize_t modalias_show(struct device *_d,
• drivers/virtio/virtio.c:47:30-47:45: static ssize_t features_show(struct device *_d,
• drivers/virtio/virtio.c:235:29-235:44: static int virtio_dev_probe(struct device *_d)
• drivers/virtio/virtio.c:323:31-323:46: static void virtio_dev_remove(struct device *_d)
• drivers/virtio/virtio_mmio.c:560:37-560:52: static void virtio_mmio_release_dev(struct device *_d)
• drivers/virtio/virtio_pci_common.c:500:36-500:51: static void virtio_pci_release_dev(struct device *_d)
• drivers/virtio/virtio_vdpa.c:345:37-345:52: static void virtio_vdpa_release_dev(struct device *_d)

variable

Defined...

• arch/x86/kernel/cpu/aperfmperf.c:348:6-348:6: if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt))
• drivers/block/nbd.c:1469:7-1469:7: if (check_shl_overflow(arg, config->blksize_bits, &bytesize))
• drivers/cxl/core/port.c:890:2-890:28: struct cxl_dport *dport, *_d;
• drivers/dma/dmaengine.c:758:2-758:30: struct dma_device *device, *_d;
• drivers/dma/dmaengine.c:814:2-814:25: struct dma_device *d, *_d;
• drivers/dma/dmaengine.c:933:2-933:30: struct dma_device *device, *_d;
• drivers/dma/dmaengine.c:972:2-972:30: struct dma_device *device, *_d;
• drivers/dma/ep93xx_dma.c:1209:2-1209:33: struct ep93xx_dma_desc *desc, *_d;
• drivers/dma/pch_dma.c:363:2-363:30: struct pch_dma_desc *desc, *_d;
• drivers/dma/pch_dma.c:446:2-446:30: struct pch_dma_desc *desc, *_d;
• drivers/dma/pch_dma.c:531:2-531:30: struct pch_dma_desc *desc, *_d;
• drivers/dma/pch_dma.c:655:2-655:30: struct pch_dma_desc *desc, *_d;
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1129:2-1129:2: PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1214:3-1214:3: PUSH_NVSQ(push, NV05F, 0x012c, 0);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1215:3-1215:3: PUSH_NVSQ(push, NV05F, 0x0134, head);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1216:3-1216:3: PUSH_NVSQ(push, NV05F, 0x0100, 0);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1217:3-1217:3: PUSH_NVSQ(push, NV05F, 0x0130, 0);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:46:2-46:2: PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:59:2-59:2: PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:63:2-63:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:76:2-76:2: PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:80:2-80:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:83:3-83:3: PUSH_MTHD(push, NV507C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:90:3-90:3: PUSH_MTHD(push, NV507C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:98:2-98:2: PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:100:2-100:2: PUSH_MTHD(push, NV507C, SURFACE_SET_SIZE(0),
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:129:2-129:2: PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:143:2-143:2: PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:169:2-169:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:182:2-182:2: PUSH_MTHD(push, NV507C, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:206:2-206:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:219:2-219:2: PUSH_MTHD(push, NV507C, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:37:2-37:2: PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:41:2-41:2: PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:44:3-44:3: PUSH_MTHD(push, NV827C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:51:3-51:3: PUSH_MTHD(push, NV827C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:59:2-59:2: PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:37:2-37:2: PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:42:2-42:2: PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:44:2-44:2: PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:74:2-74:2: PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:77:2-77:2: PUSH_MTHD(push, NV907C, SET_OUTPUT_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:80:2-80:2: PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:93:2-93:2: PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:102:2-102:2: PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, asyw->xlut.handle);
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:165:2-165:2: PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:179:2-179:2: PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:43:3-43:3: PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:49:2-49:2: PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] |
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:90:2-90:2: PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:95:2-95:2: PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:97:2-97:2: PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:139:2-139:2: PUSH_MTHD(push, NV507D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:44:3-44:3: PUSH_MTHD(push, NVC37D, WINDOW_SET_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:61:3-61:3: PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:67:2-67:2: PUSH_MTHD(push, NVC37D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS],
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:69:2-69:2: PUSH_MTHD(push, NVC37D, UPDATE, 0x00000001 |
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:74:3-74:3: PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:137:2-137:2: PUSH_MTHD(push, NVC37D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:140:3-140:3: PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:149:3-149:3: PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec57d.c:39:2-39:2: PUSH_MTHD(push, NVC57D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
• drivers/gpu/drm/nouveau/dispnv50/corec57d.c:42:3-42:3: PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec57d.c:50:3-50:3: PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:64:3-64:3: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:65:3-65:3: PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:67:3-67:3: PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:68:3-68:3: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:84:2-84:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:44:3-44:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:45:3-45:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:47:3-47:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:48:3-48:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:63:2-63:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:40:3-40:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:41:3-41:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:43:3-43:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:44:3-44:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/dac507d.c:44:2-44:2: PUSH_MTHD(push, NV507D, DAC_SET_CONTROL(or), ctrl,
• drivers/gpu/drm/nouveau/dispnv50/dac907d.c:38:2-38:2: PUSH_MTHD(push, NV907D, DAC_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/disp.c:184:2-184:2: PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:39:2-39:2: PUSH_MTHD(push, NV507D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:58:2-58:2: PUSH_MTHD(push, NV507D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:90:2-90:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:118:2-118:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:132:2-132:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:149:2-149:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:198:2-198:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTEXT_DMA_ISO(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:212:2-212:2: PUSH_MTHD(push, NV507D, HEAD_SET_OFFSET(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:215:2-215:2: PUSH_MTHD(push, NV507D, HEAD_SET_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:233:2-233:2: PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:288:2-288:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:303:2-303:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:356:2-356:2: PUSH_MTHD(push, NV507D, HEAD_SET_PIXEL_CLOCK(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:365:2-365:2: PUSH_MTHD(push, NV507D, HEAD_SET_OVERSCAN_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:393:2-393:2: PUSH_MTHD(push, NV507D, HEAD_SET_DEFAULT_BASE_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:410:2-410:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:416:2-416:2: PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:420:2-420:2: PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:39:2-39:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:44:2-44:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:58:2-58:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:69:2-69:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:83:2-83:2: PUSH_MTHD(push, NV827D, HEAD_SET_OFFSET(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:86:2-86:2: PUSH_MTHD(push, NV827D, HEAD_SET_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:104:2-104:2: PUSH_MTHD(push, NV827D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:120:2-120:2: PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:123:2-123:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:137:2-137:2: PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:145:2-145:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:46:2-46:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:67:2-67:2: PUSH_MTHD(push, NV907D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:87:2-87:2: PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:120:2-120:2: PUSH_MTHD(push, NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:148:2-148:2: PUSH_MTHD(push, NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:162:2-162:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:167:2-167:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:181:2-181:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:191:2-191:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:205:2-205:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMAS_ISO(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:219:2-219:2: PUSH_MTHD(push, NV907D, HEAD_SET_OFFSET(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:222:2-222:2: PUSH_MTHD(push, NV907D, HEAD_SET_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:240:2-240:2: PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_POINT_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:256:2-256:2: PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:259:2-259:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:273:2-273:2: PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:281:2-281:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:333:2-333:2: PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:358:2-358:2: PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:363:2-363:2: PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:388:2-388:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:394:2-394:2: PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:398:2-398:2: PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:40:2-40:2: PUSH_MTHD(push, NV917D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:73:2-73:2: PUSH_MTHD(push, NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:88:2-88:2: PUSH_MTHD(push, NV917D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:98:2-98:2: PUSH_MTHD(push, NV917D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:55:2-55:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:74:2-74:2: PUSH_MTHD(push, NVC37D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:95:2-95:2: PUSH_MTHD(push, NVC37D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:114:2-114:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:118:2-118:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:132:2-132:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:148:2-148:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:149:2-149:2: PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:171:2-171:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:185:2-185:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:220:2-220:2: PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:237:2-237:2: PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:238:2-238:2: PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:240:2-240:2: PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:243:2-243:2: PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:247:2-247:2: PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:264:2-264:2: PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:268:2-268:2: PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:55:2-55:2: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:76:2-76:2: PUSH_MTHD(push, NVC57D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:93:2-93:2: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_OLUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:107:2-107:2: PUSH_MTHD(push, NVC57D, HEAD_SET_OLUT_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:199:2-199:2: PUSH_MTHD(push, NVC57D, HEAD_SET_RASTER_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:216:2-216:2: PUSH_NVSQ(push, NVC57D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:217:2-217:2: PUSH_NVSQ(push, NVC57D, 0x2008 + (i * 0x400), m->interlace);
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:219:2-219:2: PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:222:2-222:2: PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:226:2-226:2: PUSH_MTHD(push, NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:44:2-44:2: PUSH_MTHD(push, NV507E, SET_POINT_IN,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:66:2-66:2: PUSH_MTHD(push, NV507E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:70:2-70:2: PUSH_MTHD(push, NV507E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:72:2-72:2: PUSH_MTHD(push, NV507E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:75:2-75:2: PUSH_MTHD(push, NV507E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:77:2-77:2: PUSH_MTHD(push, NV507E, SURFACE_SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:41:2-41:2: PUSH_MTHD(push, NV827E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:45:2-45:2: PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:47:2-47:2: PUSH_MTHD(push, NV827E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:50:2-50:2: PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:52:2-52:2: PUSH_MTHD(push, NV827E, SURFACE_SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:38:2-38:2: PUSH_MTHD(push, NV907E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:42:2-42:2: PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:44:2-44:2: PUSH_MTHD(push, NV907E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:47:2-47:2: PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:49:2-49:2: PUSH_MTHD(push, NV907E, SURFACE_SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/pior507d.c:45:2-45:2: PUSH_MTHD(push, NV507D, PIOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/sor507d.c:45:2-45:2: PUSH_MTHD(push, NV507D, SOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/sor907d.c:41:2-41:2: PUSH_MTHD(push, NV907D, SOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/sorc37d.c:38:2-38:2: PUSH_MTHD(push, NVC37D, SOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c:40:2-40:2: PUSH_MTHD(push, NVC37B, UPDATE, 0x00000001 |
• drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c:55:2-55:2: PUSH_MTHD(push, NVC37B, SET_POINT_OUT(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:49:2-49:2: PUSH_MTHD(push, NVC37E, SET_CSC_RED2RED, asyw->csc.matrix, 12);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:62:2-62:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_INPUT_LUT, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:75:2-75:2: PUSH_MTHD(push, NVC37E, SET_CONTROL_INPUT_LUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:104:2-104:2: PUSH_MTHD(push, NVC37E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:149:2-149:2: PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:153:2-153:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:166:2-166:2: PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:171:2-171:2: PUSH_MTHD(push, NVC37E, SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:193:2-193:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:194:2-194:2: PUSH_MTHD(push, NVC37E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:196:2-196:2: PUSH_MTHD(push, NVC37E, SET_POINT_IN(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:200:2-200:2: PUSH_MTHD(push, NVC37E, SET_SIZE_IN,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:204:2-204:2: PUSH_MTHD(push, NVC37E, SET_SIZE_OUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:219:2-219:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:232:2-232:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, asyw->ntfy.handle,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:249:2-249:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:262:2-262:2: PUSH_MTHD(push, NVC37E, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:278:2-278:2: PUSH_MTHD(push, NVC37E, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS] << 1 |
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:282:2-282:2: PUSH_MTHD(push, NVC37E, UPDATE, 0x00000001 |
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:43:2-43:2: PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:48:2-48:2: PUSH_MTHD(push, NVC57E, SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:66:2-66:2: PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:67:2-67:2: PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:69:2-69:2: PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:73:2-73:2: PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:77:2-77:2: PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:97:2-97:2: PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, identity, ARRAY_SIZE(identity));
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:110:2-110:2: PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, asyw->csc.matrix, 12);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:123:2-123:2: PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ILUT, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:136:2-136:2: PUSH_MTHD(push, NVC57E, SET_ILUT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:38:2-38:2: PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:43:2-43:2: PUSH_MTHD(push, NVC57E, SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:60:2-60:2: PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:61:2-61:2: PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:63:2-63:2: PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:67:2-67:2: PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:71:2-71:2: PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:62:2-62:2: PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma,
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:73:3-73:3: PUSH_MTHD(push, NV039, OFFSET_IN, src_offset,
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:86:3-86:3: PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000);
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:106:2-106:2: PUSH_MTHD(push, NV039, SET_OBJECT, handle);
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:107:2-107:2: PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_NOTIFIES, chan->drm->ntfy.handle);
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:63:4-63:4: PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:80:4-80:4: PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:85:4-85:4: PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:102:4-102:4: PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:106:3-106:3: PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:112:3-112:3: PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset),
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:126:3-126:3: PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000);
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:146:2-146:2: PUSH_MTHD(push, NV5039, SET_OBJECT, handle);
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:147:2-147:2: PUSH_MTHD(push, NV5039, SET_CONTEXT_DMA_NOTIFY, chan->drm->ntfy.handle,
• drivers/gpu/drm/nouveau/nouveau_bo74c1.c:47:2-47:2: PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->num_pages << PAGE_SHIFT,
• drivers/gpu/drm/nouveau/nouveau_bo85b5.c:58:3-58:3: PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset),
• drivers/gpu/drm/nouveau/nouveau_bo85b5.c:66:3-66:3: PUSH_NVSQ(push, NV85B5, 0x0300, 0x00000110);
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:56:3-56:3: PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER,
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:61:3-61:3: PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:70:3-70:3: PUSH_MTHD(push, NV9039, LAUNCH_DMA,
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:96:2-96:2: PUSH_MTHD(push, NV9039, SET_OBJECT, handle);
• drivers/gpu/drm/nouveau/nouveau_bo90b5.c:51:3-51:3: PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset),
• drivers/gpu/drm/nouveau/nouveau_bo90b5.c:59:3-59:3: PUSH_NVIM(push, NV90B5, 0x0300, 0x0110);
• drivers/gpu/drm/nouveau/nouveau_boa0b5.c:49:2-49:2: PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_boa0b5.c:63:2-63:2: PUSH_IMMD(push, NVA0B5, LAUNCH_DMA,
• drivers/gpu/drm/nouveau/nouveau_boa0b5.c:88:2-88:2: PUSH_NVSQ(push, NVA0B5, 0x0000, handle & 0x0000ffff);
• drivers/gpu/drm/nouveau/nouveau_chan.c:480:3-480:3: PUSH_DATA(chan->chan.push, 0x00000000);
• drivers/gpu/drm/nouveau/nouveau_chan.c:494:3-494:3: PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
• drivers/gpu/drm/nouveau/nouveau_dmem.c:411:4-411:4: PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:415:4-415:4: PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:428:4-428:4: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:432:4-432:4: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:442:2-442:2: PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:456:2-456:2: PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
• drivers/gpu/drm/nouveau/nouveau_dmem.c:483:3-483:3: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:487:3-487:3: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:496:2-496:2: PUSH_MTHD(push, NVA0B5, SET_REMAP_CONST_A, 0,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:505:2-505:2: PUSH_MTHD(push, NVA0B5, OFFSET_OUT_UPPER,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:510:2-510:2: PUSH_MTHD(push, NVA0B5, LINE_LENGTH_IN, length >> 3);
• drivers/gpu/drm/nouveau/nouveau_dmem.c:512:2-512:2: PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
• drivers/gpu/drm/nouveau/nouveau_drm.c:380:5-380:5: PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
• drivers/gpu/drm/nouveau/nouveau_gem.c:851:4-851:4: PUSH_CALL(chan->chan.push, nvbo->offset + push[i].offset);
• drivers/gpu/drm/nouveau/nouveau_gem.c:852:4-852:4: PUSH_DATA(chan->chan.push, 0);
• drivers/gpu/drm/nouveau/nouveau_gem.c:885:4-885:4: PUSH_JUMP(chan->chan.push, nvbo->offset + push[i].offset);
• drivers/gpu/drm/nouveau/nouveau_gem.c:886:4-886:4: PUSH_DATA(chan->chan.push, 0);
• drivers/gpu/drm/nouveau/nouveau_gem.c:888:5-888:5: PUSH_DATA(chan->chan.push, 0);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:44:2-44:2: PUSH_NVSQ(push, NV05F, 0x0300, (region->sy << 16) | region->sx,
• drivers/gpu/drm/nouveau/nv04_fbcon.c:64:2-64:2: PUSH_NVSQ(push, NV04A, 0x02fc, (rect->rop != ROP_COPY) ? 1 : 3);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:67:3-67:3: PUSH_NVSQ(push, NV04A, 0x03fc, ((uint32_t *)info->pseudo_palette)[rect->color]);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:69:3-69:3: PUSH_NVSQ(push, NV04A, 0x03fc, rect->color);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:70:2-70:2: PUSH_NVSQ(push, NV04A, 0x0400, (rect->dx << 16) | rect->dy,
• drivers/gpu/drm/nouveau/nv04_fbcon.c:105:2-105:2: PUSH_NVSQ(push, NV04A, 0x0be4, (image->dy << 16) | (image->dx & 0xffff),
• drivers/gpu/drm/nouveau/nv04_fbcon.c:122:3-122:3: PUSH_NVSQ(push, NV04A, 0x0c00, data, iter_len);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:208:2-208:2: PUSH_NVSQ(push, NV042, 0x0000, nfbdev->surf2d.handle);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:209:2-209:2: PUSH_NVSQ(push, NV042, 0x0184, chan->vram.handle,
• drivers/gpu/drm/nouveau/nv04_fbcon.c:211:2-211:2: PUSH_NVSQ(push, NV042, 0x0300, surface_fmt,
• drivers/gpu/drm/nouveau/nv04_fbcon.c:216:2-216:2: PUSH_NVSQ(push, NV043, 0x0000, nfbdev->rop.handle);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:217:2-217:2: PUSH_NVSQ(push, NV043, 0x0300, 0x55);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:219:2-219:2: PUSH_NVSQ(push, NV044, 0x0000, nfbdev->patt.handle);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:220:2-220:2: PUSH_NVSQ(push, NV044, 0x0300, pattern_fmt,
• drivers/gpu/drm/nouveau/nv04_fbcon.c:233:2-233:2: PUSH_NVSQ(push, NV019, 0x0000, nfbdev->clip.handle);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:234:2-234:2: PUSH_NVSQ(push, NV019, 0x0300, 0,
• drivers/gpu/drm/nouveau/nv04_fbcon.c:237:2-237:2: PUSH_NVSQ(push, NV05F, 0x0000, nfbdev->blit.handle);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:238:2-238:2: PUSH_NVSQ(push, NV05F, 0x019c, nfbdev->surf2d.handle);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:239:2-239:2: PUSH_NVSQ(push, NV05F, 0x02fc, 3);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:241:3-241:3: PUSH_NVSQ(push, NV09F, 0x0120, 0,
• drivers/gpu/drm/nouveau/nv04_fbcon.c:246:2-246:2: PUSH_NVSQ(push, NV04A, 0x0000, nfbdev->gdi.handle);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:247:2-247:2: PUSH_NVSQ(push, NV04A, 0x0198, nfbdev->surf2d.handle);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:248:2-248:2: PUSH_NVSQ(push, NV04A, 0x0188, nfbdev->patt.handle,
• drivers/gpu/drm/nouveau/nv04_fbcon.c:250:2-250:2: PUSH_NVSQ(push, NV04A, 0x0304, 1);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:251:2-251:2: PUSH_NVSQ(push, NV04A, 0x0300, rect_fmt);
• drivers/gpu/drm/nouveau/nv04_fbcon.c:252:2-252:2: PUSH_NVSQ(push, NV04A, 0x02fc, 3);
• drivers/gpu/drm/nouveau/nv04_fence.c:45:3-45:3: PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno);
• drivers/gpu/drm/nouveau/nv10_fence.c:38:3-38:3: PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno);
• drivers/gpu/drm/nouveau/nv17_fence.c:57:3-57:3: PUSH_MTHD(ppush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
• drivers/gpu/drm/nouveau/nv17_fence.c:65:3-65:3: PUSH_MTHD(npush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:55:3-55:3: PUSH_MTHD(push, NV502D, SET_OPERATION,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:59:2-59:2: PUSH_MTHD(push, NV502D, SET_RENDER_SOLID_PRIM_COLOR, colour);
• drivers/gpu/drm/nouveau/nv50_fbcon.c:61:2-61:2: PUSH_MTHD(push, NV502D, RENDER_SOLID_PRIM_POINT_SET_X(0), rect->dx,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:67:3-67:3: PUSH_MTHD(push, NV502D, SET_OPERATION,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:88:2-88:2: PUSH_MTHD(push, NV502D, WAIT_FOR_IDLE, 0);
• drivers/gpu/drm/nouveau/nv50_fbcon.c:90:2-90:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_DST_X0, region->dx,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:95:2-95:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC, 0,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:131:2-131:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_COLOR0, bg,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:134:2-134:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_SRC_WIDTH, image->width,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:137:2-137:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_DST_X0_FRAC, 0,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:152:3-152:3: PUSH_NINC(push, NV502D, PIXELS_FROM_CPU_DATA, data, count);
• drivers/gpu/drm/nouveau/nv50_fbcon.c:208:2-208:2: PUSH_MTHD(push, NV502D, SET_OBJECT, nfbdev->twod.handle);
• drivers/gpu/drm/nouveau/nv50_fbcon.c:209:2-209:2: PUSH_MTHD(push, NV502D, SET_DST_CONTEXT_DMA, chan->vram.handle,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:213:2-213:2: PUSH_MTHD(push, NV502D, SET_DST_FORMAT,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:219:2-219:2: PUSH_MTHD(push, NV502D, SET_DST_PITCH, info->fix.line_length,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:229:2-229:2: PUSH_MTHD(push, NV502D, SET_SRC_FORMAT,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:235:2-235:2: PUSH_MTHD(push, NV502D, SET_SRC_PITCH, info->fix.line_length,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:245:2-245:2: PUSH_MTHD(push, NV502D, SET_CLIP_ENABLE,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:248:2-248:2: PUSH_MTHD(push, NV502D, SET_ROP,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:251:2-251:2: PUSH_MTHD(push, NV502D, SET_OPERATION,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:254:2-254:2: PUSH_MTHD(push, NV502D, SET_MONOCHROME_PATTERN_COLOR_FORMAT,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:260:2-260:2: PUSH_MTHD(push, NV502D, RENDER_SOLID_PRIM_MODE,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:266:2-266:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_DATA_TYPE,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:281:2-281:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_MONO_OPACITY,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:284:2-284:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_DX_DU_FRAC, 0,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:289:2-289:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP,
• drivers/gpu/drm/nouveau/nv50_fbcon.c:292:2-292:2: PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_DU_DX_FRAC, 0,
• drivers/gpu/drm/nouveau/nv84_fence.c:41:3-41:3: PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
• drivers/gpu/drm/nouveau/nv84_fence.c:43:3-43:3: PUSH_MTHD(push, NV826F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nv84_fence.c:64:3-64:3: PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
• drivers/gpu/drm/nouveau/nv84_fence.c:66:3-66:3: PUSH_MTHD(push, NV826F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:55:3-55:3: PUSH_IMMD(push, NV902D, SET_OPERATION,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:59:2-59:2: PUSH_MTHD(push, NV902D, SET_RENDER_SOLID_PRIM_COLOR, colour);
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:61:2-61:2: PUSH_MTHD(push, NV902D, RENDER_SOLID_PRIM_POINT_SET_X(0), rect->dx,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:67:3-67:3: PUSH_IMMD(push, NV902D, SET_OPERATION,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:88:2-88:2: PUSH_IMMD(push, NV902D, WAIT_FOR_IDLE, 0);
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:90:2-90:2: PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_MEMORY_DST_X0, region->dx,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:95:2-95:2: PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC, 0,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:131:2-131:2: PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_COLOR0, bg,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:134:2-134:2: PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_SRC_WIDTH, image->width,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:137:2-137:2: PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_DST_X0_FRAC, 0,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:152:3-152:3: PUSH_NINC(push, NV902D, PIXELS_FROM_CPU_DATA, data, count);
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:209:2-209:2: PUSH_MTHD(push, NV902D, SET_OBJECT, nfbdev->twod.handle);
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:211:2-211:2: PUSH_MTHD(push, NV902D, SET_DST_FORMAT,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:217:2-217:2: PUSH_MTHD(push, NV902D, SET_DST_PITCH, info->fix.line_length,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:227:2-227:2: PUSH_MTHD(push, NV902D, SET_SRC_FORMAT,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:233:2-233:2: PUSH_MTHD(push, NV902D, SET_SRC_PITCH, info->fix.line_length,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:243:2-243:2: PUSH_IMMD(push, NV902D, SET_CLIP_ENABLE,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:246:2-246:2: PUSH_IMMD(push, NV902D, SET_ROP,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:249:2-249:2: PUSH_IMMD(push, NV902D, SET_OPERATION,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:252:2-252:2: PUSH_MTHD(push, NV902D, SET_MONOCHROME_PATTERN_COLOR_FORMAT,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:258:2-258:2: PUSH_MTHD(push, NV902D, RENDER_SOLID_PRIM_MODE,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:264:2-264:2: PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_DATA_TYPE,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:279:2-279:2: PUSH_IMMD(push, NV902D, SET_PIXELS_FROM_CPU_MONO_OPACITY,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:282:2-282:2: PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_DX_DU_FRAC, 0,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:287:2-287:2: PUSH_IMMD(push, NV902D, SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP,
• drivers/gpu/drm/nouveau/nvc0_fbcon.c:290:2-290:2: PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_MEMORY_DU_DX_FRAC, 0,
• drivers/gpu/drm/nouveau/nvc0_fence.c:40:3-40:3: PUSH_MTHD(push, NV906F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nvc0_fence.c:63:3-63:3: PUSH_MTHD(push, NV906F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c:193:4-193:4: nvkm_fo64(pt->memory, 0, 0, size >> 3);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c:94:2-94:2: VMM_FO064(pt, vmm, ptei * 8, 0ULL, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c:336:2-336:2: nvkm_fo64(inst, 0x0200, 0x00000000, 2);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c:29:2-29:2: VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(1) /* PRIV. */, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c:32:2-32:2: VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(32) /* VOL. */, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c:57:2-57:2: VMM_FO064(pt, vmm, pdei * 8, BIT_ULL(35) /* VOL_BIG. */, pdes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c:166:2-166:2: VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(3) /* VOL. */, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c:186:2-186:2: VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(5) /* PRIV. */, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c:63:2-63:2: VMM_FO032(pt, vmm, 8 + (ptei * 4), 0, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c:64:2-64:2: VMM_FO032(pt, vmm, ptei * 4, 0, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c:94:2-94:2: VMM_FO064(pt, vmm, ptei * 8, 0ULL, ptes);
• drivers/infiniband/hw/hns/hns_roce_qp.c:550:6-550:6: if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) ||
• drivers/infiniband/hw/mlx5/qp.c:5186:6-5186:6: if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
• drivers/md/bcache/stats.c:62:2-62:2: sysfs_print(cache_hit_ratio,
• drivers/net/wireless/ath/wil6210/pmc.c:141:3-141:46: struct vring_tx_desc *_d = &pmc->pring_va[i];
• drivers/net/wireless/ath/wil6210/txrx.c:159:3-160:21: volatile struct vring_tx_desc *_d =
• drivers/net/wireless/ath/wil6210/txrx.c:215:4-216:35: volatile struct vring_tx_desc *_d =
• drivers/net/wireless/ath/wil6210/txrx.c:233:4-234:34: volatile struct vring_rx_desc *_d =
• drivers/net/wireless/ath/wil6210/txrx.c:262:2-262:55: volatile struct vring_rx_desc *_d = &vring->va[i].rx.legacy;
• drivers/net/wireless/ath/wil6210/txrx.c:353:2-353:24: struct vring_rx_desc *_d;
• drivers/net/wireless/ath/wil6210/txrx.c:445:2-445:33: volatile struct vring_rx_desc *_d;
• drivers/net/wireless/ath/wil6210/txrx.c:2033:2-2033:33: volatile struct vring_tx_desc *_d;
• drivers/net/wireless/ath/wil6210/txrx.c:2430:2-2430:33: volatile struct vring_tx_desc *_d;
• drivers/net/wireless/ath/wil6210/txrx_edma.c:164:2-165:19: struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *)
• drivers/net/wireless/ath/wil6210/txrx_edma.c:453:3-455:31: struct wil_tx_enhanced_desc *_d =
• drivers/net/wireless/ath/wil6210/txrx_edma.c:1169:2-1169:31: struct wil_tx_enhanced_desc *_d;
• drivers/net/wireless/realtek/rtw89/sar.c:123:2-123:2: rtw89_sar_set_src(rtwdev, RTW89_SAR_SOURCE_COMMON, cfg_common, sar);
• drivers/nvme/host/core.c:2922:6-2922:6: if (check_shl_overflow(1U, units + page_shift - 9, &val))
• drivers/rapidio/devices/tsi721_dma.c:896:2-896:32: struct tsi721_tx_desc *desc, *_d;
• drivers/w1/masters/ds1wm.c:414:4-414:38: unsigned char resp, _r, _r_prime, _d;
• fs/io_uring.c:10564:7-10564:7: if (check_shl_overflow(off, 1, &off))
• lib/overflow_kunit.c:291:2-291:2: TEST_ONE_SHIFT(1, 0, u8, 1 << 0, false);
• lib/overflow_kunit.c:292:2-292:2: TEST_ONE_SHIFT(1, 4, u8, 1 << 4, false);
• lib/overflow_kunit.c:293:2-293:2: TEST_ONE_SHIFT(1, 7, u8, 1 << 7, false);
• lib/overflow_kunit.c:294:2-294:2: TEST_ONE_SHIFT(0xF, 4, u8, 0xF << 4, false);
• lib/overflow_kunit.c:295:2-295:2: TEST_ONE_SHIFT(1, 0, u16, 1 << 0, false);
• lib/overflow_kunit.c:296:2-296:2: TEST_ONE_SHIFT(1, 10, u16, 1 << 10, false);
• lib/overflow_kunit.c:297:2-297:2: TEST_ONE_SHIFT(1, 15, u16, 1 << 15, false);
• lib/overflow_kunit.c:298:2-298:2: TEST_ONE_SHIFT(0xFF, 8, u16, 0xFF << 8, false);
• lib/overflow_kunit.c:299:2-299:2: TEST_ONE_SHIFT(1, 0, int, 1 << 0, false);
• lib/overflow_kunit.c:300:2-300:2: TEST_ONE_SHIFT(1, 16, int, 1 << 16, false);
• lib/overflow_kunit.c:301:2-301:2: TEST_ONE_SHIFT(1, 30, int, 1 << 30, false);
• lib/overflow_kunit.c:302:2-302:2: TEST_ONE_SHIFT(1, 0, s32, 1 << 0, false);
• lib/overflow_kunit.c:303:2-303:2: TEST_ONE_SHIFT(1, 16, s32, 1 << 16, false);
• lib/overflow_kunit.c:304:2-304:2: TEST_ONE_SHIFT(1, 30, s32, 1 << 30, false);
• lib/overflow_kunit.c:305:2-305:2: TEST_ONE_SHIFT(1, 0, unsigned int, 1U << 0, false);
• lib/overflow_kunit.c:306:2-306:2: TEST_ONE_SHIFT(1, 20, unsigned int, 1U << 20, false);
• lib/overflow_kunit.c:307:2-307:2: TEST_ONE_SHIFT(1, 31, unsigned int, 1U << 31, false);
• lib/overflow_kunit.c:308:2-308:2: TEST_ONE_SHIFT(0xFFFFU, 16, unsigned int, 0xFFFFU << 16, false);
• lib/overflow_kunit.c:309:2-309:2: TEST_ONE_SHIFT(1, 0, u32, 1U << 0, false);
• lib/overflow_kunit.c:310:2-310:2: TEST_ONE_SHIFT(1, 20, u32, 1U << 20, false);
• lib/overflow_kunit.c:311:2-311:2: TEST_ONE_SHIFT(1, 31, u32, 1U << 31, false);
• lib/overflow_kunit.c:312:2-312:2: TEST_ONE_SHIFT(0xFFFFU, 16, u32, 0xFFFFU << 16, false);
• lib/overflow_kunit.c:313:2-313:2: TEST_ONE_SHIFT(1, 0, u64, 1ULL << 0, false);
• lib/overflow_kunit.c:314:2-314:2: TEST_ONE_SHIFT(1, 40, u64, 1ULL << 40, false);
• lib/overflow_kunit.c:315:2-315:2: TEST_ONE_SHIFT(1, 63, u64, 1ULL << 63, false);
• lib/overflow_kunit.c:316:2-316:2: TEST_ONE_SHIFT(0xFFFFFFFFULL, 32, u64, 0xFFFFFFFFULL << 32, false);
• lib/overflow_kunit.c:319:2-319:2: TEST_ONE_SHIFT(0, 7, u8, 0, false);
• lib/overflow_kunit.c:320:2-320:2: TEST_ONE_SHIFT(0, 15, u16, 0, false);
• lib/overflow_kunit.c:321:2-321:2: TEST_ONE_SHIFT(0, 31, unsigned int, 0, false);
• lib/overflow_kunit.c:322:2-322:2: TEST_ONE_SHIFT(0, 31, u32, 0, false);
• lib/overflow_kunit.c:323:2-323:2: TEST_ONE_SHIFT(0, 63, u64, 0, false);
• lib/overflow_kunit.c:326:2-326:2: TEST_ONE_SHIFT(0, 6, s8, 0, false);
• lib/overflow_kunit.c:327:2-327:2: TEST_ONE_SHIFT(0, 14, s16, 0, false);
• lib/overflow_kunit.c:328:2-328:2: TEST_ONE_SHIFT(0, 30, int, 0, false);
• lib/overflow_kunit.c:329:2-329:2: TEST_ONE_SHIFT(0, 30, s32, 0, false);
• lib/overflow_kunit.c:330:2-330:2: TEST_ONE_SHIFT(0, 62, s64, 0, false);
• lib/overflow_kunit.c:333:2-333:2: TEST_ONE_SHIFT(1, 8, u8, 0, true);
• lib/overflow_kunit.c:334:2-334:2: TEST_ONE_SHIFT(1, 16, u16, 0, true);
• lib/overflow_kunit.c:335:2-335:2: TEST_ONE_SHIFT(1, 32, unsigned int, 0, true);
• lib/overflow_kunit.c:336:2-336:2: TEST_ONE_SHIFT(1, 32, u32, 0, true);
• lib/overflow_kunit.c:337:2-337:2: TEST_ONE_SHIFT(1, 64, u64, 0, true);
• lib/overflow_kunit.c:340:2-340:2: TEST_ONE_SHIFT(1, 7, s8, 0, true);
• lib/overflow_kunit.c:341:2-341:2: TEST_ONE_SHIFT(1, 15, s16, 0, true);
• lib/overflow_kunit.c:342:2-342:2: TEST_ONE_SHIFT(1, 31, int, 0, true);
• lib/overflow_kunit.c:343:2-343:2: TEST_ONE_SHIFT(1, 31, s32, 0, true);
• lib/overflow_kunit.c:344:2-344:2: TEST_ONE_SHIFT(1, 63, s64, 0, true);
• lib/overflow_kunit.c:348:2-348:2: TEST_ONE_SHIFT(150, 1, u8, 0, true);
• lib/overflow_kunit.c:350:2-350:2: TEST_ONE_SHIFT(34966, 1, u16, 0, true);
• lib/overflow_kunit.c:352:2-352:2: TEST_ONE_SHIFT(2215151766U, 1, u32, 0, true);
• lib/overflow_kunit.c:353:2-353:2: TEST_ONE_SHIFT(2215151766U, 1, unsigned int, 0, true);
• lib/overflow_kunit.c:355:2-355:2: TEST_ONE_SHIFT(9372061470395238550ULL, 1, u64, 0, true);
• lib/overflow_kunit.c:359:2-359:2: TEST_ONE_SHIFT(75, 1, s8, 0, true);
• lib/overflow_kunit.c:361:2-361:2: TEST_ONE_SHIFT(17483, 1, s16, 0, true);
• lib/overflow_kunit.c:363:2-363:2: TEST_ONE_SHIFT(1107575883, 1, s32, 0, true);
• lib/overflow_kunit.c:364:2-364:2: TEST_ONE_SHIFT(1107575883, 1, int, 0, true);
• lib/overflow_kunit.c:366:2-366:2: TEST_ONE_SHIFT(4686030735197619275LL, 1, s64, 0, true);
• lib/overflow_kunit.c:370:2-370:2: TEST_ONE_SHIFT(75, 2, s8, 0, true);
• lib/overflow_kunit.c:372:2-372:2: TEST_ONE_SHIFT(17483, 2, s16, 0, true);
• lib/overflow_kunit.c:374:2-374:2: TEST_ONE_SHIFT(1107575883, 2, s32, 0, true);
• lib/overflow_kunit.c:375:2-375:2: TEST_ONE_SHIFT(1107575883, 2, int, 0, true);
• lib/overflow_kunit.c:377:2-377:2: TEST_ONE_SHIFT(4686030735197619275LL, 2, s64, 0, true);
• lib/overflow_kunit.c:380:2-380:2: TEST_ONE_SHIFT(0x100, 0, u8, 0, true);
• lib/overflow_kunit.c:381:2-381:2: TEST_ONE_SHIFT(0xFF, 0, s8, 0, true);
• lib/overflow_kunit.c:382:2-382:2: TEST_ONE_SHIFT(0x10000U, 0, u16, 0, true);
• lib/overflow_kunit.c:383:2-383:2: TEST_ONE_SHIFT(0xFFFFU, 0, s16, 0, true);
• lib/overflow_kunit.c:384:2-384:2: TEST_ONE_SHIFT(0x100000000ULL, 0, u32, 0, true);
• lib/overflow_kunit.c:385:2-385:2: TEST_ONE_SHIFT(0x100000000ULL, 0, unsigned int, 0, true);
• lib/overflow_kunit.c:386:2-386:2: TEST_ONE_SHIFT(0xFFFFFFFFUL, 0, s32, 0, true);
• lib/overflow_kunit.c:387:2-387:2: TEST_ONE_SHIFT(0xFFFFFFFFUL, 0, int, 0, true);
• lib/overflow_kunit.c:388:2-388:2: TEST_ONE_SHIFT(0xFFFFFFFFFFFFFFFFULL, 0, s64, 0, true);
• lib/overflow_kunit.c:391:2-391:2: TEST_ONE_SHIFT(-1, 0, s8, 0, true);
• lib/overflow_kunit.c:392:2-392:2: TEST_ONE_SHIFT(-1, 0, u8, 0, true);
• lib/overflow_kunit.c:393:2-393:2: TEST_ONE_SHIFT(-5, 0, s16, 0, true);
• lib/overflow_kunit.c:394:2-394:2: TEST_ONE_SHIFT(-5, 0, u16, 0, true);
• lib/overflow_kunit.c:395:2-395:2: TEST_ONE_SHIFT(-10, 0, int, 0, true);
• lib/overflow_kunit.c:396:2-396:2: TEST_ONE_SHIFT(-10, 0, unsigned int, 0, true);
• lib/overflow_kunit.c:397:2-397:2: TEST_ONE_SHIFT(-100, 0, s32, 0, true);
• lib/overflow_kunit.c:398:2-398:2: TEST_ONE_SHIFT(-100, 0, u32, 0, true);
• lib/overflow_kunit.c:399:2-399:2: TEST_ONE_SHIFT(-10000, 0, s64, 0, true);
• lib/overflow_kunit.c:400:2-400:2: TEST_ONE_SHIFT(-10000, 0, u64, 0, true);
• lib/overflow_kunit.c:403:2-403:2: TEST_ONE_SHIFT(0, -5, s8, 0, true);
• lib/overflow_kunit.c:404:2-404:2: TEST_ONE_SHIFT(0, -5, u8, 0, true);
• lib/overflow_kunit.c:405:2-405:2: TEST_ONE_SHIFT(0, -10, s16, 0, true);
• lib/overflow_kunit.c:406:2-406:2: TEST_ONE_SHIFT(0, -10, u16, 0, true);
• lib/overflow_kunit.c:407:2-407:2: TEST_ONE_SHIFT(0, -15, int, 0, true);
• lib/overflow_kunit.c:408:2-408:2: TEST_ONE_SHIFT(0, -15, unsigned int, 0, true);
• lib/overflow_kunit.c:409:2-409:2: TEST_ONE_SHIFT(0, -20, s32, 0, true);
• lib/overflow_kunit.c:410:2-410:2: TEST_ONE_SHIFT(0, -20, u32, 0, true);
• lib/overflow_kunit.c:411:2-411:2: TEST_ONE_SHIFT(0, -30, s64, 0, true);
• lib/overflow_kunit.c:412:2-412:2: TEST_ONE_SHIFT(0, -30, u64, 0, true);
• lib/overflow_kunit.c:415:2-415:2: TEST_ONE_SHIFT(0, 8, u8, 0, true);
• lib/overflow_kunit.c:416:2-416:2: TEST_ONE_SHIFT(0, 9, u8, 0, true);
• lib/overflow_kunit.c:417:2-417:2: TEST_ONE_SHIFT(0, 8, s8, 0, true);
• lib/overflow_kunit.c:418:2-418:2: TEST_ONE_SHIFT(0, 9, s8, 0, true);
• lib/overflow_kunit.c:419:2-419:2: TEST_ONE_SHIFT(0, 16, u16, 0, true);
• lib/overflow_kunit.c:420:2-420:2: TEST_ONE_SHIFT(0, 17, u16, 0, true);
• lib/overflow_kunit.c:421:2-421:2: TEST_ONE_SHIFT(0, 16, s16, 0, true);
• lib/overflow_kunit.c:422:2-422:2: TEST_ONE_SHIFT(0, 17, s16, 0, true);
• lib/overflow_kunit.c:423:2-423:2: TEST_ONE_SHIFT(0, 32, u32, 0, true);
• lib/overflow_kunit.c:424:2-424:2: TEST_ONE_SHIFT(0, 33, u32, 0, true);
• lib/overflow_kunit.c:425:2-425:2: TEST_ONE_SHIFT(0, 32, int, 0, true);
• lib/overflow_kunit.c:426:2-426:2: TEST_ONE_SHIFT(0, 33, int, 0, true);
• lib/overflow_kunit.c:427:2-427:2: TEST_ONE_SHIFT(0, 32, s32, 0, true);
• lib/overflow_kunit.c:428:2-428:2: TEST_ONE_SHIFT(0, 33, s32, 0, true);
• lib/overflow_kunit.c:429:2-429:2: TEST_ONE_SHIFT(0, 64, u64, 0, true);
• lib/overflow_kunit.c:430:2-430:2: TEST_ONE_SHIFT(0, 65, u64, 0, true);
• lib/overflow_kunit.c:431:2-431:2: TEST_ONE_SHIFT(0, 64, s64, 0, true);
• lib/overflow_kunit.c:432:2-432:2: TEST_ONE_SHIFT(0, 65, s64, 0, true);
• lib/overflow_kunit.c:443:2-443:2: TEST_ONE_SHIFT(0, 7, s8, 0, false);
• lib/overflow_kunit.c:444:2-444:2: TEST_ONE_SHIFT(0, 15, s16, 0, false);
• lib/overflow_kunit.c:445:2-445:2: TEST_ONE_SHIFT(0, 31, int, 0, false);
• lib/overflow_kunit.c:446:2-446:2: TEST_ONE_SHIFT(0, 31, s32, 0, false);
• lib/overflow_kunit.c:447:2-447:2: TEST_ONE_SHIFT(0, 63, s64, 0, false);
• mm/vmalloc.c:3565:6-3565:6: if (check_shl_overflow(pgoff, PAGE_SHIFT, &off))
• net/sched/act_pedit.c:370:5-370:12: u8 *d, _d;