Symbol: i0

function parameter

Defined...

• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1454:42-1454:51: static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1456:49-1456:58: static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1458:55-1458:64: static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1460:54-1460:63: static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:915:44-915:53: static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:917:48-917:57: static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1221:40-1221:49: static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1223:48-1223:57: static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1246:49-1246:58: static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1273:49-1273:58: static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1281:54-1281:63: static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1880:53-1880:62: static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1882:58-1882:67: static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1884:60-1884:69: static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1892:54-1892:63: static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1894:60-1894:69: static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1968:43-1968:52: static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1970:51-1970:60: static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1998:51-1998:60: static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2000:44-2000:53: static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2002:50-2002:59: static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2087:52-2087:61: static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2089:57-2089:66: static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2187:53-2187:62: static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2189:58-2189:67: static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2395:43-2395:52: static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2397:47-2397:56: static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2425:47-2425:56: static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2427:51-2427:60: static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2668:43-2668:52: static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2670:47-2670:56: static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2681:52-2681:61: static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2683:56-2683:65: static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2835:42-2835:51: static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2837:49-2837:58: static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2863:55-2863:64: static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2865:54-2865:63: static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2890:52-2890:61: static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2892:54-2892:63: static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2894:54-2894:63: static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2896:54-2896:63: static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2898:54-2898:63: static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:971:40-971:49: static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:973:48-973:57: static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:991:49-991:58: static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1024:45-1024:54: static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1026:49-1026:58: static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1034:54-1034:63: static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1537:50-1537:59: static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1539:54-1539:63: static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1541:54-1541:63: static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1547:51-1547:60: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1549:55-1549:64: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1551:52-1551:61: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1553:56-1553:65: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1555:52-1555:61: static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1557:56-1557:65: static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1559:53-1559:62: static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1561:57-1561:66: static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2011:51-2011:60: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2013:55-2013:64: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2015:52-2015:61: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2017:56-2017:65: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2019:52-2019:61: static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2021:56-2021:65: static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2023:53-2023:62: static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2025:57-2025:66: static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2027:51-2027:60: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2029:55-2029:64: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2031:52-2031:61: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2033:56-2033:65: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2035:57-2035:66: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2037:61-2037:70: static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2039:61-2039:70: static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2041:65-2041:74: static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2055:65-2055:74: static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2057:69-2057:78: static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2195:44-2195:53: static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2197:48-2197:57: static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2257:44-2257:53: static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2259:48-2259:57: static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2367:43-2367:52: static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2369:47-2369:56: static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2395:47-2395:56: static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2397:51-2397:60: static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2535:43-2535:52: static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2537:47-2537:56: static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2639:43-2639:52: static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2641:47-2641:56: static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2667:47-2667:56: static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2669:51-2669:60: static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2737:43-2737:52: static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2739:47-2739:56: static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2765:47-2765:56: static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2767:51-2767:60: static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2865:52-2865:61: static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2867:57-2867:66: static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2869:53-2869:62: static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2871:58-2871:67: static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2895:49-2895:58: static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2897:53-2897:62: static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2923:55-2923:64: static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2925:59-2925:68: static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2927:54-2927:63: static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2929:58-2929:67: static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3031:43-3031:52: static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3033:51-3033:60: static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3049:51-3049:60: static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3051:51-3051:60: static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3059:51-3059:60: static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3067:44-3067:53: static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3069:50-3069:59: static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1034:44-1034:53: static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1036:48-1036:57: static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1038:44-1038:53: static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1040:48-1040:57: static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2133:49-2133:58: static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2135:53-2135:62: static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2161:55-2161:64: static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2163:58-2163:67: static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2165:58-2165:67: static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2167:54-2167:63: static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2169:58-2169:67: static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3251:40-3251:49: static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3253:48-3253:57: static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3270:54-3270:63: static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3308:49-3308:58: static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3335:46-3335:55: static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3343:52-3343:61: static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3351:48-3351:57: static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3353:48-3353:57: static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3760:52-3760:61: static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3762:60-3762:69: static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3764:60-3764:69: static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3766:58-3766:67: static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3774:64-3774:73: static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3815:52-3815:61: static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3817:57-3817:66: static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3819:53-3819:62: static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3821:58-3821:67: static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3827:41-3827:50: static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3829:49-3829:58: static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3910:40-3910:49: static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3912:55-3912:64: static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3914:55-3914:64: static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3916:52-3916:61: static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3918:46-3918:55: static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3920:54-3920:63: static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3922:54-3922:63: static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3924:54-3924:63: static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4069:43-4069:52: static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4071:51-4071:60: static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4073:51-4073:60: static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4075:48-4075:57: static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4077:50-4077:59: static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4079:44-4079:53: static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4081:50-4081:59: static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4104:54-4104:63: static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4106:47-4106:56: static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4108:53-4108:62: static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4257:43-4257:52: static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4259:47-4259:56: static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4285:47-4285:56: static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4287:51-4287:60: static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4384:46-4384:55: static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4386:50-4386:59: static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4395:43-4395:52: static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4397:47-4397:56: static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1173:44-1173:53: static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1175:48-1175:57: static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1177:44-1177:53: static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1179:48-1179:57: static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1206:51-1206:60: static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1208:54-1208:63: static inline uint32_t REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008e0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1517:49-1517:58: static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1519:51-1519:60: static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1521:49-1521:58: static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1523:50-1523:59: static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1525:51-1525:60: static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1527:50-1527:59: static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1529:50-1529:59: static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1531:50-1531:59: static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1533:50-1533:59: static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1535:51-1535:60: static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1537:49-1537:58: static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1539:49-1539:58: static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1541:49-1541:58: static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1543:50-1543:59: static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1545:50-1545:59: static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1547:50-1547:59: static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1549:49-1549:58: static inline uint32_t REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000300 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1551:51-1551:60: static inline uint32_t REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000031c + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1553:49-1553:58: static inline uint32_t REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000324 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1555:50-1555:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000334 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1557:51-1557:60: static inline uint32_t REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000344 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1559:50-1559:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000350 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1561:50-1561:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000035c + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1563:50-1563:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000366 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1565:50-1565:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000036e + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1567:51-1567:60: static inline uint32_t REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000376 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1569:49-1569:58: static inline uint32_t REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000038e + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1571:49-1571:58: static inline uint32_t REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000003a6 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1573:49-1573:58: static inline uint32_t REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000003d6 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1575:50-1575:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000003e6 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1577:50-1577:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000003ea + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1579:50-1579:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000003f2 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1581:50-1581:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0) { return 0x000003fa + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1583:52-1583:61: static inline uint32_t REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0) { return 0x00000410 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1585:50-1585:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0) { return 0x0000041c + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1587:50-1587:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0) { return 0x0000042a + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1589:50-1589:59: static inline uint32_t REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0) { return 0x00000442 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1591:51-1591:60: static inline uint32_t REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0) { return 0x0000044e + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1593:52-1593:61: static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0) { return 0x00000460 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1595:53-1595:62: static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0) { return 0x00000470 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1597:53-1597:62: static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0) { return 0x00000480 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1599:53-1599:62: static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0) { return 0x0000048c + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1601:53-1601:62: static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0) { return 0x00000494 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1603:53-1603:62: static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000049c + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1619:55-1619:64: static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2112:53-2112:62: static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2144:55-2144:64: static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2311:49-2311:58: static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2313:53-2313:62: static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2351:43-2351:52: static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2353:47-2353:56: static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2355:52-2355:61: static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2357:56-2357:65: static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2359:52-2359:61: static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2361:56-2361:65: static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2447:47-2447:56: static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2449:55-2449:64: static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2457:54-2457:63: static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2465:55-2465:64: static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2473:54-2473:63: static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2481:55-2481:64: static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2489:54-2489:63: static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2497:49-2497:58: static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2499:53-2499:62: static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2507:53-2507:62: static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2867:56-2867:65: static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2869:59-2869:68: static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2883:59-2883:68: static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2897:58-2897:67: static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2899:61-2899:70: static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2913:61-2913:70: static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3169:54-3169:63: static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3171:54-3171:63: static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3173:54-3173:63: static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3551:40-3551:49: static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3553:48-3553:57: static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3570:54-3570:63: static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3608:49-3608:58: static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3634:46-3634:55: static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3642:52-3642:61: static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3650:45-3650:54: static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3658:50-3658:59: static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4228:52-4228:61: static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4230:57-4230:66: static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4238:58-4238:67: static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4498:51-4498:60: static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4500:52-4500:61: static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4504:52-4504:61: static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4506:52-4506:61: static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008e30 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4644:52-4644:61: static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4646:57-4646:66: static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4648:53-4648:62: static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4650:58-4650:67: static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4656:41-4656:50: static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4658:49-4658:58: static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4705:40-4705:49: static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4707:52-4707:61: static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4715:52-4715:61: static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4723:54-4723:63: static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4731:54-4731:63: static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4739:51-4739:60: static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4894:53-4894:62: static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4896:53-4896:62: static inline uint32_t REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x0000960b + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5230:51-5230:60: static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5232:51-5232:60: static inline uint32_t REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e42 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5367:43-5367:52: static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5369:48-5369:57: static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5377:48-5377:57: static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5379:50-5379:59: static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5381:44-5381:53: static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5383:50-5383:59: static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5412:54-5412:63: static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5414:47-5414:56: static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5416:53-5416:62: static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5434:53-5434:62: static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5436:53-5436:62: static inline uint32_t REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5483:43-5483:52: static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5485:47-5485:56: static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5511:47-5511:56: static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5513:51-5513:60: static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5771:43-5771:52: static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5773:47-5773:56: static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5799:47-5799:56: static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5801:51-5801:60: static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5951:43-5951:52: static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5953:47-5953:56: static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5979:47-5979:56: static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5981:51-5981:60: static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6334:46-6334:55: static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6336:50-6336:59: static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6345:43-6345:52: static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6347:47-6347:56: static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6375:48-6375:57: static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6377:52-6377:61: static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6418:57-6418:66: static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6420:61-6420:70: static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6647:53-6647:62: static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6649:64-6649:73: static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6710:50-6710:59: static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6712:61-6712:70: static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6773:51-6773:60: static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6775:53-6775:62: static inline uint32_t REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000ae60 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6779:51-6779:60: static inline uint32_t REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae80 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7142:53-7142:62: static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7540:55-7540:64: static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7542:66-7542:75: static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7632:52-7632:61: static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7634:63-7634:72: static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7672:55-7672:64: static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1150:47-1150:56: static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1152:49-1152:58: static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1173:49-1173:58: static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1181:49-1181:58: static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2208:52-2208:61: static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2210:54-2210:63: static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2218:54-2218:63: static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2226:54-2226:63: static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:326:38-326:47: static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:328:42-328:51: static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:330:43-330:52: static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:344:43-344:52: static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:346:45-346:54: static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:348:45-348:54: static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:360:44-360:53: static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:362:47-362:56: static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:382:53-382:62: static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:384:53-384:62: static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:386:56-386:65: static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:388:56-388:65: static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:390:57-390:66: static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:392:57-392:66: static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:404:48-404:57: static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:406:52-406:61: static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:409:50-409:59: static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:411:50-411:59: static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:413:51-413:60: static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:415:51-415:60: static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:417:49-417:58: static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:419:42-419:51: static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:422:45-422:54: static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:424:49-424:58: static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:426:49-426:58: static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:428:53-428:62: static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:430:50-430:59: static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:432:54-432:63: static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:434:49-434:58: static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:436:53-436:62: static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:438:50-438:59: static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:440:54-440:63: static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:444:38-444:47: static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:446:42-446:51: static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:448:46-448:55: static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:452:45-452:54: static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:463:37-463:51: static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:465:44-465:58: static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:494:46-494:60: static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:508:46-508:60: static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:510:48-510:62: static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:512:46-512:60: static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:526:49-526:63: static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:540:49-540:63: static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:542:48-542:62: static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:556:57-556:71: static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:566:56-566:70: static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:568:53-568:67: static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:570:54-570:68: static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:572:50-572:64: static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:574:41-574:55: static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:577:44-577:58: static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:579:48-579:62: static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:581:48-581:62: static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:583:52-583:66: static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:585:49-585:63: static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:587:53-587:67: static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:589:48-589:62: static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:591:52-591:66: static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:593:49-593:63: static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:595:53-595:67: static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:597:38-597:53: static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:599:47-599:62: static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:613:45-613:60: static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:627:47-627:62: static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:641:45-641:60: static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:655:49-655:64: static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:657:49-657:64: static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:659:49-659:64: static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:661:49-661:64: static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:663:51-663:66: static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:677:51-677:66: static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:691:56-691:71: static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:705:49-705:64: static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:766:49-766:64: static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:792:46-792:61: static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:817:50-817:65: static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:819:50-819:65: static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:821:51-821:66: static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:823:50-823:65: static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:825:42-825:57: static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:828:45-828:60: static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:830:49-830:64: static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:832:49-832:64: static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:834:53-834:68: static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:836:50-836:65: static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:838:54-838:69: static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:840:49-840:64: static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:842:53-842:68: static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:844:50-844:65: static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:846:54-846:69: static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:945:51-945:60: static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:947:58-947:67: static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:973:58-973:67: static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:276:45-276:54: static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:278:49-278:58: static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:298:45-298:54: static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:300:49-300:58: static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:330:37-330:56: static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:332:41-332:60: static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:334:45-334:64: static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:371:37-371:46: static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:385:43-385:52: static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:387:47-387:56: static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:451:40-451:49: static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:473:43-473:52: static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:504:43-504:52: static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:506:45-506:54: static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:520:47-520:56: static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:522:51-522:60: static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:565:38-565:53: static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:567:46-567:61: static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:582:52-582:67: static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:584:52-584:67: static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:586:52-586:67: static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:588:59-588:74: static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:602:59-602:74: static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:616:59-616:74: static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:630:59-630:74: static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:644:59-644:74: static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:652:54-652:69: static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:654:58-654:73: static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:668:55-668:70: static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:670:59-670:74: static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:684:53-684:68: static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:686:57-686:72: static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:694:54-694:69: static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:696:58-696:73: static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:704:47-704:62: static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:718:51-718:66: static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:732:45-732:60: static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:746:47-746:62: static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:760:45-760:60: static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:774:48-774:63: static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:776:48-776:63: static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:778:48-778:63: static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:780:48-780:63: static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:782:51-782:66: static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:796:51-796:66: static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:810:55-810:70: static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:812:49-812:64: static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:866:49-866:64: static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:892:50-892:65: static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:909:57-909:72: static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:911:51-911:66: static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:913:48-913:63: static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:915:56-915:71: static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:917:56-917:71: static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:919:56-919:71: static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:921:57-921:72: static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:923:56-923:71: static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:925:56-925:71: static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:927:56-927:71: static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:929:56-929:71: static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:931:49-931:64: static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:954:49-954:64: static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:956:52-956:67: static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:982:52-982:67: static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1008:60-1008:75: static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1022:51-1022:66: static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1062:57-1062:72: static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1064:57-1064:72: static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1066:60-1066:75: static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1068:60-1068:75: static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1070:57-1070:72: static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1072:57-1072:72: static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1086:36-1086:45: static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1088:52-1088:61: static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1098:45-1098:54: static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1112:51-1112:60: static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1114:51-1114:60: static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1129:42-1129:51: static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1131:50-1131:59: static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1153:51-1153:60: static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1155:51-1155:60: static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1157:57-1157:66: static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1159:57-1159:66: static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1161:58-1161:67: static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1163:58-1163:67: static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1165:57-1165:66: static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1167:57-1167:66: static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1169:58-1169:67: static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1171:58-1171:67: static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1173:52-1173:61: static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1187:48-1187:57: static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1201:46-1201:55: static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1215:50-1215:59: static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1223:50-1223:59: static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1231:53-1231:62: static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1233:52-1233:61: static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1247:56-1247:65: static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1257:55-1257:64: static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1259:61-1259:70: static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1261:61-1261:70: static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1263:62-1263:71: static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1265:62-1265:71: static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1267:48-1267:57: static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1279:38-1279:47: static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1281:46-1281:55: static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1298:47-1298:56: static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1300:51-1300:60: static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1302:52-1302:61: static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1304:52-1304:61: static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1306:52-1306:61: static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1308:46-1308:55: static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1310:49-1310:58: static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1312:46-1312:55: static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1324:36-1324:45: static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1326:50-1326:59: static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1328:54-1328:63: static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1338:55-1338:64: static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1340:49-1340:58: static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1354:51-1354:60: static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1356:50-1356:59: static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1370:48-1370:57: static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1384:46-1384:55: static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1386:47-1386:56: static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1388:47-1388:56: static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1390:51-1390:60: static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1392:50-1392:59: static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1394:55-1394:64: static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1396:45-1396:54: static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1398:51-1398:60: static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1400:51-1400:60: static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1415:36-1415:45: static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1417:47-1417:56: static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1484:48-1484:57: static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1538:53-1538:62: static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1564:46-1564:55: static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1566:46-1566:55: static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1568:46-1568:55: static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1570:46-1570:55: static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1572:49-1572:58: static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1586:49-1586:58: static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1600:56-1600:65: static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1602:55-1602:64: static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1604:55-1604:64: static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1606:55-1606:64: static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1608:55-1608:64: static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1610:53-1610:62: static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1612:54-1612:63: static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1614:57-1614:66: static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1616:57-1616:66: static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1618:57-1618:66: static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1620:57-1620:66: static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1622:45-1622:54: static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1636:50-1636:59: static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1638:55-1638:64: static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1652:55-1652:64: static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1666:55-1666:64: static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1680:55-1680:64: static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1694:55-1694:64: static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1702:54-1702:63: static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1704:58-1704:67: static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1718:55-1718:64: static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1720:59-1720:68: static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1734:53-1734:62: static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1736:57-1736:66: static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1744:54-1744:63: static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1746:58-1746:67: static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1765:38-1765:47: static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1767:55-1767:64: static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1769:45-1769:54: static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1771:48-1771:57: static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1785:54-1785:63: static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1787:54-1787:63: static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1789:51-1789:60: static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1791:51-1791:60: static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1793:56-1793:65: static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1795:56-1795:65: static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1797:54-1797:63: static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1799:54-1799:63: static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1801:55-1801:64: static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1810:55-1810:64: static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1818:53-1818:62: static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1820:53-1820:62: static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1822:51-1822:60: static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1836:50-1836:59: static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1851:51-1851:60: static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1853:54-1853:63: static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1855:49-1855:58: static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1857:51-1857:60: static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1862:47-1862:56: static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1864:48-1864:57: static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1866:48-1866:57: static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1868:62-1868:71: static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1870:51-1870:60: static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1872:58-1872:67: static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1874:50-1874:59: static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1876:49-1876:58: static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1878:55-1878:64: static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1880:60-1880:69: static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1882:59-1882:68: static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1884:49-1884:58: static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1886:55-1886:64: static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1888:55-1888:64: static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1890:59-1890:68: static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1892:52-1892:61: static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1894:56-1894:65: static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1896:66-1896:75: static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1898:54-1898:63: static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1908:36-1908:45: static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1910:43-1910:52: static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1912:43-1912:52: static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1914:43-1914:52: static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1916:47-1916:56: static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1918:47-1918:56: static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1920:47-1920:56: static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1922:44-1922:53: static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1924:40-1924:49: static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1926:41-1926:50: static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1928:46-1928:55: static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1930:44-1930:53: static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1932:42-1932:51: static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1934:43-1934:52: static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1936:45-1936:54: static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1938:43-1938:52: static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1940:43-1940:52: static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1942:44-1942:53: static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1944:45-1944:54: static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1946:45-1946:54: static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1948:45-1948:54: static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1950:47-1950:56: static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1952:46-1952:55: static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1954:39-1954:48: static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1956:43-1956:52: static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1958:39-1958:48: static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1960:43-1960:52: static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1962:44-1962:53: static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1964:44-1964:53: static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1966:43-1966:52: static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1968:45-1968:54: static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1970:47-1970:56: static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1972:44-1972:53: static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1974:43-1974:52: static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1976:46-1976:55: static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
• drivers/gpu/drm/msm/dsi/dsi.xml.h:448:37-448:46: static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
• drivers/gpu/drm/msm/dsi/dsi.xml.h:450:42-450:51: static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:126:44-126:53: static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:128:49-128:58: static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:130:49-130:58: static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:132:49-132:58: static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:134:49-134:58: static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:136:58-136:67: static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:138:53-138:62: static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:140:58-140:67: static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:142:60-142:69: static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:144:60-144:69: static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:146:58-146:67: static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:148:54-148:63: static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h:150:53-150:62: static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:117:44-117:53: static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:119:49-119:58: static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:127:49-127:58: static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:130:49-130:58: static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:132:49-132:58: static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:134:58-134:67: static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:136:53-136:62: static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:138:58-138:67: static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:146:58-146:67: static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:154:58-154:67: static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:162:58-162:67: static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:170:58-170:67: static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:178:58-178:67: static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:192:59-192:68: static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:200:59-200:68: static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:208:60-208:69: static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:210:60-210:69: static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:212:55-212:64: static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:56:44-56:53: static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:58:50-58:59: static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:60:50-60:59: static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:62:50-62:59: static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:64:50-64:59: static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:66:50-66:59: static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:68:58-68:67: static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:70:54-70:63: static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:72:55-72:64: static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:74:55-74:64: static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:56:44-56:53: static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:58:50-58:59: static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:60:50-60:59: static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:62:50-62:59: static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:64:50-64:59: static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:66:50-66:59: static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:68:58-68:67: static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:70:54-70:63: static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:72:55-72:64: static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:74:55-74:64: static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:56:49-56:58: static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:58:55-58:64: static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:60:55-60:64: static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:62:55-62:64: static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:64:63-64:72: static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:66:60-66:69: static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:68:60-68:69: static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h:160:43-160:52: static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h:162:48-162:57: static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h:164:48-164:57: static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h:166:48-166:57: static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h:168:57-168:66: static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h:170:52-170:61: static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h:172:53-172:62: static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
• drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h:174:52-174:61: static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:178:42-178:51: static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; }
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:182:42-182:51: static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; }
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:186:42-186:51: static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:188:37-188:55: static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:190:39-190:57: static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:198:39-198:57: static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:395:49-395:58: static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; }
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:397:53-397:62: static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; }

variable

Defined...

• fs/jffs2/compr_rubin.c:105:2-105:7: long i0, i1;
• fs/jffs2/compr_rubin.c:203:2-203:7: long i0, threshold;
• fs/jfs/jfs_dmap.c:3345:2-3345:14: int i, i0 = true, j, j0 = true, k, n;
• lib/crypto/curve25519-hacl64.c:193:3-193:7: u64 i0;
• lib/crypto/curve25519-hacl64.c:251:2-251:6: u64 i0;
• lib/crypto/curve25519-hacl64.c:607:2-607:6: u64 i0, i1, i2, i3, i4, output0, output1, output2, output3, output4;
• lib/crypto/curve25519-hacl64.c:677:2-677:6: u64 i0;