Symbol: i1

function parameter

Defined...

• drivers/connector/cn_queue.c:54:17-54:37: int cn_cb_equal(const struct cb_id *i1, const struct cb_id *i2)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:360:57-360:66: static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:362:60-362:69: static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:382:66-382:75: static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:384:66-384:75: static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:386:69-386:78: static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:388:69-388:78: static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:390:70-390:79: static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:392:70-392:79: static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:404:61-404:70: static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:406:65-406:74: static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:422:58-422:67: static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:424:62-424:71: static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:426:62-426:71: static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:428:66-428:75: static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:430:63-430:72: static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:432:67-432:76: static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:434:62-434:71: static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:436:66-436:75: static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:438:63-438:72: static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:440:67-440:76: static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:446:55-446:64: static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:448:59-448:68: static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:577:62-577:71: static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:579:66-579:75: static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:581:66-581:75: static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:583:70-583:79: static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:585:67-585:76: static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:587:71-587:80: static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:589:66-589:75: static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:591:70-591:79: static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:593:67-593:76: static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:595:71-595:80: static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:828:64-828:73: static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:830:68-830:77: static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:832:68-832:77: static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:834:72-834:81: static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:836:69-836:78: static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:838:73-838:82: static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:840:68-840:77: static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:842:72-842:81: static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:844:69-844:78: static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:846:73-846:82: static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:332:64-332:73: static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:334:68-334:77: static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:385:56-385:65: static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:387:60-387:69: static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:520:60-520:69: static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:522:64-522:73: static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:652:73-652:82: static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:654:77-654:86: static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:668:74-668:83: static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:670:78-670:87: static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:684:72-684:81: static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:686:76-686:85: static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:694:73-694:82: static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:696:77-696:86: static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:954:68-954:92: static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:956:71-956:95: static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:982:71-982:95: static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1008:79-1008:103: static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1129:55-1129:64: static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1131:63-1131:72: static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1153:64-1153:73: static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1155:64-1155:73: static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1157:70-1157:79: static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1159:70-1159:79: static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1161:71-1161:80: static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1163:71-1163:80: static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1165:70-1165:79: static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1167:70-1167:79: static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1169:71-1169:80: static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1171:71-1171:80: static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1702:67-1702:76: static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1704:71-1704:80: static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1718:68-1718:77: static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1720:72-1720:81: static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1734:66-1734:75: static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1736:70-1736:79: static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1744:67-1744:76: static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1746:71-1746:80: static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
• fs/fat/inode.c:1926:46-1926:60: int fat_flush_inodes(struct super_block *sb, struct inode *i1, struct inode *i2)
• fs/ntfs3/inode.c:1060:47-1060:61: int ntfs_flush_inodes(struct super_block *sb, struct inode *i1,
• fs/xfs/xfs_trace.h:3228:1-3228:1: DEFINE_REFCOUNT_DOUBLE_EXTENT_EVENT(xfs_refcount_merge_left_extent);
• fs/xfs/xfs_trace.h:3229:1-3229:1: DEFINE_REFCOUNT_DOUBLE_EXTENT_EVENT(xfs_refcount_merge_right_extent);
• fs/xfs/xfs_trace.h:3230:1-3230:1: DEFINE_REFCOUNT_DOUBLE_EXTENT_AT_EVENT(xfs_refcount_find_left_extent);
• fs/xfs/xfs_trace.h:3231:1-3231:1: DEFINE_REFCOUNT_DOUBLE_EXTENT_AT_EVENT(xfs_refcount_find_right_extent);
• fs/xfs/xfs_trace.h:3224:1-3224:1: DEFINE_REFCOUNT_TRIPLE_EXTENT_EVENT(xfs_refcount_merge_center_extents);
• include/sound/pcm_params.h:289:35-289:62: static inline int snd_interval_eq(const struct snd_interval *i1, const struct snd_interval *i2)

variable

Defined...

• drivers/isdn/mISDN/dsp_cmx.c:377:2-377:24: int memb = 0, i, ii, i1, i2;
• drivers/isdn/mISDN/l1oip_codec.c:312:2-312:6: int i1, i2, c, sample;
• drivers/md/dm-crypt.c:829:2-829:9: int i, i1, i2, i3;
• drivers/md/dm-crypt.c:860:2-860:9: int i, i1, i2, i3;
• drivers/md/dm-crypt.c:891:2-891:9: int i, i1, i2, i3;
• drivers/md/dm-crypt.c:922:2-922:9: int i, i1, i2, i3;
• fs/jffs2/compr_rubin.c:105:2-105:11: long i0, i1;
• lib/crypto/curve25519-hacl64.c:194:3-194:7: u64 i1;
• lib/crypto/curve25519-hacl64.c:252:2-252:6: u64 i1;
• lib/crypto/curve25519-hacl64.c:607:2-607:10: u64 i0, i1, i2, i3, i4, output0, output1, output2, output3, output4;
• lib/crypto/curve25519-hacl64.c:678:2-678:6: u64 i1;
• sound/soc/generic/simple-card-utils.c:286:2-286:6: int i1, i2, i;