Symbol: val

function parameter

Defined...

• arch/x86/boot/compressed/kaslr.c:229:46-229:52: static void parse_gb_huge_pages(char *param, char *val)
• arch/x86/boot/compressed/sev.c:68:39-68:43: static inline void sev_es_wr_ghcb_msr(u64 val)
• arch/x86/coco/core.c:113:14-113:18: u64 cc_mkenc(u64 val)
• arch/x86/coco/core.c:135:14-135:18: u64 cc_mkdec(u64 val)
• arch/x86/coco/tdx/tdx.c:356:53-356:68: static bool mmio_read(int size, unsigned long addr, unsigned long *val)
• arch/x86/coco/tdx/tdx.c:373:54-373:68: static bool mmio_write(int size, unsigned long addr, unsigned long val)
• arch/x86/events/amd/brs.c:44:48-44:52: static __always_inline void set_debug_extn_cfg(u64 val)
• arch/x86/events/amd/lbr.c:62:68-62:72: static __always_inline void amd_pmu_lbr_set_from(unsigned int idx, u64 val)
• arch/x86/events/amd/lbr.c:67:66-67:70: static __always_inline void amd_pmu_lbr_set_to(unsigned int idx, u64 val)
• arch/x86/events/intel/ds.c:241:38-241:43: static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
• arch/x86/events/intel/lbr.c:249:38-249:42: inline u64 lbr_from_signext_quirk_wr(u64 val)
• arch/x86/events/intel/lbr.c:269:38-269:42: static u64 lbr_from_signext_quirk_rd(u64 val)
• arch/x86/events/intel/lbr.c:281:58-281:62: static __always_inline void wrlbr_from(unsigned int idx, u64 val)
• arch/x86/events/intel/lbr.c:287:56-287:60: static __always_inline void wrlbr_to(unsigned int idx, u64 val)
• arch/x86/events/intel/lbr.c:292:58-292:62: static __always_inline void wrlbr_info(unsigned int idx, u64 val)
• arch/x86/hyperv/hv_apic.c:75:36-75:40: static void hv_apic_write(u32 reg, u32 val)
• arch/x86/hyperv/hv_spinlock.c:26:37-26:40: static void hv_qlock_wait(u8 *byte, u8 val)
• arch/x86/hyperv/ivm.c:116:32-116:36: static inline void wr_ghcb_msr(u64 val)
• arch/x86/hyperv/ivm.c:385:39-385:43: static void hv_tdx_msr_write(u64 msr, u64 val)
• arch/x86/hyperv/ivm.c:399:38-399:43: static void hv_tdx_msr_read(u64 msr, u64 *val)
• arch/x86/include/asm/apic.h:400:49-400:53: static __always_inline void apic_write(u32 reg, u32 val)
• arch/x86/include/asm/ibt.h:68:29-68:33: static inline bool is_endbr(u32 val)
• arch/x86/include/asm/io.h:64:1-64:1: build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
• arch/x86/include/asm/io.h:65:1-65:1: build_mmio_write(writew, "w", unsigned short, "r", :"memory")
• arch/x86/include/asm/io.h:66:1-66:1: build_mmio_write(writel, "l", unsigned int, "r", :"memory")
• arch/x86/include/asm/io.h:68:1-68:1: build_mmio_write(__writeb, "b", unsigned char, "q", )
• arch/x86/include/asm/io.h:69:1-69:1: build_mmio_write(__writew, "w", unsigned short, "r", )
• arch/x86/include/asm/io.h:70:1-70:1: build_mmio_write(__writel, "l", unsigned int, "r", )
• arch/x86/include/asm/io.h:96:1-96:1: build_mmio_write(writeq, "q", u64, "r", :"memory")
• arch/x86/include/asm/io.h:97:1-97:1: build_mmio_write(__writeq, "q", u64, "r", )
• arch/x86/include/asm/msr-trace.h:21:1-21:1: DECLARE_EVENT_CLASS(msr_trace_class,
• arch/x86/include/asm/msr-trace.h:40:1-40:1: DEFINE_EVENT(msr_trace_class, read_msr,
• arch/x86/include/asm/msr-trace.h:45:1-45:1: DEFINE_EVENT(msr_trace_class, write_msr,
• arch/x86/include/asm/msr-trace.h:50:1-50:1: DEFINE_EVENT(msr_trace_class, rdpmc,
• arch/x86/include/asm/msr.h:303:40-303:44: static inline int wrmsrl_safe(u32 msr, u64 val)
• arch/x86/include/asm/nospec-branch.h:490:46-490:50: void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
• arch/x86/include/asm/numachip/numachip_csr.h:50:53-50:66: static inline void write_lcsr(unsigned long offset, unsigned int val)
• arch/x86/include/asm/numachip/numachip_csr.h:83:65-83:69: static inline void numachip2_write32_lcsr(unsigned long offset, u32 val)
• arch/x86/include/asm/numachip/numachip_csr.h:88:65-88:69: static inline void numachip2_write64_lcsr(unsigned long offset, u64 val)
• arch/x86/include/asm/paravirt.h:127:42-127:56: static __always_inline void set_debugreg(unsigned long val, int reg)
• arch/x86/include/asm/paravirt.h:227:41-227:45: static inline void wrmsrl(unsigned msr, u64 val)
• arch/x86/include/asm/paravirt.h:390:27-390:36: static inline pte_t __pte(pteval_t val)
• arch/x86/include/asm/paravirt.h:403:27-403:36: static inline pgd_t __pgd(pgdval_t val)
• arch/x86/include/asm/paravirt.h:444:27-444:36: static inline pmd_t __pmd(pmdval_t val)
• arch/x86/include/asm/paravirt.h:462:27-462:36: static inline pud_t __pud(pudval_t val)
• arch/x86/include/asm/paravirt.h:492:27-492:36: static inline p4d_t __p4d(p4dval_t val)
• arch/x86/include/asm/paravirt.h:584:8-584:12: u32 val)
• arch/x86/include/asm/paravirt.h:596:46-596:49: static __always_inline void pv_wait(u8 *ptr, u8 val)
• arch/x86/include/asm/pci_x86.h:223:58-223:61: static inline void mmio_config_writeb(void __iomem *pos, u8 val)
• arch/x86/include/asm/pci_x86.h:228:58-228:62: static inline void mmio_config_writew(void __iomem *pos, u16 val)
• arch/x86/include/asm/pci_x86.h:233:58-233:62: static inline void mmio_config_writel(void __iomem *pos, u32 val)
• arch/x86/include/asm/pgtable-invert.h:16:39-16:43: static inline bool __pte_needs_invert(u64 val)
• arch/x86/include/asm/pgtable-invert.h:22:33-22:37: static inline u64 protnone_mask(u64 val)
• arch/x86/include/asm/pgtable-invert.h:27:51-27:55: static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask)
• arch/x86/include/asm/pgtable_types.h:325:37-325:46: static inline pgd_t native_make_pgd(pgdval_t val)
• arch/x86/include/asm/pgtable_types.h:343:37-343:46: static inline p4d_t native_make_p4d(pudval_t val)
• arch/x86/include/asm/pgtable_types.h:369:37-369:46: static inline pud_t native_make_pud(pmdval_t val)
• arch/x86/include/asm/pgtable_types.h:393:37-393:46: static inline pmd_t native_make_pmd(pmdval_t val)
• arch/x86/include/asm/pgtable_types.h:468:37-468:46: static inline pte_t native_make_pte(pteval_t val)
• arch/x86/include/asm/pgtable_types.h:494:46-494:58: static inline pgprotval_t protval_4k_2_large(pgprotval_t val)
• arch/x86/include/asm/pgtable_types.h:503:46-503:58: static inline pgprotval_t protval_large_2_4k(pgprotval_t val)
• arch/x86/include/asm/preempt.h:78:49-78:53: static __always_inline void __preempt_count_add(int val)
• arch/x86/include/asm/preempt.h:83:49-83:53: static __always_inline void __preempt_count_sub(int val)
• arch/x86/include/asm/ptrace.h:213:3-213:17: unsigned long val)
• arch/x86/include/asm/ptrace.h:229:3-229:17: unsigned long val)
• arch/x86/include/asm/qspinlock.h:49:70-49:74: static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
• arch/x86/include/asm/resctrl.h:82:55-82:68: static inline unsigned int resctrl_arch_round_mon_val(unsigned int val)
• arch/x86/include/asm/sev.h:69:30-69:34: static inline u64 lower_bits(u64 val, unsigned int bits)
• arch/x86/include/asm/special_insns.h:40:46-40:60: static __always_inline void native_write_cr2(unsigned long val)
• arch/x86/include/asm/special_insns.h:52:37-52:51: static inline void native_write_cr3(unsigned long val)
• arch/x86/include/asm/special_insns.h:206:57-206:61: static inline int write_user_shstk_64(u64 __user *addr, u64 val)
• arch/x86/include/asm/syscall.h:76:21-76:26: int error, long val)
• arch/x86/include/asm/text-patching.h:151:46-151:60: void int3_emulate_push(struct pt_regs *regs, unsigned long val)
• arch/x86/include/asm/uv/uv_hub.h:569:75-569:89: static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
• arch/x86/include/asm/uv/uv_hub.h:589:75-589:89: static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
• arch/x86/include/asm/uv/uv_hub.h:599:74-599:88: static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
• arch/x86/include/asm/uv/uv_hub.h:623:61-623:75: static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
• arch/x86/include/asm/uv/uv_hub.h:633:62-633:76: static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
• arch/x86/include/asm/xen/page.h:93:61-93:75: static inline int xen_safe_write_ulong(unsigned long *addr, unsigned long val)
• arch/x86/include/asm/xen/page.h:107:11-107:26: unsigned long *val)
• arch/x86/include/uapi/asm/swab.h:8:55-8:61: static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
• arch/x86/include/uapi/asm/swab.h:15:55-15:61: static inline __attribute_const__ __u64 __arch_swab64(__u64 val)
• arch/x86/kernel/acpi/cppc.c:35:51-35:56: int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
• arch/x86/kernel/acpi/cppc.c:50:52-50:56: int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
• arch/x86/kernel/alternative.c:1486:52-1486:66: int3_exception_notify(struct notifier_block *self, unsigned long val, void *data)
• arch/x86/kernel/apic/apic_noop.c:40:38-40:42: static void noop_apic_write(u32 reg, u32 val)
• arch/x86/kernel/apic/apic_numachip.c:64:50-64:63: static void numachip1_apic_icr_write(int apicid, unsigned int val)
• arch/x86/kernel/apic/apic_numachip.c:69:50-69:63: static void numachip2_apic_icr_write(int apicid, unsigned int val)
• arch/x86/kernel/cpu/amd.c:136:49-136:68: static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
• arch/x86/kernel/cpu/bugs.c:69:30-69:34: static void update_spec_ctrl(u64 val)
• arch/x86/kernel/cpu/bugs.c:79:28-79:32: void update_spec_ctrl_cond(u64 val)
• arch/x86/kernel/cpu/cacheinfo.c:1144:33-1144:38: void set_cache_aps_delayed_init(bool val)
• arch/x86/kernel/cpu/common.c:409:23-409:37: void native_write_cr0(unsigned long val)
• arch/x86/kernel/cpu/common.c:428:36-428:50: void __no_profile native_write_cr4(unsigned long val)
• arch/x86/kernel/cpu/common.c:2060:26-2060:40: static void wrmsrl_cstar(unsigned long val)
• arch/x86/kernel/cpu/mce/core.c:540:58-540:72: static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
• arch/x86/kernel/cpu/mce/core.c:563:58-563:72: static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
• arch/x86/kernel/cpu/mce/core.c:590:60-590:74: static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
• arch/x86/kernel/cpu/mce/core.c:2828:39-2828:44: static int fake_panic_get(void *data, u64 *val)
• arch/x86/kernel/cpu/mce/core.c:2834:39-2834:43: static int fake_panic_set(void *data, u64 val)
• arch/x86/kernel/cpu/mce/dev-mcelog.c:36:51-36:65: static int dev_mce_log(struct notifier_block *nb, unsigned long val,
• arch/x86/kernel/cpu/mce/inject.c:75:1-75:1: MCE_INJECT_SET(status);
• arch/x86/kernel/cpu/mce/inject.c:76:1-76:1: MCE_INJECT_SET(misc);
• arch/x86/kernel/cpu/mce/inject.c:77:1-77:1: MCE_INJECT_SET(addr);
• arch/x86/kernel/cpu/mce/inject.c:78:1-78:1: MCE_INJECT_SET(synd);
• arch/x86/kernel/cpu/mce/inject.c:89:1-89:1: MCE_INJECT_GET(status);
• arch/x86/kernel/cpu/mce/inject.c:90:1-90:1: MCE_INJECT_GET(misc);
• arch/x86/kernel/cpu/mce/inject.c:91:1-91:1: MCE_INJECT_GET(addr);
• arch/x86/kernel/cpu/mce/inject.c:92:1-92:1: MCE_INJECT_GET(synd);
• arch/x86/kernel/cpu/mce/inject.c:93:1-93:1: MCE_INJECT_GET(ipid);
• arch/x86/kernel/cpu/mce/inject.c:400:1-400:1: MCE_INJECT_GET(extcpu);
• arch/x86/kernel/cpu/mce/inject.c:633:1-633:1: MCE_INJECT_GET(bank);
• arch/x86/kernel/cpu/mce/inject.c:101:37-101:41: static int inj_ipid_set(void *data, u64 val)
• arch/x86/kernel/cpu/mce/inject.c:294:56-294:70: static int mce_inject_raise(struct notifier_block *nb, unsigned long val,
• arch/x86/kernel/cpu/mce/inject.c:402:39-402:43: static int inj_extcpu_set(void *data, u64 val)
• arch/x86/kernel/cpu/mce/inject.c:582:37-582:41: static int inj_bank_set(void *data, u64 val)
• arch/x86/kernel/cpu/mshyperv.c:262:27-262:40: static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs)
• arch/x86/kernel/cpu/resctrl/monitor.c:130:53-130:67: static inline u64 get_corrected_mbm_count(u32 rmid, unsigned long val)
• arch/x86/kernel/cpu/resctrl/monitor.c:149:65-149:70: static int __rmid_read(u32 rmid, enum resctrl_event_id eventid, u64 *val)
• arch/x86/kernel/cpu/resctrl/monitor.c:233:48-233:53: u32 rmid, enum resctrl_event_id eventid, u64 *val)
• arch/x86/kernel/cpu/resctrl/rdtgroup.c:1551:41-1551:45: struct rdt_domain *d, u32 evtid, u32 val)
• arch/x86/kernel/hw_breakpoint.c:581:34-581:48: struct notifier_block *unused, unsigned long val, void *data)
• arch/x86/kernel/kprobes/opt.c:93:56-93:70: static void synthesize_set_arg1(kprobe_opcode_t *addr, unsigned long val)
• arch/x86/kernel/kvm.c:1040:31-1040:34: static void kvm_wait(u8 *ptr, u8 val)
• arch/x86/kernel/msr.c:297:29-297:41: static int set_allow_writes(const char *val, const struct kernel_param *cp)
• arch/x86/kernel/nmi_selftest.c:37:30-37:43: static int __init nmi_unk_cb(unsigned int val, struct pt_regs *regs)
• arch/x86/kernel/nmi_selftest.c:55:41-55:54: static int __init test_nmi_ipi_callback(unsigned int val, struct pt_regs *regs)
• arch/x86/kernel/paravirt.c:147:41-147:55: static noinstr void pv_native_write_cr2(unsigned long val)
• arch/x86/kernel/paravirt.c:157:55-157:69: static noinstr void pv_native_set_debugreg(int regno, unsigned long val)
• arch/x86/kernel/process.c:319:18-319:31: int set_tsc_mode(unsigned int val)
• arch/x86/kernel/ptrace.c:670:11-670:25: unsigned long val)
• arch/x86/kernel/ptrace.c:971:64-971:69: static int getreg32(struct task_struct *child, unsigned regno, u32 *val)
• arch/x86/kernel/reboot.c:846:31-846:44: static int crash_nmi_callback(unsigned int val, struct pt_regs *regs)
• arch/x86/kernel/rtc.c:94:21-94:35: void rtc_cmos_write(unsigned char val, unsigned char addr)
• arch/x86/kernel/sev.c:262:48-262:52: static __always_inline void sev_es_wr_ghcb_msr(u64 val)
• arch/x86/kernel/smp.c:121:34-121:47: static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
• arch/x86/kernel/tsc.c:526:34-526:48: static inline int pit_verify_msb(unsigned char val)
• arch/x86/kernel/tsc.c:533:34-533:48: static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
• arch/x86/kernel/tsc.c:1018:61-1018:75: static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
• arch/x86/kernel/unwind_orc.c:401:8-401:23: unsigned long *val)
• arch/x86/kernel/unwind_orc.c:448:7-448:22: unsigned long *val)
• arch/x86/kernel/uprobes.c:526:53-526:67: static int emulate_push_stack(struct pt_regs *regs, unsigned long val)
• arch/x86/kernel/uprobes.c:1001:63-1001:77: int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
• arch/x86/kvm/debugfs.c:15:50-15:55: static int vcpu_get_timer_advance_ns(void *data, u64 *val)
• arch/x86/kvm/debugfs.c:24:44-24:49: static int vcpu_get_guest_mode(void *data, u64 *val)
• arch/x86/kvm/debugfs.c:33:44-33:49: static int vcpu_get_tsc_offset(void *data, u64 *val)
• arch/x86/kvm/debugfs.c:42:51-42:56: static int vcpu_get_tsc_scaling_ratio(void *data, u64 *val)
• arch/x86/kvm/debugfs.c:51:55-51:60: static int vcpu_get_tsc_scaling_frac_bits(void *data, u64 *val)
• arch/x86/kvm/emulate.c:492:49-492:53: static void assign_register(unsigned long *reg, u64 val, int bytes)
• arch/x86/kvm/i8254.c:54:60-54:64: static void pit_set_gate(struct kvm_pit *pit, int channel, u32 val)
• arch/x86/kvm/i8254.c:322:51-322:55: static void create_pit_timer(struct kvm_pit *pit, u32 val, int is_period)
• arch/x86/kvm/i8254.c:365:62-365:66: static void pit_load_count(struct kvm_pit *pit, int channel, u32 val)
• arch/x86/kvm/i8254.c:403:59-403:63: void kvm_pit_load_count(struct kvm_pit *pit, int channel, u32 val,
• arch/x86/kvm/i8259.c:307:54-307:58: static void pic_ioport_write(void *opaque, u32 addr, u32 val)
• arch/x86/kvm/i8259.c:444:45-444:49: static void elcr_ioport_write(void *opaque, u32 val)
• arch/x86/kvm/i8259.c:457:26-457:38: gpa_t addr, int len, const void *val)
• arch/x86/kvm/i8259.c:491:31-491:37: gpa_t addr, int len, void *val)
• arch/x86/kvm/i8259.c:522:32-522:44: gpa_t addr, int len, const void *val)
• arch/x86/kvm/i8259.c:529:31-529:37: gpa_t addr, int len, void *val)
• arch/x86/kvm/i8259.c:536:31-536:43: gpa_t addr, int len, const void *val)
• arch/x86/kvm/i8259.c:543:30-543:36: gpa_t addr, int len, void *val)
• arch/x86/kvm/i8259.c:550:30-550:42: gpa_t addr, int len, const void *val)
• arch/x86/kvm/i8259.c:557:29-557:35: gpa_t addr, int len, void *val)
• arch/x86/kvm/ioapic.c:316:62-316:66: static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
• arch/x86/kvm/ioapic.c:608:26-608:32: gpa_t addr, int len, void *val)
• arch/x86/kvm/ioapic.c:650:27-650:39: gpa_t addr, int len, const void *val)
• arch/x86/kvm/kvm_cache_regs.h:28:1-28:1: BUILD_KVM_GPR_ACCESSORS(rax, RAX)
• arch/x86/kvm/kvm_cache_regs.h:29:1-29:1: BUILD_KVM_GPR_ACCESSORS(rbx, RBX)
• arch/x86/kvm/kvm_cache_regs.h:30:1-30:1: BUILD_KVM_GPR_ACCESSORS(rcx, RCX)
• arch/x86/kvm/kvm_cache_regs.h:31:1-31:1: BUILD_KVM_GPR_ACCESSORS(rdx, RDX)
• arch/x86/kvm/kvm_cache_regs.h:32:1-32:1: BUILD_KVM_GPR_ACCESSORS(rbp, RBP)
• arch/x86/kvm/kvm_cache_regs.h:33:1-33:1: BUILD_KVM_GPR_ACCESSORS(rsi, RSI)
• arch/x86/kvm/kvm_cache_regs.h:34:1-34:1: BUILD_KVM_GPR_ACCESSORS(rdi, RDI)
• arch/x86/kvm/kvm_cache_regs.h:36:1-36:1: BUILD_KVM_GPR_ACCESSORS(r8, R8)
• arch/x86/kvm/kvm_cache_regs.h:37:1-37:1: BUILD_KVM_GPR_ACCESSORS(r9, R9)
• arch/x86/kvm/kvm_cache_regs.h:38:1-38:1: BUILD_KVM_GPR_ACCESSORS(r10, R10)
• arch/x86/kvm/kvm_cache_regs.h:39:1-39:1: BUILD_KVM_GPR_ACCESSORS(r11, R11)
• arch/x86/kvm/kvm_cache_regs.h:40:1-40:1: BUILD_KVM_GPR_ACCESSORS(r12, R12)
• arch/x86/kvm/kvm_cache_regs.h:41:1-41:1: BUILD_KVM_GPR_ACCESSORS(r13, R13)
• arch/x86/kvm/kvm_cache_regs.h:42:1-42:1: BUILD_KVM_GPR_ACCESSORS(r14, R14)
• arch/x86/kvm/kvm_cache_regs.h:43:1-43:1: BUILD_KVM_GPR_ACCESSORS(r15, R15)
• arch/x86/kvm/kvm_cache_regs.h:107:8-107:22: unsigned long val)
• arch/x86/kvm/kvm_cache_regs.h:121:57-121:71: static inline void kvm_rip_write(struct kvm_vcpu *vcpu, unsigned long val)
• arch/x86/kvm/kvm_cache_regs.h:131:57-131:71: static inline void kvm_rsp_write(struct kvm_vcpu *vcpu, unsigned long val)
• arch/x86/kvm/lapic.c:71:65-71:69: static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)
• arch/x86/kvm/lapic.c:76:75-76:79: static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
• arch/x86/kvm/lapic.c:92:72-92:76: static __always_inline void __kvm_lapic_set_reg64(char *regs, int reg, u64 val)
• arch/x86/kvm/lapic.c:99:16-99:20: int reg, u64 val)
• arch/x86/kvm/lapic.c:485:58-485:62: static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
• arch/x86/kvm/lapic.c:518:61-518:65: static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val)
• arch/x86/kvm/lapic.c:880:51-880:54: static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
• arch/x86/kvm/lapic.c:887:51-887:55: static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
• arch/x86/kvm/lapic.c:2253:65-2253:69: static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
• arch/x86/kvm/mmu/mmu.c:6814:33-6814:38: static void __set_nx_huge_pages(bool val)
• arch/x86/kvm/mmu/mmu.c:6819:30-6819:42: static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
• arch/x86/kvm/mmu/mmu.c:6978:45-6978:57: static int set_nx_huge_pages_recovery_param(const char *val, const struct kernel_param *kp)
• arch/x86/kvm/pmu.h:77:59-77:63: static inline void pmc_write_counter(struct kvm_pmc *pmc, u64 val)
• arch/x86/kvm/svm/svm.c:2618:10-2618:24: unsigned long val)
• arch/x86/kvm/trace.h:258:1-258:1: TRACE_EVENT(kvm_apic,
• arch/x86/kvm/trace.h:457:1-457:1: TRACE_EVENT(kvm_cr,
• arch/x86/kvm/vmx/hyperv.c:569:9-569:13: u32 val)
• arch/x86/kvm/vmx/nested.h:251:37-251:41: static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
• arch/x86/kvm/vmx/nested.h:256:66-256:80: static inline bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
• arch/x86/kvm/vmx/nested.h:270:65-270:79: static inline bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
• arch/x86/kvm/vmx/nested.h:278:60-278:74: static inline bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
• arch/x86/kvm/vmx/vmx.c:5385:50-5385:64: static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
• arch/x86/kvm/vmx/vmx.c:5411:50-5411:64: static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
• arch/x86/kvm/vmx/vmx.c:5602:48-5602:62: static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
• arch/x86/kvm/vmx/vmx.h:607:1-607:1: BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32)
• arch/x86/kvm/vmx/vmx.h:607:1-607:1: BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32)
• arch/x86/kvm/vmx/vmx.h:607:1-607:1: BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32)
• arch/x86/kvm/vmx/vmx.h:608:1-608:1: BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32)
• arch/x86/kvm/vmx/vmx.h:611:1-611:1: BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32)
• arch/x86/kvm/vmx/vmx.h:608:1-608:1: BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32)
• arch/x86/kvm/vmx/vmx.h:611:1-611:1: BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32)
• arch/x86/kvm/vmx/vmx.h:608:1-608:1: BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32)
• arch/x86/kvm/vmx/vmx.h:609:1-609:1: BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32)
• arch/x86/kvm/vmx/vmx.h:609:1-609:1: BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32)
• arch/x86/kvm/vmx/vmx.h:609:1-609:1: BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32)
• arch/x86/kvm/vmx/vmx.h:611:1-611:1: BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32)
• arch/x86/kvm/vmx/vmx.h:610:1-610:1: BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32)
• arch/x86/kvm/vmx/vmx.h:610:1-610:1: BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32)
• arch/x86/kvm/vmx/vmx.h:612:1-612:1: BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64)
• arch/x86/kvm/vmx/vmx.h:610:1-610:1: BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32)
• arch/x86/kvm/vmx/vmx.h:612:1-612:1: BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64)
• arch/x86/kvm/vmx/vmx.h:612:1-612:1: BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64)
• arch/x86/kvm/x86.c:1373:47-1373:61: int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
• arch/x86/kvm/x86.c:1402:48-1402:63: void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
• arch/x86/kvm/x86.c:7339:51-7339:57: static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
• arch/x86/kvm/x86.c:7372:17-7372:23: gva_t addr, void *val, unsigned int bytes,
• arch/x86/kvm/x86.c:7399:23-7399:29: gva_t addr, void *val, unsigned int bytes,
• arch/x86/kvm/x86.c:7417:21-7417:27: gva_t addr, void *val, unsigned int bytes,
• arch/x86/kvm/x86.c:7431:52-7431:58: static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
• arch/x86/kvm/x86.c:7461:74-7461:80: static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
• arch/x86/kvm/x86.c:7477:68-7477:74: int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
• arch/x86/kvm/x86.c:7566:4-7566:16: const void *val, int bytes)
• arch/x86/kvm/x86.c:7589:48-7589:54: static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
• arch/x86/kvm/x86.c:7602:4-7602:10: void *val, int bytes)
• arch/x86/kvm/x86.c:7608:5-7608:11: void *val, int bytes)
• arch/x86/kvm/x86.c:7613:68-7613:74: static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
• arch/x86/kvm/x86.c:7620:6-7620:12: void *val, int bytes)
• arch/x86/kvm/x86.c:7627:7-7627:13: void *val, int bytes)
• arch/x86/kvm/x86.c:7649:60-7649:66: static int emulator_read_write_onepage(unsigned long addr, void *val,
• arch/x86/kvm/x86.c:7702:4-7702:10: void *val, unsigned int bytes,
• arch/x86/kvm/x86.c:7756:7-7756:13: void *val,
• arch/x86/kvm/x86.c:7766:8-7766:20: const void *val,
• arch/x86/kvm/x86.c:7902:34-7902:40: unsigned short port, void *val, unsigned int count)
• arch/x86/kvm/x86.c:7911:61-7911:67: static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
• arch/x86/kvm/x86.c:7921:40-7921:46: int size, unsigned short port, void *val,
• arch/x86/kvm/x86.c:7941:29-7941:41: unsigned short port, const void *val,
• arch/x86/kvm/x86.c:7950:10-7950:22: const void *val, unsigned int count)
• arch/x86/kvm/x86.c:8044:67-8044:73: static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
• arch/x86/kvm/x86.c:8276:77-8276:83: static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
• arch/x86/kvm/x86.c:9297:65-9297:79: static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
• arch/x86/kvm/x86.h:60:46-60:59: static inline unsigned int __grow_ple_window(unsigned int val,
• arch/x86/kvm/x86.h:76:48-76:61: static inline unsigned int __shrink_ple_window(unsigned int val,
• arch/x86/kvm/x86.h:281:21-281:35: int reg, unsigned long val)
• arch/x86/lib/misc.c:9:16-9:20: int num_digits(int val)
• arch/x86/lib/msr.c:123:43-123:47: void do_trace_write_msr(unsigned int msr, u64 val, int failed)
• arch/x86/lib/msr.c:130:42-130:46: void do_trace_read_msr(unsigned int msr, u64 val, int failed)
• arch/x86/lib/msr.c:137:39-137:43: void do_trace_rdpmc(unsigned counter, u64 val, int failed)
• arch/x86/mm/dump_pagetables.c:251:67-251:71: static void effective_prot(struct ptdump_state *pt_st, int level, u64 val)
• arch/x86/mm/dump_pagetables.c:275:9-275:13: u64 val)
• arch/x86/mm/kmmio.c:591:47-591:61: kmmio_die_notifier(struct notifier_block *nb, unsigned long val, void *args)
• arch/x86/mm/pat/set_memory.c:544:45-544:57: static inline bool conflicts(pgprot_t prot, pgprotval_t val)
• arch/x86/mm/pat/set_memory.c:549:63-549:75: static inline void check_conflict(int warnlvl, pgprot_t prot, pgprotval_t val,
• arch/x86/pci/amd_bus.c:54:44-54:48: static inline resource_size_t cap_resource(u64 val)
• arch/x86/pci/common.c:41:25-41:30: int reg, int len, u32 *val)
• arch/x86/pci/common.c:51:25-51:29: int reg, int len, u32 val)
• arch/x86/pci/early.c:36:9-36:13: u32 val)
• arch/x86/pci/early.c:42:65-42:68: void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val)
• arch/x86/pci/early.c:48:63-48:67: void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val)
• arch/x86/pci/intel_mid_pci.c:98:26-98:30: int reg, int len, u32 val, int offset)
• arch/x86/pci/irq.c:330:53-330:56: static void write_pc_conf_nybble(u8 base, u8 index, u8 val)
• arch/x86/pci/irq.c:422:15-422:28: unsigned nr, unsigned int val)
• arch/x86/platform/intel/iosf_mbi.c:451:32-451:37: static int mcr_get(void *data, u64 *val)
• arch/x86/platform/intel/iosf_mbi.c:457:32-457:36: static int mcr_set(void *data, u64 val)
• arch/x86/platform/uv/uv_nmi.c:118:30-118:42: static int param_set_local64(const char *val, const struct kernel_param *kp)
• arch/x86/platform/uv/uv_nmi.c:201:29-201:41: static int param_set_action(const char *val, const struct kernel_param *kp)
• arch/x86/xen/apic.c:73:37-73:41: static void xen_apic_write(u32 reg, u32 val)
• arch/x86/xen/enlighten_pv.c:366:47-366:61: static noinstr void xen_set_debugreg(int reg, unsigned long val)
• arch/x86/xen/enlighten_pv.c:770:41-770:58: static int cvt_gate_to_trap(int vector, const gate_desc *val,
• arch/x86/xen/mmu_pv.c:226:43-226:49: static void xen_set_pmd_hyper(pmd_t *ptr, pmd_t val)
• arch/x86/xen/mmu_pv.c:244:37-244:43: static void xen_set_pmd(pmd_t *ptr, pmd_t val)
• arch/x86/xen/mmu_pv.c:332:32-332:41: static pteval_t pte_mfn_to_pfn(pteval_t val)
• arch/x86/xen/mmu_pv.c:348:32-348:41: static pteval_t pte_pfn_to_mfn(pteval_t val)
• arch/x86/xen/mmu_pv.c:409:43-409:49: static void xen_set_pud_hyper(pud_t *ptr, pud_t val)
• arch/x86/xen/mmu_pv.c:427:37-427:43: static void xen_set_pud(pud_t *ptr, pud_t val)
• arch/x86/xen/mmu_pv.c:478:45-478:51: static void __xen_set_p4d_hyper(p4d_t *ptr, p4d_t val)
• arch/x86/xen/mmu_pv.c:494:50-494:56: static void __init xen_set_p4d_hyper(p4d_t *ptr, p4d_t val)
• arch/x86/xen/mmu_pv.c:507:37-507:43: static void xen_set_p4d(p4d_t *ptr, p4d_t val)
• arch/x86/xen/pmu.c:198:53-198:58: static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
• arch/x86/xen/pmu.c:261:51-261:56: static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
• arch/x86/xen/pmu.c:302:52-302:62: static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_read,
• arch/x86/xen/pmu.c:317:37-317:47: bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
• arch/x86/xen/pmu.c:408:21-408:30: int pmu_apic_update(uint32_t val)
• arch/x86/xen/spinlock.c:37:38-37:41: static void xen_qlock_wait(u8 *byte, u8 val)
• block/bfq-cgroup.c:44:56-44:65: static inline void bfq_stat_add(struct bfq_stat *stat, uint64_t val)
• block/bfq-cgroup.c:1074:9-1074:13: u64 val)
• block/blk-cgroup-rwstat.h:62:23-62:32: blk_opf_t opf, uint64_t val)
• block/blk-cgroup.c:610:32-610:36: struct cftype *cftype, u64 val)
• block/blk-iolatency.c:787:63-787:67: static void iolatency_set_min_lat_nsec(struct blkcg_gq *blkg, u64 val)
• block/blk-mq.h:283:3-283:7: int val)
• block/blk-wbt.c:508:47-508:51: void wbt_set_min_lat(struct request_queue *q, u64 val)
• block/disk-events.c:405:43-405:55: static int disk_events_set_dfl_poll_msecs(const char *val,
• block/ioctl.c:197:52-197:67: static int put_ushort(unsigned short __user *argp, unsigned short val)
• block/ioctl.c:202:38-202:42: static int put_int(int __user *argp, int val)
• block/ioctl.c:207:48-207:61: static int put_uint(unsigned int __user *argp, unsigned int val)
• block/ioctl.c:212:40-212:45: static int put_long(long __user *argp, long val)
• block/ioctl.c:217:50-217:64: static int put_ulong(unsigned long __user *argp, unsigned long val)
• block/ioctl.c:222:38-222:42: static int put_u64(u64 __user *argp, u64 val)
• block/ioctl.c:228:56-228:61: static int compat_put_long(compat_long_t __user *argp, long val)
• block/ioctl.c:233:58-233:73: static int compat_put_ulong(compat_ulong_t __user *argp, compat_ulong_t val)
• crypto/api.c:301:27-301:41: int crypto_probing_notify(unsigned long val, void *v)
• crypto/asymmetric_keys/public_key.c:148:35-148:39: static u8 *pkey_pack_u32(u8 *dst, u32 val)
• crypto/dh.c:36:61-36:65: static int _compute_val(const struct dh_ctx *ctx, MPI base, MPI val)
• crypto/dh.c:334:57-334:61: static u64 __add_u64_to_be(__be64 *dst, unsigned int n, u64 val)
• crypto/drbg.c:284:37-284:43: static inline void drbg_cpu_to_be32(__u32 val, unsigned char *buf)
• crypto/internal.h:198:34-198:48: static inline void crypto_notify(unsigned long val, void *v)
• crypto/michael_mic.c:28:25-28:29: static inline u32 xswap(u32 val)
• drivers/accel/habanalabs/common/debugfs.c:24:29-24:34: u8 i2c_reg, u8 i2c_len, u64 *val)
• drivers/accel/habanalabs/common/debugfs.c:56:29-56:33: u8 i2c_reg, u8 i2c_len, u64 val)
• drivers/accel/habanalabs/common/debugfs.c:753:3-753:8: u64 *val, enum debugfs_access_type acc_type, bool *found)
• drivers/accel/habanalabs/common/debugfs.c:773:66-773:71: static void hl_access_host_mem(struct hl_device *hdev, u64 addr, u64 *val,
• drivers/accel/habanalabs/common/debugfs.c:798:60-798:65: static int hl_access_mem(struct hl_device *hdev, u64 addr, u64 *val,
• drivers/accel/habanalabs/common/device.c:67:66-67:71: int hl_access_sram_dram_region(struct hl_device *hdev, u64 addr, u64 *val,
• drivers/accel/habanalabs/common/device.c:228:60-228:65: int hl_access_cfg_region(struct hl_device *hdev, u64 addr, u64 *val,
• drivers/accel/habanalabs/common/device.c:274:14-274:19: u64 addr, u64 *val, enum debugfs_access_type acc_type)
• drivers/accel/habanalabs/common/device.c:2517:54-2517:58: inline void hl_wreg(struct hl_device *hdev, u32 reg, u32 val)
• drivers/accel/habanalabs/common/hw_queue.c:20:41-20:45: inline u32 hl_hw_queue_add_ptr(u32 ptr, u16 val)
• drivers/accel/habanalabs/common/hwmon.c:243:27-243:33: u32 attr, int channel, long *val)
• drivers/accel/habanalabs/common/hwmon.c:397:27-397:32: u32 attr, int channel, long val)
• drivers/accel/habanalabs/common/mmu/mmu.c:963:9-963:13: u64 val, u32 hop_table_size)
• drivers/accel/habanalabs/common/mmu/mmu_v1.c:107:71-107:75: static inline void write_pte(struct hl_ctx *ctx, u64 shadow_pte_addr, u64 val)
• drivers/accel/habanalabs/common/mmu/mmu_v1.c:128:6-128:10: u64 val)
• drivers/accel/habanalabs/gaudi/gaudi.c:4558:60-4558:64: static int gaudi_scrub_device_dram(struct hl_device *hdev, u64 val)
• drivers/accel/habanalabs/gaudi/gaudi.c:5563:56-5563:60: static void gaudi_update_eq_ci(struct hl_device *hdev, u32 val)
• drivers/accel/habanalabs/gaudi/gaudi.c:5569:16-5569:20: u32 size, u64 val)
• drivers/accel/habanalabs/gaudi/gaudi.c:5648:20-5648:24: u32 num_regs, u32 val)
• drivers/accel/habanalabs/gaudi/gaudi.c:6039:63-6039:67: static void gaudi_write_pte(struct hl_device *hdev, u64 addr, u64 val)
• drivers/accel/habanalabs/gaudi2/gaudi2.c:6845:82-6845:86: static void gaudi2_memset_device_lbw(struct hl_device *hdev, u32 addr, u32 size, u32 val)
• drivers/accel/habanalabs/gaudi2/gaudi2.c:7407:57-7407:61: static void gaudi2_update_eq_ci(struct hl_device *hdev, u32 val)
• drivers/accel/habanalabs/gaudi2/gaudi2.c:9933:41-9933:45: u32 hw_queue_id, u32 size, u64 addr, u32 val)
• drivers/accel/habanalabs/gaudi2/gaudi2.c:9958:84-9958:88: static int gaudi2_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size, u64 val)
• drivers/accel/habanalabs/gaudi2/gaudi2.c:10079:61-10079:65: static int gaudi2_scrub_device_dram(struct hl_device *hdev, u64 val)
• drivers/accel/habanalabs/goya/goya.c:4177:48-4177:52: void goya_update_eq_ci(struct hl_device *hdev, u32 val)
• drivers/accel/habanalabs/goya/goya.c:4224:62-4224:66: static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
• drivers/accel/habanalabs/goya/goya.c:4766:5-4766:9: u64 val, bool is_dram)
• drivers/accel/habanalabs/goya/goya.c:5423:59-5423:63: static int goya_scrub_device_dram(struct hl_device *hdev, u64 val)
• drivers/accel/ivpu/ivpu_hw_reg_io.h:89:73-89:77: ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val,
• drivers/accel/ivpu/ivpu_hw_reg_io.h:97:73-97:77: ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val,
• drivers/accel/ivpu/ivpu_hw_reg_io.h:106:33-106:37: u32 stride, u32 index, u32 val, const char *name,
• drivers/accel/ivpu/ivpu_mmu.c:379:66-379:70: static int ivpu_mmu_reg_write(struct ivpu_device *vdev, u32 reg, u32 val)
• drivers/accel/qaic/mhi_controller.c:417:81-417:85: static void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 val)
• drivers/accel/qaic/qaic_control.c:245:25-245:32: static __le32 incr_le32(__le32 val)
• drivers/accessibility/speakup/main.c:273:19-273:27: static void bleep(u_short val)
• drivers/acpi/ac.c:103:7-103:35: union power_supply_propval *val)
• drivers/acpi/acpi_extlog.c:134:52-134:66: static int extlog_print(struct notifier_block *nb, unsigned long val,
• drivers/acpi/acpi_lpss.c:733:30-733:34: static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
• drivers/acpi/acpi_lpss.c:739:64-739:69: static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
• drivers/acpi/acpi_lpss.c:813:51-813:55: static void acpi_lpss_set_ltr(struct device *dev, s32 val)
• drivers/acpi/acpi_tad.c:141:46-141:51: static char *acpi_tad_rt_next_field(char *s, int *val)
• drivers/acpi/acpi_video.c:1655:5-1655:19: unsigned long val, void *ign)
• drivers/acpi/apei/apei-base.c:57:63-57:68: int __apei_exec_read_register(struct acpi_whea_header *entry, u64 *val)
• drivers/acpi/apei/apei-base.c:99:64-99:68: int __apei_exec_write_register(struct acpi_whea_header *entry, u64 val)
• drivers/acpi/apei/apei-base.c:645:15-645:20: int apei_read(u64 *val, struct acpi_generic_address *reg)
• drivers/acpi/apei/apei-base.c:679:16-679:20: int apei_write(u64 val, struct acpi_generic_address *reg)
• drivers/acpi/apei/einj.c:618:39-618:44: static int error_type_get(void *data, u64 *val)
• drivers/acpi/apei/einj.c:625:39-625:43: static int error_type_set(void *data, u64 val)
• drivers/acpi/apei/einj.c:660:41-660:45: static int error_inject_set(void *data, u64 val)
• drivers/acpi/battery.c:202:10-202:38: union power_supply_propval *val)
• drivers/acpi/button.c:668:37-668:49: static int param_set_lid_init_state(const char *val,
• drivers/acpi/cppc_acpi.c:954:58-954:63: int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
• drivers/acpi/cppc_acpi.c:969:59-969:63: int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
• drivers/acpi/cppc_acpi.c:980:69-980:74: static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
• drivers/acpi/cppc_acpi.c:1040:70-1040:74: static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
• drivers/acpi/device_pm.c:516:56-516:60: static void acpi_pm_notify_handler(acpi_handle handle, u32 val, void *not_used)
• drivers/acpi/ec.c:886:22-886:26: int ec_read(u8 addr, u8 *val)
• drivers/acpi/ec.c:904:23-904:26: int ec_write(u8 addr, u8 val)
• drivers/acpi/ec.c:2136:37-2136:49: static int param_set_event_clearing(const char *val,
• drivers/acpi/nfit/mce.c:13:55-13:69: static int nfit_handle_mce(struct notifier_block *nb, unsigned long val,
• drivers/acpi/property.c:971:40-971:46: enum dev_prop_type proptype, void *val)
• drivers/acpi/property.c:1050:9-1050:16: char **val, size_t nval)
• drivers/acpi/property.c:1066:11-1066:17: void *val, size_t nval)
• drivers/acpi/property.c:1164:11-1164:17: void *val, size_t nval)
• drivers/acpi/property.c:1358:2-1358:15: unsigned int val)
• drivers/acpi/property.c:1451:33-1451:39: unsigned int elem_size, void *val,
• drivers/acpi/property.c:1478:34-1478:47: const char *propname, const char **val,
• drivers/acpi/sbs.c:133:11-133:39: union power_supply_propval *val)
• drivers/acpi/sbs.c:161:7-161:35: union power_supply_propval *val)
• drivers/acpi/scan.c:1948:70-1948:75: void acpi_scan_hotplug_enabled(struct acpi_hotplug_profile *hotplug, bool val)
• drivers/acpi/sysfs.c:156:40-156:52: static int param_set_trace_method_name(const char *val,
• drivers/acpi/sysfs.c:218:34-218:46: static int param_set_trace_state(const char *val,
• drivers/acpi/sysfs.c:824:44-824:50: static int __init acpi_gpe_set_masked_gpes(char *val)
• drivers/android/binder.c:124:42-124:54: static int binder_set_stop_on_user_error(const char *val,
• drivers/android/binder_alloc_selftest.c:193:41-193:45: static bool is_dup(int *seq, int index, int val)
• drivers/ata/ahci_brcm.c:109:39-109:43: static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
• drivers/ata/ahci_imx.c:163:30-163:34: static int imx_phy_reg_write(u16 val, void __iomem *mmio)
• drivers/ata/ahci_imx.c:205:29-205:34: static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
• drivers/ata/ahci_xgene.c:113:27-113:40: void __iomem *reg, unsigned int val,
• drivers/ata/ata_piix.c:787:29-787:34: unsigned int reg, u32 *val)
• drivers/ata/ata_piix.c:800:23-800:27: unsigned int reg, u32 val)
• drivers/ata/libahci.c:656:70-656:75: static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
• drivers/ata/libahci.c:668:71-668:75: static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
• drivers/ata/libahci.c:1215:60-1215:77: static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
• drivers/ata/libata-core.c:6625:73-6625:77: u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, u32 val,
• drivers/ata/libata-pmp.c:75:68-75:72: static unsigned int sata_pmp_write(struct ata_link *link, int reg, u32 val)
• drivers/ata/libata-pmp.c:172:56-172:60: int sata_pmp_scr_write(struct ata_link *link, int reg, u32 val)
• drivers/ata/libata-sata.c:65:51-65:56: int sata_scr_read(struct ata_link *link, int reg, u32 *val)
• drivers/ata/libata-sata.c:93:52-93:56: int sata_scr_write(struct ata_link *link, int reg, u32 val)
• drivers/ata/libata-sata.c:120:58-120:62: int sata_scr_write_flush(struct ata_link *link, int reg, u32 val)
• drivers/ata/pata_cs5536.c:86:55-86:60: static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
• drivers/ata/pata_cs5536.c:98:56-98:60: static int cs5536_write(struct pci_dev *pdev, int reg, int val)
• drivers/ata/pata_legacy.c:793:58-793:61: static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
• drivers/ata/pata_opti.c:81:49-81:52: static void opti_write_reg(struct ata_port *ap, u8 val, int reg)
• drivers/ata/pata_parport/aten.c:28:72-28:76: static void aten_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/bpck.c:69:72-69:76: static void bpck_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/bpck6.c:141:72-141:76: static void bpck6_write_regr(struct pi_adapter *pi, int cont, int reg, int val)
• drivers/ata/pata_parport/comm.c:64:72-64:76: static void comm_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/dstr.c:69:72-69:76: static void dstr_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/epat.c:37:72-37:76: static void epat_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/epia.c:72:72-72:76: static void epia_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/fit2.c:36:72-36:76: static void fit2_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/fit3.c:33:72-33:76: static void fit3_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/friq.c:60:72-60:76: static void friq_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/frpw.c:47:72-47:76: static void frpw_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/kbic.c:65:72-65:76: static void kbic_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/ktti.c:28:72-28:76: static void ktti_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/on20.c:60:72-60:76: static void on20_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/pata_parport/on26.c:72:72-72:76: static void on26_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
• drivers/ata/sata_dwc_460ex.c:363:71-363:76: static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
• drivers/ata/sata_dwc_460ex.c:378:72-378:76: static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
• drivers/ata/sata_fsl.c:583:34-583:38: unsigned int sc_reg_in, u32 val)
• drivers/ata/sata_fsl.c:607:33-607:38: unsigned int sc_reg_in, u32 *val)
• drivers/ata/sata_highbank.c:268:56-268:60: static void cphy_override_tx_attenuation(u8 sata_port, u32 val)
• drivers/ata/sata_highbank.c:287:49-287:53: static void cphy_override_rx_mode(u8 sata_port, u32 val)
• drivers/ata/sata_inic162x.c:291:66-291:71: static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
• drivers/ata/sata_inic162x.c:306:67-306:71: static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
• drivers/ata/sata_mv.c:1341:71-1341:76: static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
• drivers/ata/sata_mv.c:1352:72-1352:76: static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
• drivers/ata/sata_mv.c:3052:72-3052:77: static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
• drivers/ata/sata_mv.c:3066:73-3066:77: static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
• drivers/ata/sata_nv.c:1501:68-1501:73: static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
• drivers/ata/sata_nv.c:1510:69-1510:73: static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
• drivers/ata/sata_promise.c:462:30-462:35: unsigned int sc_reg, u32 *val)
• drivers/ata/sata_promise.c:471:31-471:35: unsigned int sc_reg, u32 val)
• drivers/ata/sata_qstor.c:214:68-214:73: static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
• drivers/ata/sata_qstor.c:228:69-228:73: static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
• drivers/ata/sata_rcar.c:167:10-167:14: u32 val, int group)
• drivers/ata/sata_rcar.c:482:10-482:15: u32 *val)
• drivers/ata/sata_rcar.c:492:11-492:15: u32 val)
• drivers/ata/sata_sil.c:397:69-397:74: static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
• drivers/ata/sata_sil.c:408:70-408:74: static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
• drivers/ata/sata_sil24.c:500:67-500:72: static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
• drivers/ata/sata_sil24.c:511:68-511:72: static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
• drivers/ata/sata_sis.c:129:29-129:34: unsigned int sc_reg, u32 *val)
• drivers/ata/sata_sis.c:142:30-142:34: unsigned int sc_reg, u32 val)
• drivers/ata/sata_sis.c:151:69-151:74: static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
• drivers/ata/sata_sis.c:166:70-166:74: static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
• drivers/ata/sata_svw.c:107:29-107:34: unsigned int sc_reg, u32 *val)
• drivers/ata/sata_svw.c:117:30-117:34: unsigned int sc_reg, u32 val)
• drivers/ata/sata_uli.c:103:72-103:76: static void uli_scr_cfg_write(struct ata_link *link, unsigned int scr, u32 val)
• drivers/ata/sata_uli.c:111:69-111:74: static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
• drivers/ata/sata_uli.c:120:70-120:74: static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
• drivers/ata/sata_via.c:185:70-185:75: static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
• drivers/ata/sata_via.c:193:71-193:75: static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
• drivers/ata/sata_via.c:201:69-201:74: static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
• drivers/ata/sata_via.c:250:70-250:74: static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val)
• drivers/ata/sata_vsc.c:85:30-85:35: unsigned int sc_reg, u32 *val)
• drivers/ata/sata_vsc.c:95:31-95:35: unsigned int sc_reg, u32 val)
• drivers/atm/fore200e.c:239:62-239:66: fore200e_poll(struct fore200e* fore200e, volatile u32* addr, u32 val, int msecs)
• drivers/atm/fore200e.c:263:73-263:77: fore200e_io_poll(struct fore200e* fore200e, volatile u32 __iomem *addr, u32 val, int msecs)
• drivers/atm/fore200e.c:441:32-441:36: static void fore200e_pca_write(u32 val, volatile u32 __iomem *addr)
• drivers/atm/he.c:182:43-182:52: he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr,
• drivers/atm/he.c:2670:37-2670:51: he_phy_put(struct atm_dev *atm_dev, unsigned char val, unsigned long addr)
• drivers/atm/iphase.c:826:69-826:73: static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val)
• drivers/atm/lanai.c:484:61-484:65: static inline void reg_write(const struct lanai_dev *lanai, u32 val,
• drivers/atm/lanai.c:546:2-546:6: u32 val, int offset)
• drivers/atm/lanai.c:658:2-658:6: u32 val, enum lanai_vcc_offset offset)
• drivers/atm/lanai.c:1913:53-1913:57: static int check_board_id_and_rev(const char *name, u32 val, int *revp)
• drivers/auxdisplay/hd44780.c:64:53-64:56: static void hd44780_write_gpio8(struct hd44780 *hd, u8 val, unsigned int rs)
• drivers/auxdisplay/hd44780.c:80:53-80:56: static void hd44780_write_gpio4(struct hd44780 *hd, u8 val, unsigned int rs)
• drivers/auxdisplay/panel.c:577:45-577:50: static void lcd_get_bits(unsigned int port, int *val)
• drivers/base/memory.c:169:19-169:33: int memory_notify(unsigned long val, void *v)
• drivers/base/power/domain.c:819:10-819:24: unsigned long val, void *ptr)
• drivers/base/power/qos.c:774:49-774:53: int dev_pm_qos_expose_flags(struct device *dev, s32 val)
• drivers/base/power/qos.c:904:66-904:70: int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val)
• drivers/base/property.c:94:7-94:11: u8 *val, size_t nval)
• drivers/base/property.c:122:8-122:13: u16 *val, size_t nval)
• drivers/base/property.c:150:8-150:13: u32 *val, size_t nval)
• drivers/base/property.c:178:8-178:13: u64 *val, size_t nval)
• drivers/base/property.c:206:11-206:24: const char **val, size_t nval)
• drivers/base/property.c:228:5-228:18: const char **val)
• drivers/base/property.c:258:32-258:38: unsigned int elem_size, void *val,
• drivers/base/property.c:297:29-297:33: const char *propname, u8 *val, size_t nval)
• drivers/base/property.c:326:30-326:35: const char *propname, u16 *val, size_t nval)
• drivers/base/property.c:355:30-355:35: const char *propname, u32 *val, size_t nval)
• drivers/base/property.c:384:30-384:35: const char *propname, u64 *val, size_t nval)
• drivers/base/property.c:413:33-413:46: const char *propname, const char **val,
• drivers/base/property.c:447:27-447:40: const char *propname, const char **val)
• drivers/base/regmap/regcache-maple.c:39:5-39:18: unsigned int val)
• drivers/base/regmap/regcache-rbtree.c:56:25-56:38: unsigned int idx, unsigned int val)
• drivers/base/regmap/regcache.c:283:9-283:22: unsigned int val)
• drivers/base/regmap/regcache.c:585:9-585:22: unsigned int val)
• drivers/base/regmap/regcache.c:685:61-685:74: int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-ac97.c:45:2-45:16: unsigned int *val)
• drivers/base/regmap/regmap-ac97.c:55:2-55:15: unsigned int val)
• drivers/base/regmap/regmap-i2c.c:16:11-16:25: unsigned int *val)
• drivers/base/regmap/regmap-i2c.c:35:12-35:25: unsigned int val)
• drivers/base/regmap/regmap-i2c.c:52:11-52:25: unsigned int *val)
• drivers/base/regmap/regmap-i2c.c:71:12-71:25: unsigned int val)
• drivers/base/regmap/regmap-i2c.c:88:8-88:22: unsigned int *val)
• drivers/base/regmap/regmap-i2c.c:107:9-107:22: unsigned int val)
• drivers/base/regmap/regmap-i2c.c:140:8-140:20: const void *val, size_t val_size)
• drivers/base/regmap/regmap-i2c.c:174:7-174:13: void *val, size_t val_size)
• drivers/base/regmap/regmap-i2c.c:223:27-223:33: size_t reg_size, void *val,
• drivers/base/regmap/regmap-i2c.c:264:27-264:33: size_t reg_size, void *val,
• drivers/base/regmap/regmap-i3c.c:26:7-26:13: void *val, size_t val_size)
• drivers/base/regmap/regmap-mmio.c:67:5-67:18: unsigned int val)
• drivers/base/regmap/regmap-mmio.c:74:5-74:18: unsigned int val)
• drivers/base/regmap/regmap-mmio.c:80:24-80:37: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-mmio.c:87:7-87:20: unsigned int val)
• drivers/base/regmap/regmap-mmio.c:94:7-94:20: unsigned int val)
• drivers/base/regmap/regmap-mmio.c:100:27-100:40: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-mmio.c:107:7-107:20: unsigned int val)
• drivers/base/regmap/regmap-mmio.c:113:27-113:40: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-mmio.c:120:7-120:20: unsigned int val)
• drivers/base/regmap/regmap-mmio.c:127:7-127:20: unsigned int val)
• drivers/base/regmap/regmap-mmio.c:133:27-133:40: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-mmio.c:140:7-140:20: unsigned int val)
• drivers/base/regmap/regmap-mmio.c:146:27-146:40: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-mmio.c:151:63-151:76: static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-mmio.c:171:8-171:20: const void *val, size_t val_count)
• drivers/base/regmap/regmap-mmio.c:311:62-311:76: static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
• drivers/base/regmap/regmap-mmio.c:331:7-331:13: void *val, size_t val_count)
• drivers/base/regmap/regmap-ram.c:19:62-19:75: static int regmap_ram_write(void *context, unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-ram.c:29:61-29:75: static int regmap_ram_read(void *context, unsigned int reg, unsigned int *val)
• drivers/base/regmap/regmap-raw-ram.c:31:12-31:24: const void *val, size_t val_len)
• drivers/base/regmap/regmap-raw-ram.c:60:11-60:17: void *val, size_t val_len)
• drivers/base/regmap/regmap-sccb.c:40:62-40:76: static int regmap_sccb_read(void *context, unsigned int reg, unsigned int *val)
• drivers/base/regmap/regmap-sccb.c:75:63-75:76: static int regmap_sccb_write(void *context, unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-sdw-mbq.c:12:66-12:79: static int regmap_sdw_mbq_write(void *context, unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-sdw-mbq.c:25:65-25:79: static int regmap_sdw_mbq_read(void *context, unsigned int reg, unsigned int *val)
• drivers/base/regmap/regmap-slimbus.c:18:11-18:17: void *val, size_t val_size)
• drivers/base/regmap/regmap-spi-avmm.c:501:5-501:10: u32 *val, unsigned int expected_count)
• drivers/base/regmap/regmap-spi.c:38:8-38:20: const void *val, size_t val_len)
• drivers/base/regmap/regmap-spi.c:55:7-55:19: const void *val, size_t val_len,
• drivers/base/regmap/regmap-spi.c:93:7-93:13: void *val, size_t val_size)
• drivers/base/regmap/regmap-spmi.c:18:6-18:12: void *val, size_t val_size)
• drivers/base/regmap/regmap-spmi.c:33:7-33:19: const void *val, size_t val_size)
• drivers/base/regmap/regmap-spmi.c:107:5-107:11: void *val, size_t val_size)
• drivers/base/regmap/regmap-spmi.c:151:6-151:18: const void *val, size_t val_size)
• drivers/base/regmap/regmap-w1.c:21:63-21:77: static int w1_reg_a8_v8_read(void *context, unsigned int reg, unsigned int *val)
• drivers/base/regmap/regmap-w1.c:43:64-43:77: static int w1_reg_a8_v8_write(void *context, unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap-w1.c:70:5-70:19: unsigned int *val)
• drivers/base/regmap/regmap-w1.c:94:5-94:18: unsigned int val)
• drivers/base/regmap/regmap-w1.c:122:5-122:19: unsigned int *val)
• drivers/base/regmap/regmap-w1.c:147:5-147:18: unsigned int val)
• drivers/base/regmap/regmap.c:213:28-213:41: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap.c:225:28-225:41: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap.c:233:28-233:41: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap.c:240:27-240:40: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap.c:247:27-247:40: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap.c:257:27-257:40: unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap.c:266:40-266:53: static void regmap_format_8(void *buf, unsigned int val, unsigned int shift)
• drivers/base/regmap/regmap.c:273:44-273:57: static void regmap_format_16_be(void *buf, unsigned int val, unsigned int shift)
• drivers/base/regmap/regmap.c:278:44-278:57: static void regmap_format_16_le(void *buf, unsigned int val, unsigned int shift)
• drivers/base/regmap/regmap.c:283:48-283:61: static void regmap_format_16_native(void *buf, unsigned int val,
• drivers/base/regmap/regmap.c:291:44-291:57: static void regmap_format_24_be(void *buf, unsigned int val, unsigned int shift)
• drivers/base/regmap/regmap.c:296:44-296:57: static void regmap_format_32_be(void *buf, unsigned int val, unsigned int shift)
• drivers/base/regmap/regmap.c:301:44-301:57: static void regmap_format_32_le(void *buf, unsigned int val, unsigned int shift)
• drivers/base/regmap/regmap.c:306:48-306:61: static void regmap_format_32_native(void *buf, unsigned int val,
• drivers/base/regmap/regmap.c:1598:7-1598:19: const void *val, size_t val_len, bool noinc)
• drivers/base/regmap/regmap.c:1829:12-1829:25: unsigned int val)
• drivers/base/regmap/regmap.c:1857:6-1857:19: unsigned int val)
• drivers/base/regmap/regmap.c:1875:6-1875:19: unsigned int val)
• drivers/base/regmap/regmap.c:1897:5-1897:18: unsigned int val)
• drivers/base/regmap/regmap.c:1936:56-1936:69: int regmap_write(struct regmap *map, unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap.c:1963:62-1963:75: int regmap_write_async(struct regmap *map, unsigned int reg, unsigned int val)
• drivers/base/regmap/regmap.c:1985:9-1985:21: const void *val, size_t val_len, bool noinc)
• drivers/base/regmap/regmap.c:2039:8-2039:20: const void *val, size_t val_len)
• drivers/base/regmap/regmap.c:2059:7-2059:13: void *val, unsigned int val_len, bool write)
• drivers/base/regmap/regmap.c:2158:9-2158:21: const void *val, size_t val_len)
• drivers/base/regmap/regmap.c:2224:26-2224:39: unsigned int mask, unsigned int val,
• drivers/base/regmap/regmap.c:2273:27-2273:40: unsigned int mask, unsigned int val,
• drivers/base/regmap/regmap.c:2302:61-2302:73: int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val,
• drivers/base/regmap/regmap.c:2687:7-2687:19: const void *val, size_t val_len)
• drivers/base/regmap/regmap.c:2710:67-2710:73: static int _regmap_raw_read(struct regmap *map, unsigned int reg, void *val,
• drivers/base/regmap/regmap.c:2743:5-2743:19: unsigned int *val)
• drivers/base/regmap/regmap.c:2761:8-2761:22: unsigned int *val)
• drivers/base/regmap/regmap.c:2779:4-2779:18: unsigned int *val)
• drivers/base/regmap/regmap.c:2820:55-2820:69: int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val)
• drivers/base/regmap/regmap.c:2848:59-2848:65: int regmap_raw_read(struct regmap *map, unsigned int reg, void *val,
• drivers/base/regmap/regmap.c:2948:9-2948:15: void *val, size_t val_len)
• drivers/base/regmap/regmap.c:3014:51-3014:65: int regmap_field_read(struct regmap_field *field, unsigned int *val)
• drivers/base/regmap/regmap.c:3041:10-3041:24: unsigned int *val)
• drivers/base/regmap/regmap.c:3074:60-3074:66: int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
• drivers/base/regmap/regmap.c:3136:30-3136:43: unsigned int mask, unsigned int val,
• drivers/base/regmap/regmap.c:3191:27-3191:40: unsigned int mask, unsigned int val,
• drivers/base/regmap/regmap.c:3416:4-3416:18: unsigned int *val)
• drivers/base/regmap/trace.h:16:1-16:1: DECLARE_EVENT_CLASS(regmap_reg,
• drivers/base/regmap/trace.h:38:1-38:1: DEFINE_EVENT(regmap_reg, regmap_reg_write,
• drivers/base/regmap/trace.h:46:1-46:1: DEFINE_EVENT(regmap_reg, regmap_reg_read,
• drivers/base/regmap/trace.h:54:1-54:1: DEFINE_EVENT(regmap_reg, regmap_reg_read_cache,
• drivers/base/regmap/trace.h:62:1-62:1: DECLARE_EVENT_CLASS(regmap_bulk,
• drivers/base/regmap/trace.h:87:1-87:1: DEFINE_EVENT(regmap_bulk, regmap_bulk_write,
• drivers/base/regmap/trace.h:95:1-95:1: DEFINE_EVENT(regmap_bulk, regmap_bulk_read,
• drivers/base/swnode.c:162:31-162:37: unsigned int elem_size, void *val,
• drivers/base/swnode.c:392:30-392:36: unsigned int elem_size, void *val,
• drivers/base/swnode.c:403:9-403:22: const char **val, size_t nval)
• drivers/bcma/driver_pcie2.c:29:11-29:15: u32 val)
• drivers/block/drbd/drbd_bitmap.c:1387:19-1387:23: unsigned long e, int val)
• drivers/block/drbd/drbd_bitmap.c:1436:25-1436:29: const unsigned long e, int val)
• drivers/block/drbd/drbd_int.h:2236:64-2236:68: static inline int drbd_set_ed_uuid(struct drbd_device *device, u64 val)
• drivers/block/drbd/drbd_main.c:1027:86-1027:103: int drbd_send_state_req(struct drbd_peer_device *peer_device, union drbd_state mask, union drbd_state val)
• drivers/block/drbd/drbd_main.c:1041:84-1041:101: int conn_send_state_req(struct drbd_connection *connection, union drbd_state mask, union drbd_state val)
• drivers/block/drbd/drbd_main.c:3328:59-3328:63: void __drbd_uuid_set(struct drbd_device *device, int idx, u64 val) __must_hold(local)
• drivers/block/drbd/drbd_main.c:3343:58-3343:62: void _drbd_uuid_set(struct drbd_device *device, int idx, u64 val) __must_hold(local)
• drivers/block/drbd/drbd_main.c:3351:57-3351:61: void drbd_uuid_set(struct drbd_device *device, int idx, u64 val) __must_hold(local)
• drivers/block/drbd/drbd_main.c:3392:51-3392:55: void drbd_uuid_set_bm(struct drbd_device *device, u64 val) __must_hold(local)
• drivers/block/drbd/drbd_nl.c:2998:26-2998:43: union drbd_state mask, union drbd_state val)
• drivers/block/drbd/drbd_state.c:481:60-481:77: apply_mask_val(union drbd_state os, union drbd_state mask, union drbd_state val)
• drivers/block/drbd/drbd_state.c:490:28-490:45: union drbd_state mask, union drbd_state val)
• drivers/block/drbd/drbd_state.c:511:25-511:42: union drbd_state mask, union drbd_state val)
• drivers/block/drbd/drbd_state.c:518:7-518:24: union drbd_state val)
• drivers/block/drbd/drbd_state.c:564:9-564:26: union drbd_state val, enum chg_state_flags f)
• drivers/block/drbd/drbd_state.c:650:7-650:24: union drbd_state val, enum chg_state_flags f)
• drivers/block/drbd/drbd_state.c:701:7-701:24: union drbd_state val, enum chg_state_flags f)
• drivers/block/drbd/drbd_state.c:2156:85-2156:102: conn_is_valid_transition(struct drbd_connection *connection, union drbd_state mask, union drbd_state val,
• drivers/block/drbd/drbd_state.c:2199:75-2199:92: conn_set_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val,
• drivers/block/drbd/drbd_state.c:2271:74-2271:91: _conn_rq_cond(struct drbd_connection *connection, union drbd_state mask, union drbd_state val)
• drivers/block/drbd/drbd_state.c:2289:80-2289:97: _conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val,
• drivers/block/drbd/drbd_state.c:2383:79-2383:96: conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val,
• drivers/block/drbd/drbd_state.h:159:10-159:27: union drbd_state val)
• drivers/block/drbd/drbd_vli.h:248:60-248:64: static inline int bitstream_put_bits(struct bitstream *bs, u64 val, const unsigned int bits)
• drivers/block/loop.c:1790:35-1790:47: static int max_loop_param_set_int(const char *val,
• drivers/block/null_blk/main.c:120:50-120:55: static int null_param_store_val(const char *str, int *val, int min, int max)
• drivers/block/null_blk/main.c:256:51-256:64: static inline ssize_t nullb_device_uint_attr_show(unsigned int val, char *page)
• drivers/block/null_blk/main.c:261:52-261:66: static inline ssize_t nullb_device_ulong_attr_show(unsigned long val,
• drivers/block/null_blk/main.c:267:51-267:56: static inline ssize_t nullb_device_bool_attr_show(bool val, char *page)
• drivers/block/null_blk/main.c:272:45-272:59: static ssize_t nullb_device_uint_attr_store(unsigned int *val,
• drivers/block/null_blk/main.c:286:46-286:61: static ssize_t nullb_device_ulong_attr_store(unsigned long *val,
• drivers/block/null_blk/main.c:300:45-300:51: static ssize_t nullb_device_bool_attr_store(bool *val, const char *page,
• drivers/block/rbd.c:1664:73-1664:76: static void __rbd_object_map_set(struct rbd_device *rbd_dev, u64 objno, u8 val)
• drivers/block/rnbd/rnbd-srv.c:32:32-32:44: static int dev_search_path_set(const char *val, const struct kernel_param *kp)
• drivers/bluetooth/btintel.c:699:7-699:13: void *val, size_t val_size)
• drivers/bluetooth/btintel.c:764:8-764:20: const void *val, size_t val_size)
• drivers/bluetooth/btmtksdio.c:895:66-895:71: static int btmtksdio_mtk_reg_read(struct hci_dev *hdev, u32 reg, u32 *val)
• drivers/bluetooth/btmtksdio.c:923:67-923:71: static int btmtksdio_mtk_reg_write(struct hci_dev *hdev, u32 reg, u32 val, u32 mask)
• drivers/bluetooth/btusb.c:2889:70-2889:74: static int btusb_mtk_uhw_reg_write(struct btusb_data *data, u32 reg, u32 val)
• drivers/bluetooth/btusb.c:2917:69-2917:74: static int btusb_mtk_uhw_reg_read(struct btusb_data *data, u32 reg, u32 *val)
• drivers/bluetooth/btusb.c:2946:65-2946:70: static int btusb_mtk_reg_read(struct btusb_data *data, u32 reg, u32 *val)
• drivers/bluetooth/hci_bcm4377.c:604:7-604:11: u16 val)
• drivers/bluetooth/hci_bcm4377.c:1947:18-1947:30: char tag, const char *val, size_t len)
• drivers/bluetooth/hci_bcm4377.c:1959:7-1959:19: const char *val, size_t len)
• drivers/bluetooth/hci_vhci.c:202:40-202:44: static int msft_opcode_set(void *data, u64 val)
• drivers/bluetooth/hci_vhci.c:217:40-217:45: static int msft_opcode_get(void *data, u64 *val)
• drivers/bus/hisi_lpc.c:241:10-241:14: u32 val, size_t dwidth)
• drivers/bus/mhi/ep/mmio.c:18:68-18:72: void mhi_ep_mmio_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 val)
• drivers/bus/mhi/ep/mmio.c:23:85-23:89: void mhi_ep_mmio_masked_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 mask, u32 val)
• drivers/bus/mhi/host/main.c:43:19-43:23: u32 mask, u32 val, u32 delayus)
• drivers/bus/mhi/host/main.c:63:18-63:22: u32 offset, u32 val)
• drivers/bus/mhi/host/main.c:70:10-70:14: u32 val)
• drivers/bus/mhi/host/pci_generic.c:693:30-693:34: void __iomem *addr, u32 val)
• drivers/bus/moxtet.c:421:45-421:48: int moxtet_device_write(struct device *dev, u8 val)
• drivers/cdrom/cdrom.c:3433:49-3433:53: static int cdrom_print_info(const char *header, int val, char *info,
• drivers/char/hw_random/ba431-rng.c:53:6-53:10: u32 val)
• drivers/char/hw_random/bcm2835-rng.c:54:62-54:66: static inline void rng_writel(struct bcm2835_rng_priv *priv, u32 val,
• drivers/char/hw_random/cctrng.c:77:72-77:76: static inline void cc_iowrite(struct cctrng_drvdata *drvdata, u32 reg, u32 val)
• drivers/char/hw_random/omap-rng.c:167:11-167:15: u32 val)
• drivers/char/ipmi/ipmb_dev_int.c:250:32-250:36: enum i2c_slave_event event, u8 *val)
• drivers/char/ipmi/ipmi_ipmb.c:182:38-182:42: enum i2c_slave_event event, u8 *val)
• drivers/char/ipmi/ipmi_msghandler.c:74:35-74:47: static int panic_op_write_handler(const char *val,
• drivers/char/ipmi/ipmi_msghandler.c:1588:50-1588:55: int ipmi_set_gets_events(struct ipmi_user *user, bool val)
• drivers/char/ipmi/ipmi_poweroff.c:50:28-50:40: static int set_param_ifnum(const char *val, const struct kernel_param *kp)
• drivers/char/ipmi/ipmi_si_hotmod.c:58:51-58:65: static int parse_str(const struct hotmod_vals *v, unsigned int *val, char *name,
• drivers/char/ipmi/ipmi_si_hotmod.c:84:29-84:43: const char *name, unsigned int *val)
• drivers/char/ipmi/ipmi_si_hotmod.c:185:27-185:39: static int hotmod_handler(const char *val, const struct kernel_param *kp)
• drivers/char/ipmi/ipmi_watchdog.c:177:30-177:42: static int set_param_timeout(const char *val, const struct kernel_param *kp)
• drivers/char/ipmi/ipmi_watchdog.c:209:26-209:38: static int set_param_str(const char *val, const struct kernel_param *kp)
• drivers/char/ipmi/ipmi_watchdog.c:249:33-249:45: static int set_param_wdog_ifnum(const char *val, const struct kernel_param *kp)
• drivers/char/ipmi/ipmi_watchdog.c:1105:10-1105:23: ipmi_nmi(unsigned int val, struct pt_regs *regs)
• drivers/char/ipmi/kcs_bmc.c:49:69-49:72: void kcs_bmc_update_status(struct kcs_bmc_device *kcs_bmc, u8 mask, u8 val)
• drivers/char/ipmi/kcs_bmc_aspeed.c:199:82-199:85: static void aspeed_kcs_updateb(struct kcs_bmc_device *kcs_bmc, u32 reg, u8 mask, u8 val)
• drivers/char/ipmi/ssif_bmc.c:458:66-458:70: static void handle_read_processed(struct ssif_bmc_ctx *ssif_bmc, u8 *val)
• drivers/char/ipmi/ssif_bmc.c:473:66-473:70: static void handle_write_received(struct ssif_bmc_ctx *ssif_bmc, u8 *val)
• drivers/char/ipmi/ssif_bmc.c:577:62-577:66: static void process_smbus_cmd(struct ssif_bmc_ctx *ssif_bmc, u8 *val)
• drivers/char/ipmi/ssif_bmc.c:599:68-599:72: static void on_read_requested_event(struct ssif_bmc_ctx *ssif_bmc, u8 *val)
• drivers/char/ipmi/ssif_bmc.c:643:68-643:72: static void on_read_processed_event(struct ssif_bmc_ctx *ssif_bmc, u8 *val)
• drivers/char/ipmi/ssif_bmc.c:666:69-666:73: static void on_write_requested_event(struct ssif_bmc_ctx *ssif_bmc, u8 *val)
• drivers/char/ipmi/ssif_bmc.c:685:68-685:72: static void on_write_received_event(struct ssif_bmc_ctx *ssif_bmc, u8 *val)
• drivers/char/ipmi/ssif_bmc.c:717:58-717:62: static void on_stop_event(struct ssif_bmc_ctx *ssif_bmc, u8 *val)
• drivers/char/ipmi/ssif_bmc.c:758:79-758:83: static int ssif_bmc_cb(struct i2c_client *client, enum i2c_slave_event event, u8 *val)
• drivers/char/tpm/tpm_nsc.c:70:58-70:61: static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
• drivers/clk/actions/owl-factor.c:28:4-28:17: unsigned int val, unsigned int *mul, unsigned int *div)
• drivers/clk/actions/owl-pll.c:32:3-32:16: unsigned int val)
• drivers/clk/baikal-t1/ccu-div.c:50:41-50:45: static inline u32 ccu_div_get(u32 mask, u32 val)
• drivers/clk/baikal-t1/ccu-div.c:55:42-55:46: static inline u32 ccu_div_prep(u32 mask, u32 val)
• drivers/clk/baikal-t1/ccu-div.c:397:46-397:51: static int ccu_div_dbgfs_bit_get(void *priv, u64 *val)
• drivers/clk/baikal-t1/ccu-div.c:411:53-411:58: static int ccu_div_dbgfs_var_clkdiv_get(void *priv, u64 *val)
• drivers/clk/baikal-t1/ccu-div.c:424:55-424:60: static int ccu_div_dbgfs_fixed_clkdiv_get(void *priv, u64 *val)
• drivers/clk/baikal-t1/ccu-pll.c:411:46-411:51: static int ccu_pll_dbgfs_bit_get(void *priv, u64 *val)
• drivers/clk/baikal-t1/ccu-pll.c:425:46-425:51: static int ccu_pll_dbgfs_fld_get(void *priv, u64 *val)
• drivers/clk/bcm/clk-bcm2835.c:335:73-335:77: static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
• drivers/clk/bcm/clk-iproc-pll.c:164:26-164:30: const u32 offset, u32 val)
• drivers/clk/bcm/clk-kona.c:40:71-40:75: static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val)
• drivers/clk/bcm/clk-raspberrypi.c:151:20-151:25: u32 tag, u32 *val)
• drivers/clk/clk-aspeed.c:129:65-129:69: static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val)
• drivers/clk/clk-aspeed.c:149:65-149:69: static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
• drivers/clk/clk-axi-clkgen.c:232:20-232:33: unsigned int reg, unsigned int val)
• drivers/clk/clk-axi-clkgen.c:238:20-238:34: unsigned int reg, unsigned int *val)
• drivers/clk/clk-axi-clkgen.c:259:20-259:34: unsigned int reg, unsigned int *val)
• drivers/clk/clk-axi-clkgen.c:283:20-283:33: unsigned int reg, unsigned int val, unsigned int mask)
• drivers/clk/clk-cdce706.c:113:8-113:18: unsigned *val)
• drivers/clk/clk-cdce706.c:123:9-123:18: unsigned val)
• drivers/clk/clk-cdce706.c:133:25-133:34: unsigned mask, unsigned val)
• drivers/clk/clk-cdce925.c:551:39-551:45: const void *reg, size_t reg_size, void *val, size_t val_size)
• drivers/clk/clk-divider.c:37:64-37:68: static inline void clk_div_writel(struct clk_divider *divider, u32 val)
• drivers/clk/clk-divider.c:81:8-81:21: unsigned int val)
• drivers/clk/clk-divider.c:92:9-92:22: unsigned int val, unsigned long flags, u8 width)
• drivers/clk/clk-divider.c:131:7-131:20: unsigned int val,
• drivers/clk/clk-divider.c:363:31-363:44: unsigned long flags, unsigned int val)
• drivers/clk/clk-divider.c:409:28-409:41: unsigned long flags, unsigned int val)
• drivers/clk/clk-fractional-divider.c:61:69-61:73: static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
• drivers/clk/clk-fractional-divider.c:207:43-207:48: static int clk_fd_numerator_get(void *hw, u64 *val)
• drivers/clk/clk-fractional-divider.c:219:45-219:50: static int clk_fd_denominator_get(void *hw, u64 *val)
• drivers/clk/clk-gate.c:35:59-35:63: static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
• drivers/clk/clk-hsdk-pll.c:121:70-121:74: static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val)
• drivers/clk/clk-multiplier.c:23:65-23:69: static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val)
• drivers/clk/clk-mux.c:35:56-35:60: static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
• drivers/clk/clk-mux.c:44:5-44:18: unsigned int val)
• drivers/clk/clk-qoriq.c:102:41-102:45: static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
• drivers/clk/clk-renesas-pcie.c:99:23-99:36: unsigned int reg, unsigned int val)
• drivers/clk/clk-renesas-pcie.c:116:29-116:43: unsigned int reg, unsigned int *val)
• drivers/clk/clk-si521xx.c:96:9-96:22: unsigned int val)
• drivers/clk/clk-si521xx.c:113:8-113:22: unsigned int *val)
• drivers/clk/clk-si5351.c:105:16-105:19: u8 reg, u8 val)
• drivers/clk/clk-si5351.c:117:24-117:27: u8 reg, u8 mask, u8 val)
• drivers/clk/clk-versaclock3.c:472:5-472:18: unsigned int val, unsigned long flag)
• drivers/clk/clk.c:3361:37-3361:42: static int clk_rate_get(void *data, u64 *val)
• drivers/clk/imgtec/clk-boston.c:26:22-26:26: static u32 ext_field(u32 val, u32 mask)
• drivers/clk/imx/clk-gate-93.c:158:63-158:67: unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val,
• drivers/clk/imx/clk.c:151:23-151:28: void imx_cscmr1_fixup(u32 *val)
• drivers/clk/ingenic/cgu.c:63:50-63:55: const struct ingenic_cgu_gate_info *info, bool val)
• drivers/clk/microchip/clk-mpfs.c:364:43-364:47: void mpfs_reset_write(struct device *dev, u32 val)
• drivers/clk/pistachio/clk-pll.c:83:62-83:66: static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)
• drivers/clk/qcom/clk-alpha-pll.c:345:6-345:19: unsigned int val)
• drivers/clk/qcom/clk-branch.h:72:89-72:93: static inline void qcom_branch_set_wakeup(struct regmap *regmap, struct clk_branch clk, u32 val)
• drivers/clk/qcom/clk-branch.h:78:88-78:92: static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branch clk, u32 val)
• drivers/clk/qcom/clk-rcg.c:156:45-156:49: static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
• drivers/clk/qcom/clk-rcg.c:182:51-182:55: static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
• drivers/clk/qcom/gdsc.c:119:54-119:59: static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
• drivers/clk/renesas/clk-mstp.c:70:67-70:71: static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
• drivers/clk/renesas/r9a06g032-clocks.c:675:44-675:48: int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val)
• drivers/clk/sprd/pll.c:54:16-54:20: u32 msk, u32 val)
• drivers/clk/x86/clk-pmc-atom.c:92:63-92:67: static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val)
• drivers/clocksource/dw_apb_timer.c:54:60-54:64: static inline void apbt_writel(struct dw_apb_timer *timer, u32 val,
• drivers/clocksource/dw_apb_timer.c:65:68-65:72: static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val,
• drivers/clocksource/timer-davinci.c:80:28-80:41: unsigned int reg, unsigned int val)
• drivers/clocksource/timer-fsl-ftm.c:40:31-40:35: static inline void ftm_writel(u32 val, void __iomem *addr)
• drivers/clocksource/timer-mediatek-cpux.c:43:29-43:33: static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to)
• drivers/clocksource/timer-ti-dm.c:190:66-190:70: static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val)
• drivers/comedi/drivers/addi_apci_1500.c:69:4-69:17: unsigned int val, unsigned int reg)
• drivers/comedi/drivers/addi_apci_3120.c:158:6-158:19: unsigned int val, unsigned int reg)
• drivers/comedi/drivers/addi_apci_3120.c:314:26-314:39: unsigned int timer, unsigned int val)
• drivers/comedi/drivers/adv_pci1710.c:302:7-302:23: unsigned short *val)
• drivers/comedi/drivers/adv_pci1760.c:96:27-96:42: unsigned char cmd, unsigned short val)
• drivers/comedi/drivers/adv_pci1760.c:121:29-121:44: unsigned char cmd, unsigned short val)
• drivers/comedi/drivers/amplc_dio200_common.c:103:27-103:41: unsigned int offset, unsigned char val)
• drivers/comedi/drivers/amplc_dio200_common.c:130:28-130:41: unsigned int offset, unsigned int val)
• drivers/comedi/drivers/amplc_dio200_common.c:768:58-768:72: void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val)
• drivers/comedi/drivers/c6xdigio.c:63:11-63:24: unsigned int val, unsigned int status)
• drivers/comedi/drivers/c6xdigio.c:86:30-86:43: unsigned int chan, unsigned int val)
• drivers/comedi/drivers/cb_pcidas.c:520:7-520:20: unsigned int val, unsigned int len,
• drivers/comedi/drivers/cb_pcidas.c:579:62-579:75: static void cb_pcidas_dac08_write(struct comedi_device *dev, unsigned int val)
• drivers/comedi/drivers/cb_pcidas.c:615:28-615:41: unsigned int chan, unsigned int val)
• drivers/comedi/drivers/comedi_8254.c:152:6-152:19: unsigned int val, unsigned int reg)
• drivers/comedi/drivers/comedi_8254.c:229:32-229:45: unsigned int counter, unsigned int val)
• drivers/comedi/drivers/comedi_8254.c:279:8-279:21: unsigned int val, unsigned int mode)
• drivers/comedi/drivers/das6402.c:142:6-142:19: unsigned int val)
• drivers/comedi/drivers/das800.c:210:9-210:22: unsigned int val, unsigned int reg)
• drivers/comedi/drivers/jr3_pci.c:294:5-294:19: unsigned int *val)
• drivers/comedi/drivers/jr3_pci.h:12:44-12:48: static inline void set_u16(u32 __iomem *p, u16 val)
• drivers/comedi/drivers/jr3_pci.h:22:44-22:48: static inline void set_s16(s32 __iomem *p, s16 val)
• drivers/comedi/drivers/ni_6527.c:84:12-84:25: unsigned int val)
• drivers/comedi/drivers/ni_6527.c:102:10-102:23: unsigned int val)
• drivers/comedi/drivers/ni_labpc_common.c:890:26-890:39: unsigned int chan, unsigned int val)
• drivers/comedi/drivers/ni_mio_common.c:4297:35-4297:39: static int pack_mb88341(int addr, int val, int *bitstring)
• drivers/comedi/drivers/ni_mio_common.c:4315:35-4315:39: static int pack_dac8800(int addr, int val, int *bitstring)
• drivers/comedi/drivers/ni_mio_common.c:4321:35-4321:39: static int pack_dac8043(int addr, int val, int *bitstring)
• drivers/comedi/drivers/ni_mio_common.c:4327:34-4327:38: static int pack_ad8522(int addr, int val, int *bitstring)
• drivers/comedi/drivers/ni_mio_common.c:4333:34-4333:38: static int pack_ad8804(int addr, int val, int *bitstring)
• drivers/comedi/drivers/ni_mio_common.c:4339:34-4339:38: static int pack_ad8842(int addr, int val, int *bitstring)
• drivers/comedi/drivers/ni_mio_common.c:4361:66-4361:70: static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
• drivers/comedi/drivers/ni_usb6501.c:169:11-169:24: unsigned int val, u8 *bitmap)
• drivers/comedi/drivers/ni_usb6501.c:251:7-251:12: u32 *val)
• drivers/comedi/drivers/pcl711.c:356:27-356:40: unsigned int chan, unsigned int val)
• drivers/comedi/drivers/pcl818.c:424:27-424:42: unsigned int chan, unsigned short val)
• drivers/comedi/drivers/pcmmio.c:184:57-184:70: static void pcmmio_dio_write(struct comedi_device *dev, unsigned int val,
• drivers/comedi/drivers/pcmuio.c:152:53-152:66: static void pcmuio_write(struct comedi_device *dev, unsigned int val,
• drivers/comedi/drivers/quatech_daqp_cs.c:363:55-363:68: static void daqp_set_pacer(struct comedi_device *dev, unsigned int val)
• drivers/comedi/drivers/s526.c:176:27-176:40: unsigned int chan, unsigned int val)
• drivers/comedi/drivers/s626.c:240:58-240:62: static int s626_i2c_handshake(struct comedi_device *dev, u32 val)
• drivers/comedi/drivers/s626.c:356:53-356:57: static int s626_send_dac(struct comedi_device *dev, u32 val)
• drivers/counter/104-quad-8.c:208:31-208:40: const size_t channel, const u8 val,
• drivers/counter/104-quad-8.c:236:37-236:42: struct counter_count *count, u64 *val)
• drivers/counter/104-quad-8.c:284:38-284:42: struct counter_count *count, u64 val)
• drivers/counter/counter-sysfs.c:1006:69-1006:73: static int counter_num_signals_read(struct counter_device *counter, u8 *val)
• drivers/counter/counter-sysfs.c:1012:68-1012:72: static int counter_num_counts_read(struct counter_device *counter, u8 *val)
• drivers/counter/counter-sysfs.c:1019:8-1019:13: u64 *val)
• drivers/counter/counter-sysfs.c:1026:9-1026:13: u64 val)
• drivers/counter/ftm-quaddec.c:162:7-162:12: u64 *val)
• drivers/counter/ftm-quaddec.c:176:8-176:18: const u64 val)
• drivers/counter/i8254.c:58:8-58:19: u64 *const val)
• drivers/counter/intel-qep.c:109:34-109:39: struct counter_count *count, u64 *val)
• drivers/counter/intel-qep.c:223:36-223:39: struct counter_count *count, u8 val)
• drivers/counter/intel-qep.c:341:36-341:39: struct counter_count *count, u8 val)
• drivers/counter/interrupt-cnt.c:88:39-88:44: struct counter_count *count, u64 *val)
• drivers/counter/interrupt-cnt.c:98:40-98:50: struct counter_count *count, const u64 val)
• drivers/counter/microchip-tcb-capture.c:239:39-239:44: struct counter_count *count, u64 *val)
• drivers/counter/rz-mtu3-cnt.c:158:39-158:44: struct counter_count *count, u64 *val)
• drivers/counter/rz-mtu3-cnt.c:180:40-180:50: struct counter_count *count, const u64 val)
• drivers/counter/stm32-lptimer-cnt.c:141:34-141:39: struct counter_count *count, u64 *val)
• drivers/counter/stm32-timer-cnt.c:47:37-47:42: struct counter_count *count, u64 *val)
• drivers/counter/stm32-timer-cnt.c:59:38-59:48: struct counter_count *count, const u64 val)
• drivers/counter/ti-ecap-capture.c:161:86-161:90: static void ecap_cnt_count_set_val(struct counter_device *counter, unsigned int reg, u32 val)
• drivers/counter/ti-ecap-capture.c:171:40-171:45: struct counter_count *count, u64 *val)
• drivers/counter/ti-ecap-capture.c:179:34-179:38: struct counter_count *count, u64 val)
• drivers/counter/ti-ecap-capture.c:289:34-289:39: struct counter_count *count, u64 *val)
• drivers/counter/ti-ecap-capture.c:299:35-299:39: struct counter_count *count, u64 val)
• drivers/counter/ti-ecap-capture.c:312:35-312:40: struct counter_count *count, u64 *val)
• drivers/counter/ti-eqep.c:96:39-96:44: struct counter_count *count, u64 *val)
• drivers/counter/ti-eqep.c:108:40-108:44: struct counter_count *count, u64 val)
• drivers/cpufreq/acpi-cpufreq.c:136:53-136:57: static int set_boost(struct cpufreq_policy *policy, int val)
• drivers/cpufreq/acpi-cpufreq.c:237:61-237:65: static unsigned extract_freq(struct cpufreq_policy *policy, u32 val)
• drivers/cpufreq/acpi-cpufreq.c:260:70-260:74: static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val)
• drivers/cpufreq/acpi-cpufreq.c:277:68-277:72: static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val)
• drivers/cpufreq/acpi-cpufreq.c:290:62-290:66: static void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val)
• drivers/cpufreq/acpi-cpufreq.c:335:37-335:41: const struct cpumask *mask, u32 val)
• drivers/cpufreq/cpufreq.c:315:28-315:42: static void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci)
• drivers/crypto/caam/regs.h:94:1-94:1: caam_to_cpu(16)
• drivers/crypto/caam/regs.h:95:1-95:1: caam_to_cpu(32)
• drivers/crypto/caam/regs.h:96:1-96:1: caam_to_cpu(64)
• drivers/crypto/caam/regs.h:97:1-97:1: cpu_to_caam(16)
• drivers/crypto/caam/regs.h:98:1-98:1: cpu_to_caam(32)
• drivers/crypto/caam/regs.h:99:1-99:1: cpu_to_caam(64)
• drivers/crypto/caam/regs.h:265:63-265:74: static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
• drivers/crypto/cavium/cpt/cpt_common.h:144:8-144:12: u64 val)
• drivers/crypto/cavium/cpt/cptvf_main.c:362:54-362:59: static void cptvf_write_vq_ctl(struct cpt_vf *cptvf, bool val)
• drivers/crypto/cavium/cpt/cptvf_main.c:371:52-371:56: void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, u32 val)
• drivers/crypto/cavium/cpt/cptvf_main.c:382:57-382:60: static void cptvf_write_vq_inprog(struct cpt_vf *cptvf, u8 val)
• drivers/crypto/cavium/cpt/cptvf_main.c:391:63-391:67: static void cptvf_write_vq_done_numwait(struct cpt_vf *cptvf, u32 val)
• drivers/crypto/cavium/cpt/cptvf_main.c:630:56-630:60: static void cptvf_write_vq_saddr(struct cpt_vf *cptvf, u64 val)
• drivers/crypto/cavium/zip/zip_main.c:63:20-63:24: void zip_reg_write(u64 val, u64 __iomem *addr)
• drivers/crypto/ccree/cc_driver.h:212:68-212:72: static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
• drivers/crypto/ccree/cc_hw_queue_defs.h:302:60-302:64: static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size)
• drivers/crypto/ccree/cc_hw_queue_defs.h:400:58-400:62: static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val)
• drivers/crypto/exynos-rng.c:92:59-92:63: static void exynos_rng_writel(struct exynos_rng_dev *rng, u32 val, u32 offset)
• drivers/crypto/hisilicon/debugfs.c:606:48-606:52: static int current_q_write(struct hisi_qm *qm, u32 val)
• drivers/crypto/hisilicon/debugfs.c:665:49-665:53: static int current_qm_write(struct hisi_qm *qm, u32 val)
• drivers/crypto/hisilicon/debugfs.c:1047:48-1047:52: static int qm_debugfs_atomic64_set(void *data, u64 val)
• drivers/crypto/hisilicon/debugfs.c:1057:48-1057:53: static int qm_debugfs_atomic64_get(void *data, u64 *val)
• drivers/crypto/hisilicon/hpre/hpre_main.c:436:25-436:37: static int pf_q_num_set(const char *val, const struct kernel_param *kp)
• drivers/crypto/hisilicon/hpre/hpre_main.c:822:68-822:72: static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val)
• drivers/crypto/hisilicon/hpre/hpre_main.c:847:70-847:74: static void hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val)
• drivers/crypto/hisilicon/hpre/hpre_main.c:951:50-951:55: static int hpre_debugfs_atomic64_get(void *data, u64 *val)
• drivers/crypto/hisilicon/hpre/hpre_main.c:960:50-960:54: static int hpre_debugfs_atomic64_set(void *data, u64 val)
• drivers/crypto/hisilicon/qm.c:3705:11-3705:26: unsigned long *val,
• drivers/crypto/hisilicon/sec2/sec_main.c:314:29-314:41: static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
• drivers/crypto/hisilicon/sec2/sec_main.c:328:30-328:42: static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp)
• drivers/crypto/hisilicon/sec2/sec_main.c:698:55-698:59: static int sec_clear_enable_write(struct hisi_qm *qm, u32 val)
• drivers/crypto/hisilicon/sec2/sec_main.c:803:49-803:54: static int sec_debugfs_atomic64_get(void *data, u64 *val)
• drivers/crypto/hisilicon/sec2/sec_main.c:810:49-810:53: static int sec_debugfs_atomic64_set(void *data, u64 val)
• drivers/crypto/hisilicon/zip/zip_crypto.c:117:27-117:39: static int sgl_sge_nr_set(const char *val, const struct kernel_param *kp)
• drivers/crypto/hisilicon/zip/zip_main.c:367:25-367:37: static int pf_q_num_set(const char *val, const struct kernel_param *kp)
• drivers/crypto/hisilicon/zip/zip_main.c:630:51-630:55: static int clear_enable_write(struct hisi_qm *qm, u32 val)
• drivers/crypto/hisilicon/zip/zip_main.c:733:49-733:53: static int zip_debugfs_atomic64_set(void *data, u64 val)
• drivers/crypto/hisilicon/zip/zip_main.c:743:49-743:54: static int zip_debugfs_atomic64_get(void *data, u64 *val)
• drivers/crypto/intel/qat/qat_common/adf_cfg.c:220:11-220:17: char *val)
• drivers/crypto/intel/qat/qat_common/adf_cfg.c:251:22-251:34: const char *key, const void *val,
• drivers/crypto/intel/qat/qat_common/qat_hal.c:1328:32-1328:45: unsigned short reg_num, unsigned int val)
• drivers/crypto/intel/qat/qat_common/qat_hal.c:1429:29-1429:42: unsigned short nn, unsigned int val)
• drivers/crypto/intel/qat/qat_common/qat_uclo.c:125:30-125:44: unsigned int addr, unsigned int *val,
• drivers/crypto/intel/qat/qat_common/qat_uclo.c:142:11-142:25: unsigned int *val,
• drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c:86:24-86:28: static int is_eng_type(int val, int eng_type)
• drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c:653:43-653:47: struct otx_cpt_engs_rsvd *engs, int val)
• drivers/crypto/marvell/octeontx/otx_cptvf_main.c:345:57-345:62: static void cptvf_write_vq_ctl(struct otx_cptvf *cptvf, bool val)
• drivers/crypto/marvell/octeontx/otx_cptvf_main.c:354:59-354:63: void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val)
• drivers/crypto/marvell/octeontx/otx_cptvf_main.c:363:60-363:63: static void cptvf_write_vq_inprog(struct otx_cptvf *cptvf, u8 val)
• drivers/crypto/marvell/octeontx/otx_cptvf_main.c:372:66-372:70: static void cptvf_write_vq_done_numwait(struct otx_cptvf *cptvf, u32 val)
• drivers/crypto/marvell/octeontx/otx_cptvf_main.c:614:59-614:63: static void cptvf_write_vq_saddr(struct otx_cptvf *cptvf, u64 val)
• drivers/crypto/marvell/octeontx2/otx2_cpt_common.h:126:19-126:23: u64 offs, u64 val)
• drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c:50:9-50:14: u64 *val, int blkaddr)
• drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c:75:19-75:23: u64 reg, u64 val, int blkaddr)
• drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c:101:14-101:19: u64 reg, u64 *val, int blkaddr)
• drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c:114:15-114:19: u64 reg, u64 val, int blkaddr)
• drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c:55:24-55:28: static int is_eng_type(int val, int eng_type)
• drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c:507:44-507:48: struct otx2_cpt_engs_rsvd *engs, int val)
• drivers/crypto/qce/common.c:26:66-26:70: static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)
• drivers/crypto/qce/common.c:32:8-32:19: const u32 *val, unsigned int len)
• drivers/cxl/core/pci.c:243:60-243:64: static int cxl_set_mem_enable(struct cxl_dev_state *cxlds, u16 val)
• drivers/devfreq/devfreq.c:704:7-704:21: unsigned long val, void *ptr)
• drivers/devfreq/devfreq.c:716:7-716:21: unsigned long val, void *ptr)
• drivers/devfreq/tegra30-devfreq.c:223:56-223:60: static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset)
• drivers/devfreq/tegra30-devfreq.c:233:61-233:65: static void device_writel(struct tegra_devfreq_device *dev, u32 val,
• drivers/devfreq/tegra30-devfreq.c:239:33-239:52: static unsigned long do_percent(unsigned long long val, unsigned int pct)
• drivers/dma/apple-admac.c:202:68-202:72: static void admac_modify(struct admac_data *ad, int reg, u32 mask, u32 val)
• drivers/dma/bcm-sba-raid.c:163:47-163:51: static inline u64 __pure sba_cmd_enc(u64 cmd, u32 val, u32 shift, u32 mask)
• drivers/dma/dma-axi-dmac.c:171:2-171:15: unsigned int val)
• drivers/dma/dma-jz4780.c:190:38-190:42: unsigned int chn, unsigned int reg, u32 val)
• drivers/dma/dma-jz4780.c:202:20-202:24: unsigned int reg, u32 val)
• drivers/dma/dma-jz4780.c:272:2-272:16: unsigned long val, u32 *shift)
• drivers/dma/dmatest.c:277:29-277:35: static int dmatest_wait_get(char *val, const struct kernel_param *kp)
• drivers/dma/dmatest.c:481:55-481:68: static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
• drivers/dma/dmatest.c:1162:28-1162:34: static int dmatest_run_get(char *val, const struct kernel_param *kp)
• drivers/dma/dmatest.c:1179:28-1179:40: static int dmatest_run_set(const char *val, const struct kernel_param *kp)
• drivers/dma/dmatest.c:1218:29-1218:41: static int dmatest_chan_set(const char *val, const struct kernel_param *kp)
• drivers/dma/dmatest.c:1290:29-1290:35: static int dmatest_chan_get(char *val, const struct kernel_param *kp)
• drivers/dma/dmatest.c:1304:34-1304:40: static int dmatest_test_list_get(char *val, const struct kernel_param *kp)
• drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:55:55-55:59: axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
• drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:66:56-66:60: axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val)
• drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:77:56-77:60: axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val)
• drivers/dma/dw-edma/dw-edma-v0-debugfs.c:71:48-71:53: static int dw_edma_debugfs_u32_get(void *data, u64 *val)
• drivers/dma/dw-edma/dw-hdma-v0-debugfs.c:48:48-48:53: static int dw_hdma_debugfs_u32_get(void *data, u64 *val)
• drivers/dma/fsl-edma-common.h:272:11-272:14: u8 val, void __iomem *addr)
• drivers/dma/fsl-edma-common.h:282:11-282:15: u16 val, void __iomem *addr)
• drivers/dma/fsl-edma-common.h:292:11-292:15: u32 val, void __iomem *addr)
• drivers/dma/hisi_dma.c:331:12-331:16: u32 val)
• drivers/dma/hisi_dma.c:336:69-336:74: static inline void hisi_dma_update_bit(void __iomem *addr, u32 pos, bool val)
• drivers/dma/idxd/init.c:432:45-432:50: void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count)
• drivers/dma/idxd/sysfs.c:984:45-984:50: static int __get_sysfs_u64(const char *buf, u64 *val)
• drivers/dma/img-mdc-dma.c:153:53-153:57: static inline void mdc_writel(struct mdc_dma *mdma, u32 val, u32 reg)
• drivers/dma/img-mdc-dma.c:163:60-163:64: static inline void mdc_chan_writel(struct mdc_chan *mchan, u32 val, u32 reg)
• drivers/dma/lgm/lgm-dma.c:279:48-279:52: ldma_update_bits(struct ldma_dev *d, u32 mask, u32 val, u32 ofs)
• drivers/dma/lgm/lgm-dma.c:519:53-519:57: static int ldma_chan_cctrl_cfg(struct ldma_chan *c, u32 val)
• drivers/dma/lgm/lgm-dma.c:576:54-576:58: static void ldma_chan_set_class(struct ldma_chan *c, u32 val)
• drivers/dma/mediatek/mtk-cqdma.c:173:64-173:68: static void mtk_dma_write(struct mtk_cqdma_pchan *pc, u32 reg, u32 val)
• drivers/dma/mediatek/mtk-cqdma.c:189:62-189:66: static void mtk_dma_set(struct mtk_cqdma_pchan *pc, u32 reg, u32 val)
• drivers/dma/mediatek/mtk-cqdma.c:194:62-194:66: static void mtk_dma_clr(struct mtk_cqdma_pchan *pc, u32 reg, u32 val)
• drivers/dma/mediatek/mtk-hsdma.c:273:68-273:72: static void mtk_dma_write(struct mtk_hsdma_device *hsdma, u32 reg, u32 val)
• drivers/dma/mediatek/mtk-hsdma.c:289:66-289:70: static void mtk_dma_set(struct mtk_hsdma_device *hsdma, u32 reg, u32 val)
• drivers/dma/mediatek/mtk-hsdma.c:294:66-294:70: static void mtk_dma_clr(struct mtk_hsdma_device *hsdma, u32 reg, u32 val)
• drivers/dma/mediatek/mtk-uart-apdma.c:121:29-121:42: unsigned int reg, unsigned int val)
• drivers/dma/qcom/hidma_mgmt_sys.c:47:1-47:1: IMPLEMENT_GETSET(hw_version_major)
• drivers/dma/qcom/hidma_mgmt_sys.c:48:1-48:1: IMPLEMENT_GETSET(hw_version_minor)
• drivers/dma/qcom/hidma_mgmt_sys.c:49:1-49:1: IMPLEMENT_GETSET(max_wr_xactions)
• drivers/dma/qcom/hidma_mgmt_sys.c:50:1-50:1: IMPLEMENT_GETSET(max_rd_xactions)
• drivers/dma/qcom/hidma_mgmt_sys.c:51:1-51:1: IMPLEMENT_GETSET(max_write_request)
• drivers/dma/qcom/hidma_mgmt_sys.c:52:1-52:1: IMPLEMENT_GETSET(max_read_request)
• drivers/dma/qcom/hidma_mgmt_sys.c:53:1-53:1: IMPLEMENT_GETSET(dma_channels)
• drivers/dma/qcom/hidma_mgmt_sys.c:54:1-54:1: IMPLEMENT_GETSET(chreset_timeout_cycles)
• drivers/dma/qcom/hidma_mgmt_sys.c:56:70-56:74: static int set_priority(struct hidma_mgmt_dev *mdev, unsigned int i, u64 val)
• drivers/dma/qcom/hidma_mgmt_sys.c:72:68-72:72: static int set_weight(struct hidma_mgmt_dev *mdev, unsigned int i, u64 val)
• drivers/dma/sh/rz-dmac.c:175:50-175:63: static void rz_dmac_writel(struct rz_dmac *dmac, unsigned int val,
• drivers/dma/sh/rz-dmac.c:181:54-181:67: static void rz_dmac_ext_writel(struct rz_dmac *dmac, unsigned int val,
• drivers/dma/sh/rz-dmac.c:192:61-192:74: static void rz_dmac_ch_writel(struct rz_dmac_chan *channel, unsigned int val,
• drivers/dma/sh/shdmac.c:244:56-244:60: static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
• drivers/dma/sh/shdmac.c:256:57-256:61: static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
• drivers/dma/sprd-dma.c:242:15-242:19: u32 mask, u32 val)
• drivers/dma/sprd-dma.c:252:15-252:19: u32 mask, u32 val)
• drivers/dma/stm32-dma.c:262:71-262:75: static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
• drivers/dma/stm32-dmamux.c:59:69-59:73: static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)
• drivers/dma/stm32-mdma.c:294:73-294:77: static void stm32_mdma_write(struct stm32_mdma_device *dmadev, u32 reg, u32 val)
• drivers/dma/tegra186-gpc-dma.c:261:18-261:22: u32 reg, u32 val)
• drivers/dma/tegra20-apb-dma.c:230:64-230:68: static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
• drivers/dma/tegra20-apb-dma.c:236:18-236:22: u32 reg, u32 val)
• drivers/dma/tegra210-adma.c:168:65-168:69: static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
• drivers/dma/tegra210-adma.c:178:72-178:76: static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
• drivers/dma/ti/dma-crossbar.c:52:73-52:76: static inline void ti_am335x_xbar_write(void __iomem *iomem, int event, u8 val)
• drivers/dma/ti/dma-crossbar.c:219:70-219:74: static inline void ti_dra7_xbar_write(void __iomem *iomem, int xbar, u16 val)
• drivers/dma/ti/edma.c:305:64-305:68: static inline void edma_write(struct edma_cc *ecc, int offset, int val)
• drivers/dma/ti/edma.c:335:9-335:18: unsigned val)
• drivers/dma/ti/edma.c:353:17-353:26: int j, unsigned val)
• drivers/dma/ti/edma.c:365:11-365:20: unsigned val)
• drivers/dma/ti/edma.c:371:17-371:26: int i, unsigned val)
• drivers/dma/ti/omap-dma.c:310:28-310:37: static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
• drivers/dma/ti/omap-dma.c:351:71-351:80: static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
• drivers/dma/ti/omap-dma.c:369:68-369:77: static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
• drivers/dma/xilinx/xilinx_dpdma.c:472:64-472:68: static inline void dpdma_write(void __iomem *base, u32 offset, u32 val)
• drivers/edac/amd64_edac.c:74:11-74:16: u32 *val, const char *func)
• drivers/edac/amd64_edac.c:87:5-87:9: u32 val, const char *func)
• drivers/edac/amd64_edac.c:127:19-127:24: int offset, u32 *val)
• drivers/edac/edac_mc_sysfs.c:53:31-53:43: static int edac_set_poll_msec(const char *val, const struct kernel_param *kp)
• drivers/edac/ghes_edac.c:270:11-270:25: unsigned long val, void *data)
• drivers/edac/i10nm_base.c:1023:40-1023:44: static int debugfs_u64_set(void *data, u64 val)
• drivers/edac/i7core_edac.c:865:65-865:75: static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
• drivers/edac/i7core_edac.c:1810:62-1810:76: static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
• drivers/edac/igen6_edac.c:735:58-735:72: static int ecclog_mce_handler(struct notifier_block *nb, unsigned long val,
• drivers/edac/igen6_edac.c:892:40-892:44: static int debugfs_u64_set(void *data, u64 val)
• drivers/edac/mce_amd.c:1235:43-1235:57: amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
• drivers/edac/pnd2_edac.c:1370:60-1370:74: static int pnd2_mce_check_error(struct notifier_block *nb, unsigned long val, void *data)
• drivers/edac/pnd2_edac.c:1430:40-1430:44: static int debugfs_u64_set(void *data, u64 val)
• drivers/edac/sb_edac.c:3255:63-3255:77: static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
• drivers/edac/skx_base.c:598:40-598:44: static int debugfs_u64_set(void *data, u64 val)
• drivers/edac/skx_common.c:633:52-633:66: int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
• drivers/edac/xgene_edac.c:66:65-66:70: static void xgene_edac_pcp_rd(struct xgene_edac *edac, u32 reg, u32 *val)
• drivers/extcon/extcon-max14577.c:196:3-196:6: u8 val, bool attached)
• drivers/extcon/extcon-max77693.c:258:3-258:6: u8 val, bool attached)
• drivers/extcon/extcon-max77843.c:199:3-199:6: u8 val, bool attached, bool nobccomp)
• drivers/extcon/extcon-max8997.c:198:3-198:6: u8 val, bool attached)
• drivers/firewire/nosy.c:245:45-245:49: set_phy_reg(struct pcilynx *lynx, int addr, int val)
• drivers/firewire/ohci.c:576:64-576:68: static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
• drivers/firmware/arm_scpi.c:739:46-739:51: static int scpi_sensor_get_value(u16 sensor, u64 *val)
• drivers/firmware/broadcom/bcm47xx_nvram.c:185:44-185:50: int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
• drivers/firmware/broadcom/bcm47xx_sprom.c:89:1-89:1: NVRAM_READ_VAL(u8)
• drivers/firmware/broadcom/bcm47xx_sprom.c:90:1-90:1: NVRAM_READ_VAL(s8)
• drivers/firmware/broadcom/bcm47xx_sprom.c:91:1-91:1: NVRAM_READ_VAL(u16)
• drivers/firmware/broadcom/bcm47xx_sprom.c:92:1-92:1: NVRAM_READ_VAL(u32)
• drivers/firmware/broadcom/bcm47xx_sprom.c:142:11-142:19: u8 val[6], bool fallback)
• drivers/firmware/broadcom/bcm47xx_sprom.c:157:9-157:19: char val[2], bool fallback)
• drivers/firmware/cirrus/cs_dsp.c:3251:60-3251:64: int cs_dsp_chunk_write(struct cs_dsp_chunk *ch, int nbits, u32 val)
• drivers/firmware/google/gsmi.c:711:33-711:37: static u64 __init local_hash_64(u64 val, unsigned bits)
• drivers/firmware/imx/misc.c:52:17-52:21: u8 ctrl, u32 val)
• drivers/firmware/imx/misc.c:82:17-82:22: u8 ctrl, u32 *val)
• drivers/firmware/qcom_scm.c:712:41-712:55: int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
• drivers/firmware/qcom_scm.c:733:42-733:55: int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
• drivers/fpga/altera-cvp.c:97:19-97:23: int where, u8 *val)
• drivers/fpga/altera-cvp.c:104:20-104:25: int where, u32 *val)
• drivers/fpga/altera-cvp.c:111:21-111:25: int where, u32 val)
• drivers/fpga/altera-cvp.c:133:71-133:75: static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val)
• drivers/fpga/altera-cvp.c:138:72-138:76: static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
• drivers/fpga/dfl-fme-main.c:227:33-227:39: u32 attr, int channel, long *val)
• drivers/fpga/dfl-fme-main.c:378:31-378:37: u32 attr, int channel, long *val)
• drivers/fpga/dfl-fme-main.c:412:32-412:37: u32 attr, int channel, long val)
• drivers/fpga/dfl-n3000-nios.c:478:66-478:79: static int n3000_nios_reg_write(void *context, unsigned int reg, unsigned int val)
• drivers/fpga/dfl-n3000-nios.c:497:65-497:79: static int n3000_nios_reg_read(void *context, unsigned int reg, unsigned int *val)
• drivers/fpga/xilinx-pr-decoupler.c:32:21-32:25: u32 offset, u32 val)
• drivers/fpga/zynq-fpga.c:138:8-138:12: u32 val)
• drivers/fsi/fsi-core.c:120:60-120:66: int fsi_device_read(struct fsi_device *dev, uint32_t addr, void *val,
• drivers/fsi/fsi-core.c:130:61-130:73: int fsi_device_write(struct fsi_device *dev, uint32_t addr, const void *val,
• drivers/fsi/fsi-core.c:140:45-140:51: int fsi_device_peek(struct fsi_device *dev, void *val)
• drivers/fsi/fsi-core.c:332:4-332:10: void *val, size_t size)
• drivers/fsi/fsi-core.c:357:4-357:16: const void *val, size_t size)
• drivers/fsi/fsi-core.c:1137:36-1137:42: uint8_t slave_id, uint32_t addr, void *val, size_t size)
• drivers/fsi/fsi-core.c:1154:36-1154:48: uint8_t slave_id, uint32_t addr, const void *val, size_t size)
• drivers/fsi/fsi-master-aspeed.c:98:10-98:14: u32 val, u32 transfer_size)
• drivers/fsi/fsi-master-aspeed.c:134:67-134:70: static int opb_writeb(struct fsi_master_aspeed *aspeed, u32 addr, u8 val)
• drivers/fsi/fsi-master-aspeed.c:139:67-139:74: static int opb_writew(struct fsi_master_aspeed *aspeed, u32 addr, __be16 val)
• drivers/fsi/fsi-master-aspeed.c:144:67-144:74: static int opb_writel(struct fsi_master_aspeed *aspeed, u32 addr, __be32 val)
• drivers/fsi/fsi-master-aspeed.c:256:31-256:37: uint8_t id, uint32_t addr, void *val, size_t size)
• drivers/fsi/fsi-master-aspeed.c:291:31-291:43: uint8_t id, uint32_t addr, const void *val, size_t size)
• drivers/fsi/fsi-master-ast-cf.c:598:38-598:44: uint8_t id, uint32_t addr, void *val,
• drivers/fsi/fsi-master-ast-cf.c:622:32-622:44: uint8_t id, uint32_t addr, const void *val,
• drivers/fsi/fsi-master-gpio.c:562:30-562:36: uint8_t id, uint32_t addr, void *val, size_t size)
• drivers/fsi/fsi-master-gpio.c:581:30-581:42: uint8_t id, uint32_t addr, const void *val, size_t size)
• drivers/fsi/fsi-master-hub.c:46:31-46:37: uint8_t id, uint32_t addr, void *val, size_t size)
• drivers/fsi/fsi-master-hub.c:58:31-58:43: uint8_t id, uint32_t addr, const void *val, size_t size)
• drivers/fsi/fsi-master-i2cr.c:187:86-187:92: static int i2cr_read(struct fsi_master *master, int link, uint8_t id, uint32_t addr, void *val,
• drivers/fsi/fsi-master-i2cr.c:227:9-227:21: const void *val, size_t size)
• drivers/gpio/gpio-74x164.c:56:20-56:24: unsigned offset, int val)
• drivers/gpio/gpio-74x164.c:94:20-94:24: unsigned offset, int val)
• drivers/gpio/gpio-74xx-mmio.c:98:71-98:75: static int mmio_74xx_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
• drivers/gpio/gpio-adp5520.c:44:17-44:21: unsigned off, int val)
• drivers/gpio/gpio-adp5520.c:67:17-67:21: unsigned off, int val)
• drivers/gpio/gpio-aspeed-sgpio.c:187:71-187:75: static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
• drivers/gpio/gpio-aspeed-sgpio.c:214:73-214:77: static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
• drivers/gpio/gpio-aspeed-sgpio.c:231:76-231:80: static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
• drivers/gpio/gpio-aspeed.c:392:10-392:14: int val)
• drivers/gpio/gpio-aspeed.c:412:8-412:12: int val)
• drivers/gpio/gpio-aspeed.c:456:32-456:36: unsigned int offset, int val)
• drivers/gpio/gpio-ath79.c:50:18-50:22: unsigned reg, u32 val)
• drivers/gpio/gpio-creg-snps.c:30:70-30:74: static void creg_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
• drivers/gpio/gpio-creg-snps.c:52:73-52:77: static int creg_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
• drivers/gpio/gpio-cs5535.c:60:56-60:60: static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
• drivers/gpio/gpio-cs5535.c:235:68-235:72: static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
• drivers/gpio/gpio-cs5535.c:256:72-256:76: static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
• drivers/gpio/gpio-dwapb.c:159:11-159:15: u32 val)
• drivers/gpio/gpio-eic-sprd.c:140:17-140:30: u16 reg, unsigned int val)
• drivers/gpio/gpio-f7188x.c:120:52-120:56: static inline void superio_outb(int base, int reg, int val)
• drivers/gpio/gpio-grgpio.c:91:9-91:13: int val)
• drivers/gpio/gpio-hisi.c:54:30-54:34: unsigned int off, u32 val)
• drivers/gpio/gpio-ich.c:101:53-101:57: static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)
• drivers/gpio/gpio-ich.c:176:6-176:10: int val)
• drivers/gpio/gpio-ich.c:255:68-255:72: static void ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)
• drivers/gpio/gpio-it87.c:111:33-111:37: static inline void superio_outb(int val, int reg)
• drivers/gpio/gpio-it87.c:217:25-217:29: unsigned gpio_num, int val)
• drivers/gpio/gpio-it87.c:234:27-234:31: unsigned gpio_num, int val)
• drivers/gpio/gpio-janz-ttl.c:108:59-108:63: static void ttl_write_reg(struct ttl_module *mod, u8 reg, u16 val)
• drivers/gpio/gpio-kempld.c:35:26-35:29: u8 reg, u8 bit, u8 val)
• drivers/gpio/gpio-latch.c:76:30-76:35: unsigned int offset, bool val)
• drivers/gpio/gpio-latch.c:93:71-93:75: static void gpio_latch_set(struct gpio_chip *gc, unsigned int offset, int val)
• drivers/gpio/gpio-latch.c:105:81-105:85: static void gpio_latch_set_can_sleep(struct gpio_chip *gc, unsigned int offset, int val)
• drivers/gpio/gpio-lp3943.c:66:5-66:8: u8 val)
• drivers/gpio/gpio-lpc32xx.c:173:65-173:69: static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
• drivers/gpio/gpio-max7300.c:17:5-17:18: unsigned int val)
• drivers/gpio/gpio-max7301.c:20:5-20:18: unsigned int val)
• drivers/gpio/gpio-max732x.c:154:67-154:75: static int max732x_writeb(struct max732x_chip *chip, int group_a, uint8_t val)
• drivers/gpio/gpio-max732x.c:169:66-169:75: static int max732x_readb(struct max732x_chip *chip, int group_a, uint8_t *val)
• drivers/gpio/gpio-max732x.c:204:7-204:11: int val)
• drivers/gpio/gpio-max732x.c:228:72-228:76: static void max732x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
• drivers/gpio/gpio-max732x.c:270:17-270:21: unsigned off, int val)
• drivers/gpio/gpio-ml-ioh.c:92:63-92:67: static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
• drivers/gpio/gpio-ml-ioh.c:117:10-117:14: int val)
• drivers/gpio/gpio-mmio.c:216:69-216:73: static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
• drivers/gpio/gpio-mmio.c:220:64-220:68: static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
• drivers/gpio/gpio-mmio.c:238:6-238:10: int val)
• drivers/gpio/gpio-mmio.c:248:68-248:72: static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
• drivers/gpio/gpio-mmio.c:335:5-335:9: int val)
• drivers/gpio/gpio-mmio.c:341:5-341:9: int val)
• drivers/gpio/gpio-mmio.c:388:68-388:72: static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
• drivers/gpio/gpio-mmio.c:405:8-405:12: int val)
• drivers/gpio/gpio-mmio.c:413:8-413:12: int val)
• drivers/gpio/gpio-moxtet.c:56:7-56:11: int val)
• drivers/gpio/gpio-moxtet.c:102:27-102:31: unsigned int offset, int val)
• drivers/gpio/gpio-mpc8xxx.c:76:24-76:28: unsigned int gpio, int val)
• drivers/gpio/gpio-mpc8xxx.c:87:24-87:28: unsigned int gpio, int val)
• drivers/gpio/gpio-mt7621.c:66:45-66:49: mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
• drivers/gpio/gpio-pca953x.c:482:67-482:82: static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
• drivers/gpio/gpio-pca953x.c:500:66-500:81: static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
• drivers/gpio/gpio-pca953x.c:532:17-532:21: unsigned off, int val)
• drivers/gpio/gpio-pca953x.c:570:72-570:76: static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
• drivers/gpio/gpio-pch.c:103:67-103:71: static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
• drivers/gpio/gpio-pch.c:128:10-128:14: int val)
• drivers/gpio/gpio-pmic-eic-sprd.c:66:15-66:28: u16 reg, unsigned int val)
• drivers/gpio/gpio-raspberrypi-exp.c:103:73-103:77: static int rpi_exp_gpio_dir_out(struct gpio_chip *gc, unsigned int off, int val)
• drivers/gpio/gpio-raspberrypi-exp.c:178:70-178:74: static void rpi_exp_gpio_set(struct gpio_chip *gc, unsigned int off, int val)
• drivers/gpio/gpio-rc5t583.c:38:73-38:77: static void rc5t583_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
• drivers/gpio/gpio-rda.c:45:17-45:21: u16 reg, int val)
• drivers/gpio/gpio-regmap.c:85:8-85:12: int val)
• drivers/gpio/gpio-regmap.c:99:33-99:37: unsigned int offset, int val)
• drivers/gpio/gpio-rockchip.c:65:35-65:39: static inline void gpio_writel_v2(u32 val, void __iomem *reg)
• drivers/gpio/gpio-sch.c:84:9-84:13: int val)
• drivers/gpio/gpio-sch.c:118:71-118:75: static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
• drivers/gpio/gpio-sch.c:129:7-129:11: int val)
• drivers/gpio/gpio-sch.c:220:81-220:85: static void sch_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t gpio_num, int val)
• drivers/gpio/gpio-sch311x.c:121:67-121:71: static inline void sch311x_sio_outb(int sio_config_port, int reg, int val)
• drivers/gpio/gpio-sprd.c:49:18-49:22: u16 reg, int val)
• drivers/gpio/gpio-stmpe.c:56:69-56:73: static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
• drivers/gpio/gpio-stmpe.c:94:24-94:28: unsigned offset, int val)
• drivers/gpio/gpio-stp-xway.c:116:63-116:67: static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
• drivers/gpio/gpio-stp-xway.c:137:66-137:70: static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
• drivers/gpio/gpio-syscon.c:72:70-72:74: static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
• drivers/gpio/gpio-syscon.c:103:73-103:77: static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
• drivers/gpio/gpio-syscon.c:132:10-132:14: int val)
• drivers/gpio/gpio-syscon.c:160:72-160:76: static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
• drivers/gpio/gpio-tc3589x.c:52:75-52:79: static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
• drivers/gpio/gpio-tc3589x.c:64:28-64:32: unsigned int offset, int val)
• drivers/gpio/gpio-tegra.c:103:10-103:14: u32 val, u32 reg)
• drivers/gpio/gpio-timberdale.c:78:20-78:24: unsigned nr, int val)
• drivers/gpio/gpio-timberdale.c:84:18-84:22: unsigned nr, int val)
• drivers/gpio/gpio-tqmx86.c:49:60-49:63: static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val,
• drivers/gpio/gpio-ts5500.c:225:72-225:76: static int ts5500_gpio_output(struct gpio_chip *chip, unsigned offset, int val)
• drivers/gpio/gpio-ts5500.c:247:70-247:74: static void ts5500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
• drivers/gpio/gpio-uniphier.c:59:38-59:42: unsigned int reg, u32 mask, u32 val)
• drivers/gpio/gpio-uniphier.c:73:38-73:42: unsigned int reg, u32 mask, u32 val)
• drivers/gpio/gpio-uniphier.c:86:12-86:16: int val)
• drivers/gpio/gpio-uniphier.c:127:29-127:33: unsigned int offset, int val)
• drivers/gpio/gpio-uniphier.c:141:31-141:35: unsigned int offset, int val)
• drivers/gpio/gpio-vx855.c:131:6-131:10: int val)
• drivers/gpio/gpio-vx855.c:159:28-159:32: unsigned int nr, int val)
• drivers/gpio/gpio-wcd934x.c:46:10-46:14: int val)
• drivers/gpio/gpio-wcd934x.c:68:68-68:72: static void wcd_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
• drivers/gpio/gpio-winbond.c:431:11-431:15: int val)
• drivers/gpio/gpio-winbond.c:462:9-462:13: int val)
• drivers/gpio/gpio-xgene-sb.c:62:34-62:38: void __iomem *reg, u32 gpio, int val)
• drivers/gpio/gpio-xilinx.c:177:64-177:68: static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
• drivers/gpio/gpio-xilinx.c:263:67-263:71: static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:1193:9-1193:23: unsigned long val,
• drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1704:66-1704:75: static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1732:65-1732:74: static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1746:66-1746:75: static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:473:8-473:17: uint64_t val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1691:50-1691:55: static int amdgpu_debugfs_evict_vram(void *data, u64 *val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1712:49-1712:54: static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1732:49-1732:53: static int amdgpu_debugfs_benchmark(void *data, u64 val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1888:50-1888:54: static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1962:48-1962:52: static int amdgpu_debugfs_sclk_set(void *data, u64 val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:944:40-944:45: static int gpu_recover_get(void *data, u64 *val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c:286:6-286:10: u8 *val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c:320:6-320:9: u8 val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:783:21-783:30: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:834:4-834:13: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:3039:9-3039:23: unsigned long val, void *data)
• drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c:571:50-571:54: static int amdgpu_debugfs_ring_error(void *data, u64 val)
• drivers/gpu/drm/amd/amdgpu/atom.c:450:15-450:24: int *ptr, uint32_t val, uint32_t saved)
• drivers/gpu/drm/amd/amdgpu/cik_sdma.c:869:23-869:32: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3734:35-3734:44: bool wc, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:8707:8-8707:17: uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:8730:6-8730:15: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:281:35-281:44: bool wc, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:5655:8-5655:17: uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:5678:6-5678:15: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:2321:23-2321:32: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:3209:23-3209:32: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:6375:7-6375:16: uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:961:35-961:44: bool wc, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:5646:9-5646:18: uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:5669:6-5669:15: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:214:35-214:44: bool wc, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:2668:9-2668:18: uint32_t val)
• drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:2691:6-2691:15: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c:38:108-38:117: static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c:347:24-347:33: uint32_t reg, uint32_t val,
• drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c:392:20-392:29: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c:589:5-589:14: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c:630:75-630:84: void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c:815:5-815:14: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c:856:84-856:93: static void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:42:67-42:72: static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)
• drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:41:67-41:72: static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val)
• drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c:343:67-343:72: static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
• drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c:808:24-808:33: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c:1079:24-1079:33: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1683:24-1683:33: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1692:7-1692:16: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:1218:24-1218:33: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:1227:7-1227:16: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:1304:24-1304:33: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:1313:7-1313:16: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1140:24-1140:33: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1149:7-1149:16: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c:1209:24-1209:33: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c:1218:7-1218:16: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/si_dma.c:458:21-458:30: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c:1061:23-1061:32: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1365:23-1365:32: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1381:6-1381:15: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1433:24-1433:33: uint32_t reg, uint32_t val,
• drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1456:20-1456:29: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/vce_v4_0.c:1014:8-1014:17: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/vce_v4_0.c:1036:25-1036:34: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c:57:2-57:11: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c:81:2-81:11: uint32_t val)
• drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c:1531:24-1531:33: uint32_t reg, uint32_t val,
• drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c:1566:20-1566:29: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c:1686:24-1686:33: uint32_t reg, uint32_t val,
• drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c:1709:20-1709:29: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1493:5-1493:14: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1527:19-1527:28: uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1663:5-1663:14: uint32_t val, uint32_t mask)
• drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1684:74-1684:83: void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
• drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h:332:68-332:78: static inline int read_sdma_queue_counter(uint64_t __user *q_rptr, uint64_t *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6194:10-6194:19: uint64_t val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6249:10-6249:20: uint64_t *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:2861:48-2861:52: static int force_yuv420_output_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:2873:48-2873:53: static int force_yuv420_output_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:2888:32-2888:37: static int psr_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:2904:43-2904:48: static int psr_read_residency(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:2918:56-2918:61: static int allow_edp_hotplug_detection_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:2931:56-2931:60: static int allow_edp_hotplug_detection_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:2948:52-2948:56: static int dmcub_trace_event_state_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:2966:52-2966:57: static int dmcub_trace_event_state_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3178:44-3178:48: static int crc_win_x_start_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3195:44-3195:49: static int crc_win_x_start_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3215:44-3215:48: static int crc_win_y_start_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3232:44-3232:49: static int crc_win_y_start_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3251:42-3251:46: static int crc_win_x_end_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3268:42-3268:47: static int crc_win_x_end_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3287:42-3287:46: static int crc_win_y_end_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3304:42-3304:47: static int crc_win_y_end_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3322:43-3322:47: static int crc_win_update_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3352:43-3352:48: static int crc_win_update_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3483:44-3483:48: static int trigger_hpd_mst_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3535:44-3535:49: static int trigger_hpd_mst_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3550:46-3550:50: static int force_timing_sync_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3565:46-3565:51: static int force_timing_sync_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3582:40-3582:44: static int disable_hpd_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3596:40-3596:45: static int disable_hpd_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3612:41-3612:45: static int dp_force_sst_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3621:41-3621:46: static int dp_force_sst_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3636:47-3636:51: static int dp_ignore_cable_id_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3645:47-3645:52: static int dp_ignore_cable_id_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3660:43-3660:47: static int visual_confirm_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3673:43-3673:48: static int visual_confirm_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3691:57-3691:61: static int skip_detection_link_training_set(void *data, u64 val)
• drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:3707:57-3707:62: static int skip_detection_link_training_get(void *data, u64 *val)
• drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h:105:41-105:45: static inline double dml_fmod(double f, int val)
• drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c:81:35-81:44: static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
• drivers/gpu/drm/arm/display/komeda/d71/d71_component.c:74:16-74:21: u32 count, u32 *val)
• drivers/gpu/drm/ast/ast_drv.h:286:65-286:69: static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val)
• drivers/gpu/drm/ast/ast_drv.h:296:67-296:70: static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val)
• drivers/gpu/drm/ast/ast_drv.h:316:82-316:85: static inline void ast_set_index_reg(struct ast_device *ast, u32 base, u8 index, u8 val)
• drivers/gpu/drm/ast/ast_drv.h:324:26-324:29: u8 preserve_mask, u8 val)
• drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c:91:67-91:70: static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
• drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c:230:66-230:70: int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u16 addr, u32 val)
• drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c:250:34-250:38: u8 start_bit, u8 bits_no, u32 val)
• drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c:34:8-34:11: u8 val)
• drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c:502:58-502:62: int cdns_mhdp_hdcp_set_lc(struct cdns_mhdp_device *mhdp, u8 *val)
• drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c:517:9-517:47: struct cdns_hdcp_tx_public_key_param *val)
• drivers/gpu/drm/bridge/chipone-icn6211.c:206:8-206:14: void *val, size_t val_size)
• drivers/gpu/drm/bridge/chipone-icn6211.c:236:56-236:60: static void chipone_readb(struct chipone *icn, u8 reg, u8 *val)
• drivers/gpu/drm/bridge/chipone-icn6211.c:245:56-245:59: static int chipone_writeb(struct chipone *icn, u8 reg, u8 val)
• drivers/gpu/drm/bridge/nwl-dsi.c:136:66-136:70: static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
• drivers/gpu/drm/bridge/nxp-ptn3460.c:72:3-72:8: char val)
• drivers/gpu/drm/bridge/parade-ps8622.c:65:67-65:70: static int ps8622_set(struct i2c_client *client, u8 page, u8 reg, u8 val)
• drivers/gpu/drm/bridge/samsung-dsim.c:519:29-519:33: enum reg_idx idx, u32 val)
• drivers/gpu/drm/bridge/sii902x.c:187:66-187:70: static int sii902x_read_unlocked(struct i2c_client *i2c, u8 reg, u8 *val)
• drivers/gpu/drm/bridge/sii902x.c:202:67-202:70: static int sii902x_write_unlocked(struct i2c_client *i2c, u8 reg, u8 val)
• drivers/gpu/drm/bridge/sii902x.c:214:6-214:9: u8 val)
• drivers/gpu/drm/bridge/sil-sii8620.c:256:69-256:72: static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val)
• drivers/gpu/drm/bridge/sil-sii8620.c:425:64-425:67: static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val)
• drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c:135:28-135:32: static void dw_hdmi_writel(u32 val, void __iomem *ptr)
• drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c:71:52-71:55: static void dw_hdmi_write(struct dw_hdmi_cec *cec, u8 val, int offset)
• drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c:23:10-23:13: u8 val, int offset)
• drivers/gpu/drm/bridge/synopsys/dw-hdmi.c:210:54-210:57: static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
• drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c:303:64-303:68: static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
• drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c:1020:50-1020:54: static int dw_mipi_dsi_debugfs_write(void *data, u64 val)
• drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c:1045:49-1045:54: static int dw_mipi_dsi_debugfs_show(void *data, u64 *val)
• drivers/gpu/drm/bridge/tc358762.c:90:60-90:64: static void tc358762_write(struct tc358762 *ctx, u16 addr, u32 val)
• drivers/gpu/drm/bridge/tc358764.c:166:59-166:64: static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val)
• drivers/gpu/drm/bridge/tc358764.c:182:60-182:64: static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val)
• drivers/gpu/drm/bridge/tc358768.c:181:65-181:69: static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
• drivers/gpu/drm/bridge/tc358768.c:197:64-197:69: static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
• drivers/gpu/drm/bridge/tc358768.c:214:6-214:10: u32 val)
• drivers/gpu/drm/bridge/tc358775.c:213:43-213:52: static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
• drivers/gpu/drm/bridge/tc358775.c:221:43-221:52: static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
• drivers/gpu/drm/bridge/tc358775.c:229:39-229:48: static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
• drivers/gpu/drm/bridge/tc358775.c:237:42-237:51: static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
• drivers/gpu/drm/bridge/tc358775.c:245:42-245:51: static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
• drivers/gpu/drm/bridge/tc358775.c:327:56-327:61: static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val)
• drivers/gpu/drm/bridge/tc358775.c:349:57-349:61: static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val)
• drivers/gpu/drm/bridge/ti-sn65dsi86.c:225:25-225:30: unsigned int reg, u16 *val)
• drivers/gpu/drm/bridge/ti-sn65dsi86.c:240:26-240:30: unsigned int reg, u16 val)
• drivers/gpu/drm/bridge/ti-sn65dsi86.c:1701:7-1701:11: int val)
• drivers/gpu/drm/bridge/ti-sn65dsi86.c:1749:33-1749:37: unsigned int offset, int val)
• drivers/gpu/drm/display/drm_hdcp_helper.c:316:1-316:1: DRM_ENUM_NAME_FN(drm_get_content_protection_name, drm_cp_enum_list)
• drivers/gpu/drm/display/drm_hdcp_helper.c:322:1-322:1: DRM_ENUM_NAME_FN(drm_get_hdcp_content_type_name,
• drivers/gpu/drm/display/drm_hdcp_helper.c:408:6-408:10: u64 val)
• drivers/gpu/drm/drm_atomic_uapi.c:409:3-409:12: uint64_t val)
• drivers/gpu/drm/drm_atomic_uapi.c:478:34-478:44: struct drm_property *property, uint64_t *val)
• drivers/gpu/drm/drm_atomic_uapi.c:514:34-514:43: struct drm_property *property, uint64_t val)
• drivers/gpu/drm/drm_atomic_uapi.c:610:34-610:44: struct drm_property *property, uint64_t *val)
• drivers/gpu/drm/drm_atomic_uapi.c:692:34-692:43: struct drm_property *property, uint64_t val)
• drivers/gpu/drm/drm_atomic_uapi.c:818:34-818:44: struct drm_property *property, uint64_t *val)
• drivers/gpu/drm/drm_atomic_uapi.c:899:34-899:44: struct drm_property *property, uint64_t *val)
• drivers/gpu/drm/drm_connector.c:903:1-903:1: DRM_ENUM_NAME_FN(drm_get_dpms_name, drm_dpms_enum_list)
• drivers/gpu/drm/drm_connector.c:981:1-981:1: DRM_ENUM_NAME_FN(drm_get_dvi_i_select_name, drm_dvi_i_select_enum_list)
• drivers/gpu/drm/drm_connector.c:988:1-988:1: DRM_ENUM_NAME_FN(drm_get_dvi_i_subconnector_name,
• drivers/gpu/drm/drm_connector.c:1000:1-1000:1: DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list)
• drivers/gpu/drm/drm_connector.c:1033:1-1033:1: DRM_ENUM_NAME_FN(drm_get_tv_select_name, drm_tv_select_enum_list)
• drivers/gpu/drm/drm_connector.c:1042:1-1042:1: DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
• drivers/gpu/drm/drm_connector.c:1055:1-1055:1: DRM_ENUM_NAME_FN(drm_get_dp_subconnector_name,
• drivers/gpu/drm/drm_flip_work.c:76:54-76:60: void drm_flip_work_queue(struct drm_flip_work *work, void *val)
• drivers/gpu/drm/drm_kms_helper_common.c:42:30-42:42: static int edid_firmware_set(const char *val, const struct kernel_param *kp)
• drivers/gpu/drm/drm_mipi_dbi.c:132:57-132:61: int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
• drivers/gpu/drm/drm_mode_object.c:284:38-284:47: struct drm_property *property, uint64_t val)
• drivers/gpu/drm/drm_mode_object.c:304:7-304:17: uint64_t *val)
• drivers/gpu/drm/drm_mode_object.c:320:9-320:19: uint64_t *val)
• drivers/gpu/drm/drm_mode_object.c:352:38-352:48: struct drm_property *property, uint64_t *val)
• drivers/gpu/drm/drm_mode_object.c:378:8-378:18: uint64_t *val)
• drivers/gpu/drm/drm_self_refresh_helper.c:56:1-56:1: DECLARE_EWMA(psr_time, 4, 4)
• drivers/gpu/drm/exynos/exynos5433_drm_decon.c:97:7-97:11: u32 val)
• drivers/gpu/drm/exynos/exynos_drm_fimc.c:118:50-118:54: static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg)
• drivers/gpu/drm/exynos/exynos_drm_fimd.c:255:6-255:10: u32 val)
• drivers/gpu/drm/exynos/exynos_drm_ipp.c:424:55-424:68: static inline void __limit_set_val(unsigned int *ptr, unsigned int val)
• drivers/gpu/drm/exynos/exynos_drm_ipp.c:454:34-454:47: static inline bool __align_check(unsigned int val, unsigned int align)
• drivers/gpu/drm/exynos/exynos_drm_ipp.c:464:39-464:52: static inline bool __size_limit_check(unsigned int val,
• drivers/gpu/drm/exynos/exynos_drm_scaler.c:424:36-424:40: static inline int scaler_task_done(u32 val)
• drivers/gpu/drm/exynos/exynos_hdmi.c:696:19-696:23: int bytes, u32 val)
• drivers/gpu/drm/exynos/exynos_mixer.c:190:6-190:10: u32 val)
• drivers/gpu/drm/exynos/exynos_mixer.c:196:6-196:10: u32 val, u32 mask)
• drivers/gpu/drm/exynos/exynos_mixer.c:210:6-210:10: u32 val)
• drivers/gpu/drm/exynos/exynos_mixer.c:216:18-216:22: u32 reg_id, u32 val, u32 mask)
• drivers/gpu/drm/gma500/cdv_intel_display.c:130:50-130:55: int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
• drivers/gpu/drm/gma500/cdv_intel_display.c:157:51-157:55: int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
• drivers/gpu/drm/gma500/cdv_intel_dp.c:1806:9-1806:18: uint64_t val)
• drivers/gpu/drm/gma500/opregion.c:232:8-232:22: unsigned long val, void *data)
• drivers/gpu/drm/gma500/psb_drv.h:690:7-690:16: uint32_t val)
• drivers/gpu/drm/gma500/psb_drv.h:697:11-697:20: uint32_t val)
• drivers/gpu/drm/gma500/psb_drv.h:707:11-707:20: uint32_t val, int aux)
• drivers/gpu/drm/gma500/psb_drv.h:718:20-718:29: uint32_t reg, uint32_t val)
• drivers/gpu/drm/gma500/psb_drv.h:727:26-727:35: uint32_t reg, uint32_t val)
• drivers/gpu/drm/gma500/psb_intel_sdvo.c:231:79-231:83: static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val)
• drivers/gpu/drm/gma500/psb_intel_sdvo.c:747:87-747:90: static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val)
• drivers/gpu/drm/gma500/psb_intel_sdvo.c:1592:4-1592:13: uint64_t val)
• drivers/gpu/drm/gud/gud_drv.c:227:68-227:72: int gud_usb_get_u8(struct gud_device *gdrm, u8 request, u16 index, u8 *val)
• drivers/gpu/drm/gud/gud_drv.c:246:57-246:60: int gud_usb_set_u8(struct gud_device *gdrm, u8 request, u8 val)
• drivers/gpu/drm/i2c/ch7006_drv.c:286:12-286:21: uint64_t val)
• drivers/gpu/drm/i2c/ch7006_mode.c:368:60-368:68: void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val)
• drivers/gpu/drm/i2c/sil164_drv.c:106:55-106:63: sil164_write(struct i2c_client *client, uint8_t addr, uint8_t val)
• drivers/gpu/drm/i2c/sil164_drv.c:320:8-320:17: uint64_t val)
• drivers/gpu/drm/i2c/tda9950.c:98:63-98:66: static void tda9950_write(struct i2c_client *client, u8 addr, u8 val)
• drivers/gpu/drm/i2c/tda998x_drv.c:406:48-406:51: cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
• drivers/gpu/drm/i2c/tda998x_drv.c:651:47-651:50: reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
• drivers/gpu/drm/i2c/tda998x_drv.c:670:49-670:53: reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
• drivers/gpu/drm/i2c/tda998x_drv.c:689:45-689:48: reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
• drivers/gpu/drm/i2c/tda998x_drv.c:699:47-699:50: reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
• drivers/gpu/drm/i915/display/dvo_ch7017.c:169:64-169:68: static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val)
• drivers/gpu/drm/i915/display/dvo_ch7017.c:188:65-188:68: static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
• drivers/gpu/drm/i915/display/hsw_ips.c:277:56-277:61: static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
• drivers/gpu/drm/i915/display/hsw_ips.c:287:56-287:60: static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
• drivers/gpu/drm/i915/display/intel_atomic.c:59:7-59:12: u64 *val)
• drivers/gpu/drm/i915/display/intel_atomic.c:92:7-92:11: u64 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:84:73-84:77: u32 intel_backlight_invert_pwm_level(struct intel_connector *connector, u32 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:102:82-102:86: void intel_backlight_set_pwm_level(const struct drm_connector_state *conn_state, u32 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:113:69-113:73: u32 intel_backlight_level_to_pwm(struct intel_connector *connector, u32 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:127:71-127:75: u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:358:85-358:89: static void pch_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:370:86-370:90: static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:375:86-375:90: static void i965_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:384:85-384:89: static void vlv_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:395:85-395:89: static void bxt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
• drivers/gpu/drm/i915/display/intel_backlight.c:410:85-410:89: static void cnp_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
• drivers/gpu/drm/i915/display/intel_bios.c:2131:28-2131:31: static u8 translate_iboost(u8 val)
• drivers/gpu/drm/i915/display/intel_color.c:781:33-781:37: static u32 intel_color_lut_pack(u32 val, int bit_precision)
• drivers/gpu/drm/i915/display/intel_color.c:800:58-800:62: static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
• drivers/gpu/drm/i915/display/intel_color.c:906:35-906:39: static u16 i965_lut_11p6_max_pack(u32 val)
• drivers/gpu/drm/i915/display/intel_color.c:919:58-919:62: static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
• drivers/gpu/drm/i915/display/intel_color.c:1245:22-1245:26: i915_reg_t reg, u32 val)
• drivers/gpu/drm/i915/display/intel_cx0_phy.c:107:30-107:35: int command, int lane, u32 *val)
• drivers/gpu/drm/i915/display/intel_de.h:39:63-39:67: intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
• drivers/gpu/drm/i915/display/intel_de.h:108:66-108:70: intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
• drivers/gpu/drm/i915/display/intel_de.h:121:71-121:75: intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
• drivers/gpu/drm/i915/display/intel_display_power.c:1255:64-1255:68: static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
• drivers/gpu/drm/i915/display/intel_dkl_phy.c:68:82-68:86: intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val)
• drivers/gpu/drm/i915/display/intel_drrs.c:334:51-334:55: static int intel_drrs_debugfs_ctl_set(void *data, u64 val)
• drivers/gpu/drm/i915/display/intel_dsb.c:150:21-150:25: i915_reg_t reg, u32 val)
• drivers/gpu/drm/i915/display/intel_fbc.c:1790:58-1790:63: static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
• drivers/gpu/drm/i915/display/intel_fbc.c:1799:58-1799:62: static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
• drivers/gpu/drm/i915/display/intel_hotplug_irq.c:213:62-213:66: static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
• drivers/gpu/drm/i915/display/intel_hotplug_irq.c:228:60-228:64: static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
• drivers/gpu/drm/i915/display/intel_hotplug_irq.c:242:64-242:68: static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
• drivers/gpu/drm/i915/display/intel_hotplug_irq.c:255:63-255:67: static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
• drivers/gpu/drm/i915/display/intel_hotplug_irq.c:270:61-270:65: static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
• drivers/gpu/drm/i915/display/intel_hotplug_irq.c:280:60-280:64: static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
• drivers/gpu/drm/i915/display/intel_hotplug_irq.c:296:60-296:64: static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
• drivers/gpu/drm/i915/display/intel_hotplug_irq.c:306:60-306:64: static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
• drivers/gpu/drm/i915/display/intel_hotplug_irq.c:320:61-320:65: static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
• drivers/gpu/drm/i915/display/intel_opregion.c:652:11-652:25: unsigned long val, void *data)
• drivers/gpu/drm/i915/display/intel_opregion.c:679:61-679:65: static void set_did(struct intel_opregion *opregion, int i, u32 val)
• drivers/gpu/drm/i915/display/intel_pipe_crc.c:56:6-56:11: u32 *val)
• drivers/gpu/drm/i915/display/intel_pipe_crc.c:128:5-128:10: u32 *val)
• drivers/gpu/drm/i915/display/intel_pipe_crc.c:195:6-195:11: u32 *val)
• drivers/gpu/drm/i915/display/intel_pipe_crc.c:253:5-253:10: u32 *val)
• drivers/gpu/drm/i915/display/intel_pipe_crc.c:333:5-333:10: u32 *val)
• drivers/gpu/drm/i915/display/intel_pipe_crc.c:361:5-361:10: u32 *val)
• drivers/gpu/drm/i915/display/intel_pipe_crc.c:403:47-403:52: enum intel_pipe_crc_source *source, u32 *val)
• drivers/gpu/drm/i915/display/intel_psr.c:325:8-325:12: u32 val, bool psr2_enabled)
• drivers/gpu/drm/i915/display/intel_psr.c:2411:52-2411:56: int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
• drivers/gpu/drm/i915/display/intel_psr.c:3079:36-3079:40: i915_edp_psr_debug_set(void *data, u64 val)
• drivers/gpu/drm/i915/display/intel_psr.c:3106:36-3106:41: i915_edp_psr_debug_get(void *data, u64 *val)
• drivers/gpu/drm/i915/display/intel_sdvo.c:215:67-215:71: static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
• drivers/gpu/drm/i915/display/intel_sdvo.c:821:75-821:78: static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
• drivers/gpu/drm/i915/display/intel_sdvo.c:2348:7-2348:12: u64 *val)
• drivers/gpu/drm/i915/display/intel_sdvo.c:2407:7-2407:11: u64 val)
• drivers/gpu/drm/i915/display/skl_watermark.c:2936:39-2936:43: static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
• drivers/gpu/drm/i915/gem/selftests/huge_pages.c:1058:8-1058:12: u32 val)
• drivers/gpu/drm/i915/gem/selftests/huge_pages.c:1073:63-1073:67: __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)
• drivers/gpu/drm/i915/gem/selftests/huge_pages.c:1108:73-1108:77: static int __cpu_check_vmap(struct drm_i915_gem_object *obj, u32 dword, u32 val)
• drivers/gpu/drm/i915/gem/selftests/huge_pages.c:1138:66-1138:70: static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
• drivers/gpu/drm/i915/gem/selftests/huge_pages.c:1149:19-1149:23: u32 dword, u32 val)
• drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:340:61-340:65: static void fill_scratch(struct tiled_blits *t, u32 *vaddr, u32 val)
• drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c:45:5-45:9: u32 val)
• drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c:113:28-113:32: unsigned long count, u32 val)
• drivers/gpu/drm/i915/gt/intel_context_types.h:24:1-24:1: DECLARE_EWMA(runtime, 3, 8);
• drivers/gpu/drm/i915/gt/intel_engine_types.h:148:1-148:1: DECLARE_EWMA(_engine_latency, 6, 4)
• drivers/gpu/drm/i915/gt/intel_gt_debugfs.c:17:54-17:59: int intel_gt_debugfs_reset_show(struct intel_gt *gt, u64 *val)
• drivers/gpu/drm/i915/gt/intel_gt_debugfs.c:33:56-33:60: void intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val)
• drivers/gpu/drm/i915/gt/intel_gt_debugfs.c:47:54-47:59: static int __intel_gt_debugfs_reset_show(void *data, u64 *val)
• drivers/gpu/drm/i915/gt/intel_gt_debugfs.c:52:55-52:59: static int __intel_gt_debugfs_reset_store(void *data, u64 val)
• drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:550:47-550:52: static int perf_limit_reasons_get(void *data, u64 *val)
• drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:561:49-561:53: static int perf_limit_reasons_clear(void *data, u64 val)
• drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:29:48-29:52: int (func)(struct intel_gt *gt, u32 val), u32 val)
• drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:342:56-342:60: static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
• drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:367:48-367:52: static int __set_max_freq(struct intel_gt *gt, u32 val)
• drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:377:48-377:52: static int __set_min_freq(struct intel_gt *gt, u32 val)
• drivers/gpu/drm/i915/gt/intel_gtt.c:307:46-307:56: fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
• drivers/gpu/drm/i915/gt/intel_rps.c:70:62-70:66: static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:169:47-169:50: static u32 rps_pm_mask(struct intel_rps *rps, u8 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:421:10-421:23: unsigned int val)
• drivers/gpu/drm/i915/gt/intel_rps.c:430:50-430:53: static int __gen5_rps_set(struct intel_rps *rps, u8 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:460:48-460:51: static int gen5_rps_set(struct intel_rps *rps, u8 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:648:46-648:49: static u32 rps_limits(struct intel_rps *rps, u8 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:739:60-739:63: static void gen6_rps_set_thresholds(struct intel_rps *rps, u8 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:795:48-795:51: static int gen6_rps_set(struct intel_rps *rps, u8 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:819:47-819:50: static int vlv_rps_set(struct intel_rps *rps, u8 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:834:43-834:46: static int rps_set(struct intel_rps *rps, u8 val, bool update)
• drivers/gpu/drm/i915/gt/intel_rps.c:962:54-962:58: static int rps_set_boost_freq(struct intel_rps *rps, u32 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:1053:42-1053:45: int intel_rps_set(struct intel_rps *rps, u8 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:1608:48-1608:52: static int byt_gpu_freq(struct intel_rps *rps, int val)
• drivers/gpu/drm/i915/gt/intel_rps.c:1617:51-1617:55: static int byt_freq_opcode(struct intel_rps *rps, int val)
• drivers/gpu/drm/i915/gt/intel_rps.c:1622:48-1622:52: static int chv_gpu_freq(struct intel_rps *rps, int val)
• drivers/gpu/drm/i915/gt/intel_rps.c:1631:51-1631:55: static int chv_freq_opcode(struct intel_rps *rps, int val)
• drivers/gpu/drm/i915/gt/intel_rps.c:1637:43-1637:47: int intel_gpu_freq(struct intel_rps *rps, int val)
• drivers/gpu/drm/i915/gt/intel_rps.c:1654:46-1654:50: int intel_freq_opcode(struct intel_rps *rps, int val)
• drivers/gpu/drm/i915/gt/intel_rps.c:2455:48-2455:52: static int set_max_freq(struct intel_rps *rps, u32 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:2493:56-2493:60: int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:2538:48-2538:52: static int set_min_freq(struct intel_rps *rps, u32 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:2571:56-2571:60: int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val)
• drivers/gpu/drm/i915/gt/intel_rps.c:2586:68-2586:71: static int rps_set_threshold(struct intel_rps *rps, u8 *threshold, u8 val)
• drivers/gpu/drm/i915/gt/intel_workarounds.c:301:56-301:60: wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
• drivers/gpu/drm/i915/gt/intel_workarounds.c:307:64-307:68: wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
• drivers/gpu/drm/i915/gt/intel_workarounds.c:313:57-313:61: wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
• drivers/gpu/drm/i915/gt/intel_workarounds.c:319:65-319:69: wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
• drivers/gpu/drm/i915/gt/intel_workarounds.c:326:17-326:21: u32 mask, u32 val)
• drivers/gpu/drm/i915/gt/intel_workarounds.c:333:14-333:18: u32 mask, u32 val)
• drivers/gpu/drm/i915/gt/selftest_tlb.c:23:56-23:60: static void vma_set_qw(struct i915_vma *vma, u64 addr, u64 val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c:74:55-74:60: static int guc_sched_disable_delay_ms_get(void *data, u64 *val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c:86:55-86:59: static int guc_sched_disable_delay_ms_set(void *data, u64 val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c:102:62-102:67: static int guc_sched_disable_gucid_threshold_get(void *data, u64 *val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c:113:62-113:66: static int guc_sched_disable_gucid_threshold_set(void *data, u64 val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c:82:42-82:47: static int guc_log_level_get(void *data, u64 *val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c:94:42-94:46: static int guc_log_level_set(void *data, u64 val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:407:62-407:66: int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:444:62-444:67: int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:461:69-461:74: int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:501:62-501:66: int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:543:62-543:67: int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:560:70-560:74: int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val)
• drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:780:64-780:68: int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val)
• drivers/gpu/drm/i915/gvt/debugfs.c:127:37-127:42: vgpu_scan_nonprivbb_get(void *data, u64 *val)
• drivers/gpu/drm/i915/gvt/debugfs.c:142:37-142:41: vgpu_scan_nonprivbb_set(void *data, u64 val)
• drivers/gpu/drm/i915/gvt/debugfs.c:154:40-154:45: static int vgpu_status_get(void *data, u64 *val)
• drivers/gpu/drm/i915/gvt/gvt.h:479:22-479:26: u32 offset, u32 val, bool low)
• drivers/gpu/drm/i915/gvt/kvmgt.c:1581:47-1581:57: static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len,
• drivers/gpu/drm/i915/i915_debugfs.c:609:40-609:45: static int i915_wedged_get(void *data, u64 *val)
• drivers/gpu/drm/i915/i915_debugfs.c:632:40-632:44: static int i915_wedged_set(void *data, u64 val)
• drivers/gpu/drm/i915/i915_debugfs.c:649:37-649:41: i915_perf_noa_delay_set(void *data, u64 val)
• drivers/gpu/drm/i915/i915_debugfs.c:665:37-665:42: i915_perf_noa_delay_get(void *data, u64 *val)
• drivers/gpu/drm/i915/i915_debugfs.c:699:34-699:39: i915_drop_caches_get(void *data, u64 *val)
• drivers/gpu/drm/i915/i915_debugfs.c:707:37-707:41: gt_drop_caches(struct intel_gt *gt, u64 val)
• drivers/gpu/drm/i915/i915_debugfs.c:740:34-740:38: i915_drop_caches_set(void *data, u64 val)
• drivers/gpu/drm/i915/i915_fixed.h:20:36-20:55: static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
• drivers/gpu/drm/i915/i915_fixed.h:25:49-25:53: static inline uint_fixed_16_16_t u32_to_fixed16(u32 val)
• drivers/gpu/drm/i915/i915_fixed.h:60:55-60:59: static inline uint_fixed_16_16_t clamp_u64_to_fixed16(u64 val)
• drivers/gpu/drm/i915/i915_fixed.h:69:40-69:59: static inline u32 div_round_up_fixed16(uint_fixed_16_16_t val,
• drivers/gpu/drm/i915/i915_fixed.h:75:44-75:48: static inline u32 mul_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t mul)
• drivers/gpu/drm/i915/i915_fixed.h:86:46-86:65: static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
• drivers/gpu/drm/i915/i915_fixed.h:97:46-97:50: static inline uint_fixed_16_16_t div_fixed16(u32 val, u32 d)
• drivers/gpu/drm/i915/i915_fixed.h:107:44-107:48: static inline u32 div_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t d)
• drivers/gpu/drm/i915/i915_fixed.h:118:50-118:54: static inline uint_fixed_16_16_t mul_u32_fixed16(u32 val, uint_fixed_16_16_t mul)
• drivers/gpu/drm/i915/i915_hwmon.c:316:49-316:55: hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
• drivers/gpu/drm/i915/i915_hwmon.c:363:46-363:52: hwm_power_max_read(struct hwm_drvdata *ddat, long *val)
• drivers/gpu/drm/i915/i915_hwmon.c:397:47-397:52: hwm_power_max_write(struct hwm_drvdata *ddat, long val)
• drivers/gpu/drm/i915/i915_hwmon.c:454:62-454:68: hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
• drivers/gpu/drm/i915/i915_hwmon.c:485:63-485:68: hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
• drivers/gpu/drm/i915/i915_hwmon.c:554:53-554:59: hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val)
• drivers/gpu/drm/i915/i915_hwmon.c:581:51-581:57: hwm_curr_read(struct hwm_drvdata *ddat, u32 attr, long *val)
• drivers/gpu/drm/i915/i915_hwmon.c:602:52-602:57: hwm_curr_write(struct hwm_drvdata *ddat, u32 attr, long val)
• drivers/gpu/drm/i915/i915_hwmon.c:637:16-637:22: int channel, long *val)
• drivers/gpu/drm/i915/i915_hwmon.c:657:17-657:22: int channel, long val)
• drivers/gpu/drm/i915/i915_hwmon.c:698:19-698:25: int channel, long *val)
• drivers/gpu/drm/i915/i915_mitigations.c:30:28-30:40: static int mitigations_set(const char *val, const struct kernel_param *kp)
• drivers/gpu/drm/i915/i915_params.c:232:10-232:15: bool val)
• drivers/gpu/drm/i915/i915_params.c:238:9-238:13: int val)
• drivers/gpu/drm/i915/i915_params.c:244:10-244:23: unsigned int val)
• drivers/gpu/drm/i915/i915_params.c:250:11-250:25: unsigned long val)
• drivers/gpu/drm/i915/i915_params.c:256:11-256:23: const char *val)
• drivers/gpu/drm/i915/i915_perf.c:4547:36-4547:40: static u32 mask_reg_value(u32 reg, u32 val)
• drivers/gpu/drm/i915/i915_pmu.c:200:68-200:72: store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
• drivers/gpu/drm/i915/i915_pmu.c:206:71-206:75: add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, u32 mul)
• drivers/gpu/drm/i915/i915_pmu.c:334:44-334:48: add_sample(struct i915_pmu_sample *sample, u32 val)
• drivers/gpu/drm/i915/i915_request.c:221:58-221:61: static void __i915_request_fill(struct i915_request *rq, u8 val)
• drivers/gpu/drm/i915/i915_trace.h:645:1-645:1: TRACE_EVENT_CONDITION(i915_reg_rw,
• drivers/gpu/drm/i915/intel_pcode.c:56:6-56:11: u32 *val, u32 *val1,
• drivers/gpu/drm/i915/intel_pcode.c:95:59-95:64: int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
• drivers/gpu/drm/i915/intel_pcode.c:112:68-112:72: int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
• drivers/gpu/drm/i915/intel_pcode.c:245:78-245:83: int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)
• drivers/gpu/drm/i915/intel_pcode.c:261:79-261:83: int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)
• drivers/gpu/drm/i915/intel_sbi.c:15:4-15:9: u32 *val, bool is_read)
• drivers/gpu/drm/i915/intel_uncore.c:2160:1-2160:1: __gen_fwtable_write(32)
• drivers/gpu/drm/i915/intel_uncore.c:2172:1-2172:1: __vgpu_write(8)
• drivers/gpu/drm/i915/intel_uncore.c:2173:1-2173:1: __vgpu_write(16)
• drivers/gpu/drm/i915/intel_uncore.c:2174:1-2174:1: __vgpu_write(32)
• drivers/gpu/drm/i915/intel_uncore.c:2100:1-2100:1: __gen5_write(8)
• drivers/gpu/drm/i915/intel_uncore.c:2101:1-2101:1: __gen5_write(16)
• drivers/gpu/drm/i915/intel_uncore.c:2102:1-2102:1: __gen5_write(32)
• drivers/gpu/drm/i915/intel_uncore.c:2103:1-2103:1: __gen2_write(8)
• drivers/gpu/drm/i915/intel_uncore.c:2104:1-2104:1: __gen2_write(16)
• drivers/gpu/drm/i915/intel_uncore.c:2105:1-2105:1: __gen2_write(32)
• drivers/gpu/drm/i915/intel_uncore.c:2136:1-2136:1: __gen6_write(8)
• drivers/gpu/drm/i915/intel_uncore.c:2137:1-2137:1: __gen6_write(16)
• drivers/gpu/drm/i915/intel_uncore.c:2138:1-2138:1: __gen6_write(32)
• drivers/gpu/drm/i915/intel_uncore.c:2158:1-2158:1: __gen_fwtable_write(8)
• drivers/gpu/drm/i915/intel_uncore.c:2159:1-2159:1: __gen_fwtable_write(16)
• drivers/gpu/drm/i915/intel_uncore.h:349:1-349:1: __raw_write(8, b)
• drivers/gpu/drm/i915/intel_uncore.h:350:1-350:1: __raw_write(16, w)
• drivers/gpu/drm/i915/intel_uncore.h:351:1-351:1: __raw_write(32, l)
• drivers/gpu/drm/i915/intel_uncore.h:352:1-352:1: __raw_write(64, q)
• drivers/gpu/drm/i915/intel_uncore.h:377:1-377:1: __uncore_write(write8, 8, b, true)
• drivers/gpu/drm/i915/intel_uncore.h:378:1-378:1: __uncore_write(write16, 16, w, true)
• drivers/gpu/drm/i915/intel_uncore.h:379:1-379:1: __uncore_write(write, 32, l, true)
• drivers/gpu/drm/i915/intel_uncore.h:380:1-380:1: __uncore_write(write_notrace, 32, l, false)
• drivers/gpu/drm/i915/intel_uncore.h:488:23-488:27: i915_reg_t reg, u32 val,
• drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c:39:42-39:47: static int pxp_terminate_get(void *data, u64 *val)
• drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c:45:42-45:46: static int pxp_terminate_set(void *data, u64 val)
• drivers/gpu/drm/i915/selftests/intel_memory_region.c:683:70-683:74: static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
• drivers/gpu/drm/i915/selftests/mock_uncore.c:30:1-30:1: __nop_write(8)
• drivers/gpu/drm/i915/selftests/mock_uncore.c:31:1-31:1: __nop_write(16)
• drivers/gpu/drm/i915/selftests/mock_uncore.c:32:1-32:1: __nop_write(32)
• drivers/gpu/drm/i915/soc/intel_dram.c:201:30-201:34: static int skl_get_dimm_size(u16 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:206:31-206:35: static int skl_get_dimm_width(u16 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:223:31-223:35: static int skl_get_dimm_ranks(u16 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:234:30-234:34: static int icl_get_dimm_size(u16 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:239:31-239:35: static int icl_get_dimm_width(u16 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:256:31-256:35: static int icl_get_dimm_ranks(u16 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:276:39-276:43: int channel, char dimm_name, u16 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:297:19-297:23: int channel, u32 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:415:30-415:34: static int bxt_get_dimm_size(u32 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:434:31-434:35: static int bxt_get_dimm_width(u32 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:444:31-444:35: static int bxt_get_dimm_ranks(u32 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:460:47-460:51: static enum intel_dram_type bxt_get_dimm_type(u32 val)
• drivers/gpu/drm/i915/soc/intel_dram.c:480:60-480:64: static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
• drivers/gpu/drm/i915/vlv_sideband.c:79:17-79:22: u32 addr, u32 *val)
• drivers/gpu/drm/i915/vlv_sideband.c:137:62-137:66: int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
• drivers/gpu/drm/i915/vlv_sideband.c:153:62-153:66: void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
• drivers/gpu/drm/i915/vlv_sideband.c:180:28-180:32: u8 port, u32 reg, u32 val)
• drivers/gpu/drm/i915/vlv_sideband.c:196:60-196:64: void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
• drivers/gpu/drm/i915/vlv_sideband.c:212:60-212:64: void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
• drivers/gpu/drm/i915/vlv_sideband.c:249:32-249:36: enum pipe pipe, int reg, u32 val)
• drivers/gpu/drm/i915/vlv_sideband.c:265:64-265:68: void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
• drivers/gpu/drm/i915/vlv_suspend.c:280:17-280:21: u32 mask, u32 val)
• drivers/gpu/drm/ingenic/ingenic-ipu.c:680:42-680:47: struct drm_property *property, u64 *val)
• drivers/gpu/drm/ingenic/ingenic-ipu.c:695:42-695:46: struct drm_property *property, u64 val)
• drivers/gpu/drm/kmb/kmb_plane.c:306:5-306:19: unsigned int *val)
• drivers/gpu/drm/loongson/lsdc_drv.h:351:70-351:74: static inline void lsdc_wreg32(struct lsdc_device *ldev, u32 offset, u32 val)
• drivers/gpu/drm/loongson/lsdc_drv.h:383:31-383:35: u32 offset, u32 pipe, u32 val)
• drivers/gpu/drm/mgag200/mgag200_i2c.c:42:65-42:69: static void mga_i2c_set_gpio(struct mga_device *mdev, int mask, int val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1172:62-1172:87: static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1178:62-1178:87: static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1184:63-1184:88: static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1190:63-1190:88: static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1196:63-1196:88: static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1202:63-1202:88: static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1208:63-1208:88: static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1214:64-1214:89: static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1220:64-1220:89: static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1226:62-1226:87: static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1232:62-1232:87: static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1240:62-1240:71: static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1246:53-1246:62: static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1357:59-1357:78: static inline uint32_t A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT(enum perf_mode_cnt val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1371:55-1371:64: static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1398:63-1398:72: static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1408:57-1408:66: static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1417:63-1417:72: static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1443:53-1443:62: static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1449:54-1449:63: static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1479:55-1479:64: static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1488:60-1488:69: static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1494:60-1494:69: static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1504:67-1504:76: static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1510:67-1510:76: static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1572:64-1572:73: static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1583:61-1583:70: static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1593:60-1593:69: static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1600:65-1600:74: static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1606:69-1606:78: static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1623:59-1623:68: static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1629:58-1629:67: static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1637:50-1637:73: static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1643:54-1643:63: static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1650:50-1650:59: static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1656:48-1656:57: static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1662:48-1662:57: static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1670:56-1670:84: static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1676:54-1676:63: static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1689:55-1689:64: static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1695:55-1695:64: static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1704:55-1704:64: static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1710:55-1710:64: static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1718:51-1718:59: static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1724:51-1724:59: static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1734:55-1734:64: static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1740:55-1740:64: static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1749:55-1749:64: static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1755:55-1755:64: static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1787:50-1787:59: static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1793:52-1793:61: static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1799:51-1799:60: static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1807:61-1807:70: static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1813:62-1813:71: static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1819:67-1819:76: static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1827:58-1827:67: static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1833:59-1833:68: static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1839:64-1839:73: static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1849:48-1849:54: static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1857:49-1857:55: static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1865:48-1865:54: static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1873:49-1873:55: static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1881:48-1881:54: static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1889:49-1889:55: static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1897:53-1897:62: static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1903:53-1903:62: static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1913:61-1913:70: static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1919:60-1919:85: static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1925:60-1925:69: static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1936:60-1936:85: static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1942:59-1942:68: static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1953:62-1953:71: static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1959:67-1959:76: static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1967:56-1967:65: static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1973:56-1973:65: static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1979:56-1979:65: static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1985:56-1985:65: static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1991:56-1991:65: static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:1997:56-1997:65: static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2003:56-2003:65: static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2009:56-2009:65: static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2017:56-2017:65: static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2023:56-2023:65: static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2029:57-2029:66: static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2035:57-2035:66: static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2041:57-2041:66: static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2047:57-2047:66: static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2053:57-2053:66: static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2059:57-2059:66: static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2067:48-2067:57: static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2073:48-2073:57: static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2081:48-2081:57: static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2087:48-2087:57: static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2097:58-2097:78: static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2103:62-2103:81: static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2109:57-2109:82: static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2115:59-2115:81: static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2124:62-2124:71: static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2138:51-2138:76: static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2145:57-2145:82: static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2151:57-2151:80: static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2157:58-2157:81: static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2163:58-2163:81: static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2169:60-2169:85: static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2175:60-2175:83: static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2181:61-2181:84: static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2187:61-2187:84: static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2195:61-2195:89: static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2201:61-2201:87: static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2207:62-2207:90: static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2213:61-2213:89: static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2219:61-2219:87: static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2225:62-2225:90: static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2235:56-2235:81: static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2246:54-2246:63: static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2252:57-2252:84: static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2258:57-2258:82: static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2265:67-2265:76: static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2271:67-2271:76: static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2277:67-2277:76: static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2283:67-2283:76: static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2291:59-2291:68: static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2297:56-2297:65: static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2303:68-2303:77: static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2313:63-2313:87: static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2329:57-2329:85: static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2335:60-2335:86: static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2341:59-2341:85: static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2377:59-2377:68: static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2383:56-2383:65: static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2389:68-2389:77: static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2397:55-2397:79: static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2409:45-2409:54: static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2415:47-2415:56: static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2421:46-2421:55: static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2427:47-2427:56: static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2437:53-2437:59: static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2443:52-2443:58: static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2451:52-2451:58: static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2457:52-2457:58: static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2465:51-2465:57: static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2473:61-2473:70: static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2479:61-2479:70: static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2485:66-2485:100: static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2491:64-2491:96: static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2500:58-2500:67: static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2511:55-2511:64: static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2522:62-2522:71: static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2528:61-2528:70: static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2536:55-2536:78: static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2542:55-2542:78: static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2548:55-2548:78: static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2556:52-2556:58: static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2564:52-2564:58: static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2572:52-2572:58: static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2580:52-2580:58: static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2588:46-2588:55: static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2594:46-2594:55: static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2602:46-2602:55: static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2608:46-2608:55: static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2622:73-2622:82: static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2630:63-2630:72: static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2638:64-2638:96: static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2645:56-2645:65: static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2655:48-2655:57: static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2663:59-2663:89: static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2670:54-2670:77: static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2676:52-2676:61: static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2682:59-2682:86: static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2688:59-2688:84: static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2700:51-2700:60: static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2706:51-2706:60: static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2980:43-2980:60: static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2986:45-2986:62: static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2992:45-2992:62: static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:2998:45-2998:62: static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3004:45-3004:62: static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3010:46-3010:64: static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3016:46-3016:64: static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3022:46-3022:64: static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3028:44-3028:53: static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3037:45-3037:72: static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3043:49-3043:68: static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3049:51-3049:60: static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3056:51-3056:76: static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3062:51-3062:60: static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3070:44-3070:53: static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3076:45-3076:54: static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3082:44-3082:53: static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3090:49-3090:72: static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3096:45-3096:62: static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3102:45-3102:62: static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3108:45-3108:62: static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3114:45-3114:62: static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3120:49-3120:57: static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3126:52-3126:71: static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3132:52-3132:71: static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3138:49-3138:68: static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3144:51-3144:76: static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3150:50-3150:59: static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3158:53-3158:72: static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3164:53-3164:72: static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3170:52-3170:61: static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3176:52-3176:61: static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3184:47-3184:53: static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3190:56-3190:65: static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3196:56-3196:65: static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3204:51-3204:76: static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3211:48-3211:57: static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3217:49-3217:55: static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3223:48-3223:70: static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val)
• drivers/gpu/drm/msm/adreno/a2xx.xml.h:3230:50-3230:59: static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:947:68-947:77: static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:955:54-955:63: static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:961:54-961:63: static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:969:51-969:57: static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:977:50-977:56: static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:985:51-985:57: static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:993:50-993:56: static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1001:51-1001:57: static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1009:50-1009:56: static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1017:54-1017:60: static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1023:54-1023:60: static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1031:48-1031:54: static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1039:59-1039:65: static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1047:56-1047:62: static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1058:64-1058:70: static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1067:57-1067:79: static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1073:58-1073:81: static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1079:57-1079:66: static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1088:57-1088:66: static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1094:57-1094:66: static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1103:57-1103:66: static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1109:57-1109:66: static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1118:57-1118:66: static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1124:57-1124:66: static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1133:57-1133:66: static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1139:57-1139:66: static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1148:57-1148:79: static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1154:49-1154:58: static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1168:57-1168:66: static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1176:58-1176:67: static inline uint32_t A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1185:63-1185:88: static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1196:53-1196:76: static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1202:57-1202:66: static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1210:47-1210:56: static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1216:48-1216:54: static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1229:53-1229:72: static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1235:56-1235:83: static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1241:61-1241:70: static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1249:58-1249:78: static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1255:61-1255:81: static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1261:56-1261:77: static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1268:61-1268:70: static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1276:60-1276:69: static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1284:65-1284:93: static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1290:67-1290:93: static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1296:66-1296:94: static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1302:67-1302:95: static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1308:69-1308:95: static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1314:68-1314:96: static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1323:47-1323:56: static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1329:48-1329:54: static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1337:49-1337:58: static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1343:50-1343:56: static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1351:48-1351:57: static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1357:49-1357:55: static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1365:49-1365:58: static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1371:50-1371:56: static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1387:58-1387:81: static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1394:50-1394:83: static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1401:55-1401:64: static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1408:55-1408:64: static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1416:52-1416:61: static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1424:54-1424:63: static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1432:52-1432:72: static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1438:54-1438:74: static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1444:52-1444:73: static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1450:59-1450:86: static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1456:64-1456:73: static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1462:54-1462:84: static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1474:52-1474:77: static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1486:56-1486:84: static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1492:54-1492:63: static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1500:44-1500:53: static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1511:53-1511:78: static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1517:53-1517:76: static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1523:54-1523:77: static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1529:54-1529:77: static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1535:56-1535:81: static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1541:56-1541:79: static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1547:57-1547:80: static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1553:57-1553:80: static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1563:58-1563:67: static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1571:46-1571:55: static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1579:58-1579:67: static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1585:59-1585:68: static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1591:64-1591:73: static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1599:61-1599:70: static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1605:62-1605:71: static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1611:67-1611:76: static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1622:48-1622:57: static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1628:48-1628:57: static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1650:53-1650:62: static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1656:50-1656:59: static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1666:60-1666:69: static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1672:67-1672:93: static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1678:66-1678:92: static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1692:61-1692:82: static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1702:69-1702:78: static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1710:58-1710:67: static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1722:61-1722:82: static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1729:65-1729:74: static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1735:65-1735:74: static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1743:62-1743:71: static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1749:62-1749:71: static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1755:67-1755:76: static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1763:67-1763:76: static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1769:70-1769:79: static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1775:69-1775:78: static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1781:72-1781:81: static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1789:61-1789:70: static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1795:66-1795:75: static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1801:61-1801:70: static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1809:61-1809:70: static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1815:66-1815:75: static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1821:61-1821:70: static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1829:69-1829:78: static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1835:67-1835:76: static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1843:69-1843:78: static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1849:67-1849:76: static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1857:59-1857:68: static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1863:62-1863:71: static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1869:62-1869:71: static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1875:62-1875:71: static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1905:57-1905:66: static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1911:54-1911:63: static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1917:59-1917:68: static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1923:61-1923:70: static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1931:54-1931:63: static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1937:56-1937:65: static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1943:56-1943:65: static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1949:53-1949:62: static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1955:54-1955:63: static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1973:57-1973:66: static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1979:57-1979:66: static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1987:57-1987:66: static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:1993:56-1993:65: static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2005:56-2005:65: static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2012:53-2012:71: static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2018:52-2018:61: static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2025:51-2025:72: static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2031:55-2031:64: static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2041:72-2041:81: static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2047:69-2047:78: static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2055:48-2055:57: static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2062:49-2062:58: static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2068:45-2068:54: static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2076:53-2076:62: static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2082:53-2082:62: static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2092:56-2092:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2098:56-2098:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2104:56-2104:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2110:56-2110:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2116:56-2116:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2122:56-2122:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2128:56-2128:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2134:56-2134:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2140:56-2140:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2146:56-2146:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2152:56-2152:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2158:56-2158:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2164:56-2164:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2170:56-2170:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2176:56-2176:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2182:56-2182:76: static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2192:57-2192:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2198:57-2198:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2204:57-2204:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2210:57-2210:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2216:57-2216:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2222:57-2222:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2228:57-2228:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2234:57-2234:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2240:57-2240:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2246:57-2246:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2252:57-2252:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2258:57-2258:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2264:57-2264:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2270:57-2270:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2276:57-2276:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2282:57-2282:77: static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2295:54-2295:63: static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2302:54-2302:63: static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2308:51-2308:60: static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2316:56-2316:77: static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2322:61-2322:87: static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2330:62-2330:71: static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2336:62-2336:71: static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2342:56-2342:77: static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2349:52-2349:61: static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2357:57-2357:66: static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2363:60-2363:69: static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2369:64-2369:73: static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2377:54-2377:63: static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2383:56-2383:65: static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2390:59-2390:68: static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2400:51-2400:60: static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2407:54-2407:63: static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2413:51-2413:60: static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2420:54-2420:63: static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2430:55-2430:64: static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2436:55-2436:64: static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2442:55-2442:64: static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2448:55-2448:64: static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2456:71-2456:80: static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2462:68-2462:77: static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2468:66-2468:75: static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2478:68-2478:77: static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2484:67-2484:76: static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2490:74-2490:83: static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2498:61-2498:70: static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2504:71-2504:80: static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2514:59-2514:68: static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2522:56-2522:77: static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2528:61-2528:87: static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2536:62-2536:71: static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2542:62-2542:71: static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2551:56-2551:77: static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2560:52-2560:61: static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2568:57-2568:66: static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2574:60-2574:69: static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2580:64-2580:73: static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2586:63-2586:72: static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2594:71-2594:80: static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2600:68-2600:77: static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2606:66-2606:75: static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2616:68-2616:77: static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2622:67-2622:76: static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2628:74-2628:83: static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2636:61-2636:70: static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2642:71-2642:80: static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2656:50-2656:59: static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2663:58-2663:67: static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2673:49-2673:58: static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2686:62-2686:82: static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2694:59-2694:68: static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2704:65-2704:74: static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2710:64-2710:73: static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2716:64-2716:73: static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2726:65-2726:74: static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2732:64-2732:73: static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2738:64-2738:73: static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2822:48-2822:57: static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2828:49-2828:58: static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2840:47-2840:56: static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2846:47-2846:56: static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2852:47-2852:56: static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2858:47-2858:56: static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2911:61-2911:70: static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2917:62-2917:71: static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2965:61-2965:70: static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2973:61-2973:70: static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:2979:63-2979:86: static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3026:58-3026:78: static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3032:62-3032:81: static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3038:57-3038:82: static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3044:59-3044:81: static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3053:62-3053:71: static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3065:47-3065:68: static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3071:47-3071:68: static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3077:47-3077:67: static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3083:47-3083:67: static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3089:47-3089:67: static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3095:46-3095:66: static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3101:53-3101:78: static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3111:49-3111:55: static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3117:48-3117:54: static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3123:48-3123:54: static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3131:51-3131:71: static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3138:48-3138:67: static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3144:48-3144:67: static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3150:48-3150:67: static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3156:48-3156:67: static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3162:49-3162:58: static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3168:49-3168:68: static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3174:45-3174:63: static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3181:46-3181:65: static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3189:48-3189:57: static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3195:47-3195:56: static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3201:52-3201:61: static inline uint32_t A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3209:46-3209:55: static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3215:47-3215:56: static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3221:46-3221:67: static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3229:50-3229:59: static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3235:47-3235:56: static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a3xx.xml.h:3241:50-3241:59: static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:845:48-845:57: static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:902:61-902:70: static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:908:62-908:71: static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:924:51-924:60: static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:930:52-930:61: static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:944:53-944:62: static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:952:59-952:68: static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:961:61-961:70: static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:980:53-980:72: static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:986:61-986:70: static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:994:58-994:78: static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1000:61-1000:81: static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1006:57-1006:84: static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1012:56-1012:77: static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1019:61-1019:70: static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1029:52-1029:61: static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1037:65-1037:93: static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1043:67-1043:93: static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1049:66-1049:94: static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1055:67-1055:95: static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1061:69-1061:95: static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1067:68-1067:96: static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1075:47-1075:56: static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1081:47-1081:56: static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1087:48-1087:54: static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1095:46-1095:52: static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1103:49-1103:58: static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1109:49-1109:58: static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1115:50-1115:56: static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1123:48-1123:54: static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1131:48-1131:57: static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1137:48-1137:57: static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1143:49-1143:55: static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1151:47-1151:53: static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1159:49-1159:58: static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1165:49-1165:58: static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1171:50-1171:56: static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1179:48-1179:54: static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1187:56-1187:65: static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1194:62-1194:87: static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1202:55-1202:64: static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1209:54-1209:63: static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1218:58-1218:67: static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1226:54-1226:63: static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1232:54-1232:63: static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1238:54-1238:63: static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1244:54-1244:63: static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1250:54-1250:63: static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1256:54-1256:63: static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1262:54-1262:63: static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1268:54-1268:63: static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1276:58-1276:81: static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1282:50-1282:83: static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1288:55-1288:64: static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1294:55-1294:64: static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1302:52-1302:61: static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1310:54-1310:63: static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1318:54-1318:74: static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1324:52-1324:73: static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1330:59-1330:86: static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1336:64-1336:73: static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1342:54-1342:84: static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1348:52-1348:72: static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1356:50-1356:59: static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1368:52-1368:77: static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1382:56-1382:79: static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1388:54-1388:63: static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1396:44-1396:53: static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1404:45-1404:54: static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1415:53-1415:78: static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1421:53-1421:76: static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1427:54-1427:77: static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1433:54-1433:77: static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1439:56-1439:81: static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1445:56-1445:79: static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1451:57-1451:80: static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1457:57-1457:80: static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1469:58-1469:67: static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1477:46-1477:55: static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1485:58-1485:67: static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1491:59-1491:68: static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1497:64-1497:73: static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1505:61-1505:70: static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1511:62-1511:71: static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1517:67-1517:76: static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1526:45-1526:54: static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:1532:45-1532:54: static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2200:54-2200:63: static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2206:53-2206:62: static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2212:55-2212:64: static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2218:54-2218:63: static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2300:56-2300:77: static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2308:62-2308:71: static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2314:62-2314:71: static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2320:61-2320:70: static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2326:56-2326:77: static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2336:57-2336:66: static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2342:64-2342:73: static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2350:54-2350:63: static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2356:56-2356:65: static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2362:59-2362:68: static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2372:51-2372:60: static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2378:54-2378:63: static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2384:51-2384:60: static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2390:54-2390:63: static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2400:55-2400:64: static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2406:55-2406:64: static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2412:55-2412:64: static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2418:55-2418:64: static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2426:68-2426:77: static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2432:66-2432:75: static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2448:56-2448:77: static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2456:62-2456:71: static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2462:62-2462:71: static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2468:61-2468:70: static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2474:56-2474:77: static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2484:57-2484:66: static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2495:68-2495:77: static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2501:66-2501:75: static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2517:50-2517:59: static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2524:58-2524:67: static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2530:63-2530:72: static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2540:49-2540:58: static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2549:53-2549:73: static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2558:56-2558:77: static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2566:62-2566:71: static inline uint32_t A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2572:62-2572:71: static inline uint32_t A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2578:61-2578:70: static inline uint32_t A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2584:56-2584:77: static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2606:68-2606:77: static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2612:66-2612:75: static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2628:54-2628:63: static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2634:59-2634:68: static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2644:51-2644:60: static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2650:54-2650:63: static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2656:51-2656:60: static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2662:54-2662:63: static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2672:55-2672:64: static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2678:55-2678:64: static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2684:55-2684:64: static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2690:55-2690:64: static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2698:68-2698:77: static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2704:66-2704:75: static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2720:54-2720:63: static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2726:55-2726:64: static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2732:59-2732:68: static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2742:51-2742:60: static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2748:54-2748:63: static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2754:51-2754:60: static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2760:54-2760:63: static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2770:55-2770:64: static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2776:55-2776:64: static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2782:55-2782:64: static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2788:55-2788:64: static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2796:68-2796:77: static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2802:66-2802:75: static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2832:48-2832:57: static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2839:49-2839:58: static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2848:51-2848:60: static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2854:53-2854:62: static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2860:53-2860:62: static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2878:48-2878:57: static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2884:49-2884:58: static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2900:51-2900:60: static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2906:51-2906:60: static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2912:51-2912:60: static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2918:51-2918:60: static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2962:57-2962:66: static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2968:57-2968:66: static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2974:59-2974:68: static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2980:61-2980:70: static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2988:54-2988:63: static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:2994:53-2994:62: static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3000:54-3000:63: static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3010:56-3010:65: static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3016:55-3016:64: static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3022:55-3022:64: static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3036:57-3036:66: static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3042:57-3042:66: static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3054:52-3054:61: static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3062:56-3062:65: static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3072:56-3072:65: static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3079:53-3079:71: static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3085:52-3085:61: static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3092:51-3092:72: static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3098:55-3098:64: static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3130:50-3130:59: static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3136:50-3136:59: static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3142:50-3142:59: static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3148:50-3148:59: static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3164:53-3164:62: static inline uint32_t A4XX_TPL1_TP_FS_TEX_COUNT_FS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3170:53-3170:62: static inline uint32_t A4XX_TPL1_TP_FS_TEX_COUNT_CS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3216:54-3216:63: static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3222:54-3222:63: static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3230:53-3230:59: static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3238:52-3238:58: static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3246:53-3246:59: static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3254:52-3254:58: static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3262:53-3262:59: static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3270:52-3270:58: static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3278:54-3278:60: static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3284:54-3284:60: static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3292:48-3292:54: static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3304:55-3304:61: static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3312:56-3312:62: static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3320:55-3320:61: static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3328:55-3328:78: static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3339:64-3339:70: static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3350:57-3350:79: static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3356:58-3356:67: static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3363:57-3363:66: static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3372:57-3372:66: static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3378:57-3378:66: static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3387:57-3387:66: static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3393:57-3393:66: static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3402:57-3402:66: static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3408:57-3408:66: static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3417:57-3417:66: static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3423:57-3423:66: static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3432:56-3432:65: static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3438:56-3438:65: static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3447:56-3447:65: static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3453:56-3453:65: static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3515:61-3515:82: static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3525:58-3525:67: static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3537:61-3537:82: static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3545:59-3545:68: static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3551:61-3551:70: static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3559:67-3559:76: static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3565:58-3565:67: static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3571:63-3571:72: static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3577:65-3577:74: static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3585:63-3585:72: static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3591:64-3591:73: static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3597:66-3597:75: static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3603:67-3603:76: static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3611:64-3611:73: static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3617:65-3617:74: static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3625:61-3625:70: static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3631:67-3631:76: static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3639:65-3639:74: static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3645:61-3645:70: static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3653:61-3653:70: static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3659:67-3659:76: static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3667:65-3667:74: static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3673:61-3673:70: static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3681:61-3681:70: static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3687:67-3687:76: static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3695:65-3695:74: static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3701:61-3701:70: static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3709:61-3709:70: static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3715:67-3715:76: static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3723:65-3723:74: static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3729:61-3729:70: static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3737:61-3737:70: static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3743:67-3743:76: static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3751:65-3751:74: static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3757:61-3757:70: static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3765:61-3765:70: static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3771:67-3771:76: static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3779:65-3779:74: static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3785:61-3785:70: static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3793:57-3793:66: static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3799:58-3799:67: static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3805:58-3805:67: static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3811:58-3811:67: static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3819:54-3819:63: static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3829:54-3829:63: static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3839:54-3839:63: static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3849:59-3849:68: static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3855:64-3855:73: static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3861:60-3861:69: static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3869:59-3869:68: static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3875:68-3875:77: static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3883:62-3883:71: static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3889:63-3889:72: static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3903:59-3903:68: static inline uint32_t A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3938:53-3938:62: static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3944:50-3944:59: static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3952:53-3952:62: static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3963:68-3963:94: static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3969:67-3969:93: static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3980:54-3980:63: static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3986:53-3986:62: static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:3992:50-3992:76: static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4001:54-4001:63: static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4007:49-4007:72: static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4115:47-4115:68: static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4121:47-4121:68: static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4127:47-4127:67: static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4133:47-4133:67: static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4139:47-4139:67: static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4145:46-4145:66: static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4151:49-4151:55: static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4159:53-4159:78: static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4168:48-4168:54: static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4174:48-4174:54: static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4184:48-4184:67: static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4190:48-4190:67: static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4196:48-4196:67: static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4202:48-4202:67: static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4208:49-4208:58: static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4214:45-4214:63: static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4220:46-4220:65: static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4228:48-4228:57: static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4234:47-4234:56: static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4242:52-4242:61: static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4249:47-4249:56: static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4255:46-4255:67: static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4263:49-4263:58: static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4269:47-4269:56: static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4277:49-4277:58: static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4283:46-4283:55: static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4297:43-4297:52: static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4305:44-4305:53: static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4313:50-4313:59: static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4321:42-4321:51: static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4329:42-4329:51: static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4335:42-4335:62: static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4341:44-4341:53: static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4349:45-4349:54: static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a4xx.xml.h:4355:44-4355:53: static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1043:54-1043:63: static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1049:53-1049:62: static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1055:55-1055:64: static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1061:54-1061:63: static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1838:58-1838:67: static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1844:61-1844:70: static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1850:51-1850:60: static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1856:50-1856:59: static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1862:51-1862:60: static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1868:49-1868:58: static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1874:51-1874:60: static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1880:50-1880:59: static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1886:51-1886:60: static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1892:50-1892:59: static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1898:51-1898:60: static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1904:53-1904:62: static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1910:55-1910:64: static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1916:57-1916:66: static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1922:51-1922:60: static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1928:50-1928:59: static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1934:50-1934:59: static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1940:54-1940:63: static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1946:54-1946:63: static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1952:49-1952:58: static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1958:50-1958:59: static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1964:50-1964:59: static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1970:51-1970:60: static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1976:63-1976:72: static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1982:58-1982:67: static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1988:49-1988:58: static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:1994:58-1994:67: static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2000:55-2000:64: static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2006:53-2006:62: static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2012:53-2012:62: static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2018:52-2018:61: static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2114:48-2114:57: static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2120:49-2120:58: static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2138:51-2138:60: static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2144:51-2144:60: static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2150:51-2150:60: static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2156:51-2156:60: static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2179:48-2179:57: static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2185:48-2185:57: static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2817:55-2817:64: static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2823:55-2823:64: static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2839:50-2839:59: static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2847:61-2847:70: static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2853:61-2853:70: static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2861:53-2861:59: static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2869:52-2869:58: static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2877:53-2877:59: static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2885:52-2885:58: static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2893:53-2893:59: static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2901:52-2901:58: static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2912:56-2912:62: static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2919:52-2919:72: static inline uint32_t A5XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2927:54-2927:60: static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2933:54-2933:60: static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2941:48-2941:54: static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2955:55-2955:61: static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2963:56-2963:62: static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2971:62-2971:68: static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2979:68-2979:91: static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:2995:59-2995:82: static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3003:60-3003:83: static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3015:59-3015:68: static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3021:59-3021:68: static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3030:59-3030:68: static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3036:59-3036:68: static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3045:61-3045:70: static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3051:61-3051:70: static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3060:61-3060:70: static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3066:61-3066:70: static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3075:57-3075:66: static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3081:57-3081:66: static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3090:57-3090:66: static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3096:57-3096:66: static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3113:51-3113:60: static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3125:43-3125:52: static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3131:44-3131:53: static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3145:54-3145:63: static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3151:55-3151:64: static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3159:54-3159:77: static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3167:55-3167:78: static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3182:59-3182:68: static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3195:51-3195:60: static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3204:54-3204:63: static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3210:54-3210:63: static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3216:54-3216:63: static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3222:54-3222:63: static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3228:54-3228:63: static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3234:54-3234:63: static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3240:54-3240:63: static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3246:54-3246:63: static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3259:53-3259:72: static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3265:61-3265:70: static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3273:65-3273:93: static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3279:67-3279:93: static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3285:66-3285:94: static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3291:67-3291:95: static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3297:69-3297:95: static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3303:68-3303:96: static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3311:58-3311:78: static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3317:61-3317:81: static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3323:57-3323:84: static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3329:56-3329:77: static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3338:42-3338:51: static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3346:48-3346:57: static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3358:47-3358:56: static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3364:47-3364:56: static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3370:48-3370:54: static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3378:46-3378:52: static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3386:49-3386:58: static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3392:49-3392:58: static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3398:50-3398:56: static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3406:48-3406:54: static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3414:48-3414:57: static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3420:48-3420:57: static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3426:49-3426:55: static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3434:47-3434:53: static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3442:49-3442:58: static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3448:49-3448:58: static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3454:50-3454:56: static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3462:48-3462:54: static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3470:56-3470:65: static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3477:62-3477:87: static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3485:56-3485:65: static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3493:55-3493:64: static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3507:49-3507:74: static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3516:63-3516:86: static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3528:51-3528:60: static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3536:57-3536:66: static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3547:53-3547:78: static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3553:53-3553:76: static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3559:54-3559:77: static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3565:54-3565:77: static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3571:56-3571:81: static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3577:56-3577:79: static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3583:57-3583:80: static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3589:57-3589:80: static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3604:46-3604:55: static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3612:52-3612:61: static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3620:58-3620:67: static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3626:59-3626:68: static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3632:64-3632:73: static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3640:61-3640:70: static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3646:62-3646:71: static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3652:67-3652:76: static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3661:48-3661:57: static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3667:48-3667:57: static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3678:46-3678:65: static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3687:49-3687:58: static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3693:49-3693:58: static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3702:49-3702:58: static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3708:49-3708:58: static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3723:47-3723:56: static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3731:53-3731:62: static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3749:48-3749:57: static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3769:54-3769:63: static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3777:60-3777:69: static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3789:52-3789:61: static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3797:58-3797:67: static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3809:54-3809:63: static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3836:53-3836:62: static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3842:60-3842:69: static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3848:60-3848:69: static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3856:51-3856:60: static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3862:47-3862:56: static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3885:47-3885:56: static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3891:47-3891:56: static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3898:47-3898:56: static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3904:47-3904:56: static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3929:61-3929:70: static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3943:65-3943:91: static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3949:64-3949:90: static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3958:52-3958:61: static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3970:54-3970:63: static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3976:53-3976:62: static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3982:50-3982:76: static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3990:54-3990:63: static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:3996:49-3996:72: static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4008:50-4008:59: static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4016:53-4016:62: static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4022:54-4022:63: static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4028:56-4028:65: static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4036:57-4036:66: static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4044:57-4044:66: static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4050:55-4050:64: static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4056:55-4056:64: static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4084:50-4084:59: static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4091:53-4091:71: static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4097:51-4097:72: static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4111:59-4111:68: static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4117:55-4117:64: static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4130:60-4130:69: static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4136:58-4136:67: static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4145:60-4145:69: static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4151:58-4151:67: static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4160:60-4160:69: static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4166:58-4166:67: static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4175:60-4175:69: static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4181:58-4181:67: static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4190:60-4190:69: static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4196:58-4196:67: static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4205:60-4205:69: static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4211:58-4211:67: static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4224:56-4224:77: static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4230:62-4230:71: static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4236:62-4236:71: static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4244:57-4244:66: static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4252:53-4252:62: static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4262:51-4262:60: static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4268:54-4268:63: static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4274:51-4274:60: static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4280:54-4280:63: static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4290:55-4290:64: static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4296:55-4296:64: static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4302:55-4302:64: static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4308:55-4308:64: static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4323:56-4323:77: static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4329:62-4329:71: static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4335:62-4335:71: static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4343:57-4343:66: static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4357:56-4357:65: static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4367:51-4367:60: static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4373:59-4373:68: static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4379:64-4379:73: static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4389:52-4389:61: static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4400:56-4400:76: static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4414:56-4414:77: static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4420:62-4420:71: static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4426:62-4426:71: static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4434:57-4434:66: static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4449:56-4449:77: static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4455:62-4455:71: static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4461:62-4461:71: static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4469:57-4469:66: static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4484:56-4484:77: static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4490:62-4490:71: static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4496:62-4496:71: static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4504:57-4504:66: static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4519:56-4519:77: static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4525:62-4525:71: static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4531:62-4531:71: static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4539:57-4539:66: static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4553:59-4553:82: static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4561:60-4561:83: static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4636:61-4636:82: static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4642:61-4642:82: static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4650:67-4650:76: static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4658:58-4658:67: static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4664:57-4664:66: static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4670:59-4670:68: static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4676:58-4676:67: static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4684:63-4684:72: static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4690:64-4690:73: static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4696:66-4696:75: static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4702:67-4702:76: static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4710:64-4710:73: static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4716:65-4716:74: static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4722:61-4722:70: static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4728:61-4728:70: static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4739:62-4739:71: static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4745:60-4745:69: static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4754:62-4754:71: static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4760:60-4760:69: static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4769:62-4769:71: static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4775:60-4775:69: static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4784:62-4784:71: static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4790:60-4790:69: static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4799:62-4799:71: static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4805:60-4805:69: static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4814:62-4814:71: static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4820:60-4820:69: static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4829:51-4829:60: static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4838:51-4838:60: static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4847:51-4847:60: static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4856:51-4856:60: static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4865:51-4865:60: static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4874:51-4874:60: static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4888:57-4888:66: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4894:58-4894:67: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4900:58-4900:67: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4906:58-4906:67: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4914:60-4914:69: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4922:59-4922:68: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4930:60-4930:69: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4938:59-4938:68: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4946:60-4946:69: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4954:59-4954:68: static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4962:56-4962:65: static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4968:49-4968:58: static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4974:49-4974:58: static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:4980:57-4980:66: static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5036:57-5036:77: static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5042:54-5042:74: static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5048:55-5048:76: static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5062:50-5062:59: static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5068:56-5068:65: static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5076:57-5076:77: static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5082:54-5082:74: static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5088:55-5088:76: static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5102:50-5102:59: static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5108:56-5108:65: static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5120:51-5120:60: static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5132:51-5132:60: static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5142:59-5142:79: static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5148:56-5148:76: static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5154:57-5154:78: static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5164:59-5164:79: static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5170:56-5170:76: static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5176:57-5176:78: static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5189:47-5189:68: static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5195:47-5195:68: static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5201:47-5201:67: static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5207:47-5207:67: static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5213:47-5213:67: static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5219:46-5219:66: static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5225:49-5225:55: static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5233:53-5233:78: static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5242:48-5242:54: static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5248:48-5248:54: static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5256:54-5256:63: static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5266:51-5266:71: static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5273:48-5273:67: static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5279:48-5279:67: static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5285:48-5285:67: static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5291:48-5291:67: static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5297:49-5297:58: static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5303:49-5303:72: static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5309:45-5309:63: static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5315:46-5315:67: static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5323:47-5323:56: static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5329:48-5329:57: static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5338:52-5338:61: static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5344:47-5344:56: static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5350:46-5350:65: static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5358:53-5358:62: static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5364:53-5364:62: static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5374:49-5374:58: static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5382:49-5382:58: static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5388:47-5388:56: static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5408:46-5408:55: static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5416:44-5416:53: static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5424:50-5424:59: static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5432:42-5432:51: static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5440:42-5440:60: static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5446:44-5446:53: static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5454:45-5454:54: static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5460:44-5460:53: static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5468:46-5468:55: static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5476:46-5476:55: static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5484:43-5484:52: static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx.xml.h:5492:43-5492:52: static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/a5xx_debugfs.c:93:23-93:27: reset_set(void *data, u64 val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1123:59-1123:68: static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1129:59-1129:68: static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1135:59-1135:68: static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1141:59-1141:68: static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1149:59-1149:68: static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1155:58-1155:67: static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1182:54-1182:63: static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1188:53-1188:62: static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1257:49-1257:58: static inline uint32_t A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1263:49-1263:58: static inline uint32_t A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1271:50-1271:59: static inline uint32_t A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1277:50-1277:59: static inline uint32_t A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1285:50-1285:59: static inline uint32_t A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1291:50-1291:59: static inline uint32_t A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1299:50-1299:59: static inline uint32_t A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1305:50-1305:59: static inline uint32_t A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1313:50-1313:59: static inline uint32_t A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1319:50-1319:59: static inline uint32_t A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1327:50-1327:59: static inline uint32_t A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1333:50-1333:59: static inline uint32_t A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1351:49-1351:58: static inline uint32_t A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1359:50-1359:59: static inline uint32_t A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1367:50-1367:59: static inline uint32_t A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1375:50-1375:59: static inline uint32_t A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1383:50-1383:59: static inline uint32_t A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1391:50-1391:59: static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1953:62-1953:71: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1959:64-1959:73: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1967:59-1967:68: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1973:57-1973:66: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1979:56-1979:65: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:1987:58-1987:67: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2011:60-2011:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2017:60-2017:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2023:60-2023:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2029:60-2029:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2035:60-2035:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2041:60-2041:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2047:60-2047:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2053:60-2053:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2061:60-2061:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2067:60-2067:69: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2073:61-2073:70: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2079:61-2079:70: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2085:61-2085:70: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2091:61-2091:70: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2097:61-2097:70: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2103:61-2103:70: static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2139:52-2139:61: static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2168:59-2168:68: static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2178:59-2178:68: static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2284:48-2284:57: static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2290:49-2290:58: static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2300:46-2300:55: static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2306:46-2306:55: static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2316:51-2316:60: static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2322:51-2322:60: static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2328:51-2328:60: static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2334:51-2334:60: static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2378:55-2378:64: static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2384:55-2384:64: static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2392:55-2392:64: static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2398:55-2398:64: static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2406:55-2406:64: static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2412:55-2412:64: static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2428:50-2428:59: static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2436:61-2436:70: static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2442:61-2442:70: static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2452:51-2452:57: static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2460:50-2460:56: static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2468:51-2468:57: static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2476:50-2476:56: static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2484:51-2484:57: static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2492:50-2492:56: static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2502:49-2502:55: static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2510:49-2510:55: static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2521:56-2521:62: static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2528:48-2528:57: static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2534:52-2534:72: static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2540:48-2540:57: static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2548:48-2548:57: static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2556:54-2556:60: static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2562:54-2562:60: static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2570:48-2570:54: static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2578:61-2578:82: static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2586:55-2586:61: static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2594:56-2594:62: static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2602:62-2602:68: static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2610:68-2610:91: static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2616:60-2616:69: static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2625:71-2625:80: static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2632:64-2632:73: static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2656:65-2656:74: static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2662:59-2662:86: static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2668:54-2668:76: static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2674:59-2674:86: static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2680:72-2680:104: static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2687:51-2687:60: static inline uint32_t A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2696:51-2696:60: static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2702:51-2702:60: static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2708:58-2708:80: static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2715:63-2715:90: static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2721:70-2721:79: static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2727:52-2727:61: static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2735:56-2735:79: static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2741:53-2741:62: static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2747:53-2747:62: static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2755:57-2755:80: static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2768:63-2768:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2774:63-2774:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2780:63-2780:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2786:63-2786:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2792:63-2792:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2798:63-2798:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2804:63-2804:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2810:63-2810:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2818:63-2818:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2824:63-2824:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2830:63-2830:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2836:63-2836:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2842:63-2842:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2848:63-2848:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2854:63-2854:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2860:63-2860:69: static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2872:57-2872:66: static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2878:57-2878:66: static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2886:57-2886:66: static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2892:57-2892:66: static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2902:59-2902:68: static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2908:59-2908:68: static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2916:59-2916:68: static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2922:59-2922:68: static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2930:57-2930:66: static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2936:57-2936:66: static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2944:57-2944:66: static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2950:57-2950:66: static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2964:47-2964:72: static inline uint32_t A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2975:72-2975:104: static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2983:66-2983:83: static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2991:50-2991:59: static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:2999:57-2999:66: static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3005:63-3005:72: static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3013:61-3013:70: static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3024:60-3024:69: static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3030:61-3030:70: static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3036:64-3036:73: static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3046:54-3046:73: static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3053:52-3053:61: static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3060:60-3060:77: static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3067:53-3067:62: static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3074:52-3074:61: static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3080:52-3080:70: static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3086:59-3086:81: static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3102:46-3102:55: static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3108:46-3108:55: static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3116:46-3116:55: static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3122:46-3122:55: static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3136:54-3136:63: static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3142:54-3142:63: static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3150:54-3150:63: static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3156:54-3156:63: static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3178:49-3178:58: static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3184:49-3184:58: static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3190:56-3190:78: static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3197:61-3197:88: static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3203:68-3203:77: static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3211:67-3211:76: static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3219:49-3219:58: static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3225:56-3225:78: static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3231:61-3231:88: static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3240:54-3240:63: static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3248:54-3248:77: static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3254:51-3254:60: static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3260:51-3260:60: static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3268:55-3268:78: static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3281:61-3281:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3287:61-3287:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3293:61-3293:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3299:61-3299:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3305:61-3305:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3311:61-3311:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3317:61-3317:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3323:61-3323:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3331:61-3331:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3337:61-3337:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3343:61-3343:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3349:61-3349:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3355:61-3355:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3361:61-3361:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3367:61-3367:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3373:61-3373:67: static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3387:59-3387:68: static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3400:68-3400:100: static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3417:52-3417:61: static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3425:54-3425:63: static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3431:54-3431:63: static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3437:54-3437:63: static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3443:54-3443:63: static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3449:54-3449:63: static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3455:54-3455:63: static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3461:54-3461:63: static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3467:54-3467:63: static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3475:61-3475:88: static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3481:61-3481:88: static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3487:61-3487:88: static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3493:61-3493:88: static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3499:61-3499:88: static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3505:61-3505:88: static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3511:61-3511:88: static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3517:61-3517:88: static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3559:53-3559:72: static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3565:61-3565:70: static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3573:65-3573:93: static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3579:67-3579:93: static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3585:66-3585:94: static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3591:67-3591:95: static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3597:69-3597:95: static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3603:68-3603:96: static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3611:58-3611:75: static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3617:61-3617:81: static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3623:51-3623:60: static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3629:56-3629:77: static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3637:42-3637:51: static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3645:48-3645:57: static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3653:41-3653:50: static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3661:46-3661:55: static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3669:46-3669:52: static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3677:48-3677:54: static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3685:47-3685:53: static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3693:48-3693:54: static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3701:56-3701:65: static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3708:62-3708:87: static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3716:56-3716:65: static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3726:55-3726:64: static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3734:56-3734:77: static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3744:49-3744:74: static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3755:63-3755:86: static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3761:55-3761:64: static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3769:51-3769:60: static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3777:57-3777:66: static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3785:50-3785:59: static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3793:55-3793:64: static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3801:45-3801:51: static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3809:45-3809:51: static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3820:53-3820:78: static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3826:53-3826:76: static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3832:54-3832:77: static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3838:54-3838:77: static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3844:56-3844:81: static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3850:56-3850:79: static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3856:57-3856:80: static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3862:57-3862:80: static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3874:53-3874:62: static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3882:59-3882:68: static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3890:52-3890:61: static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3898:57-3898:66: static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3906:47-3906:56: static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3912:49-3912:58: static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3920:49-3920:58: static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3926:51-3926:60: static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3934:53-3934:62: static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3940:55-3940:64: static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3948:48-3948:57: static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3954:48-3954:57: static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3969:44-3969:50: static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3977:44-3977:50: static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3985:50-3985:59: static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3991:51-3991:60: static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:3999:50-3999:59: static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4005:50-4005:59: static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4013:50-4013:59: static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4019:50-4019:59: static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4027:50-4027:59: static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4033:50-4033:59: static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4041:49-4041:58: static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4047:49-4047:58: static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4055:60-4055:83: static inline uint32_t A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4063:47-4063:56: static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4071:56-4071:76: static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4078:54-4078:77: static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4084:57-4084:78: static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4090:59-4090:76: static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4099:41-4099:50: static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4107:47-4107:56: static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4115:53-4115:62: static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4123:46-4123:55: static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4131:58-4131:67: static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4137:64-4137:73: static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4157:53-4157:62: static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4163:47-4163:56: static inline uint32_t A6XX_RB_BLIT_INFO_LAST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4169:52-4169:61: static inline uint32_t A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4179:53-4179:62: static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4187:60-4187:69: static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4193:66-4193:75: static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4203:55-4203:64: static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4211:62-4211:71: static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4217:61-4217:70: static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4223:68-4223:77: static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4233:53-4233:62: static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4241:60-4241:69: static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4247:66-4247:75: static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4255:50-4255:59: static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4271:52-4271:71: static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4278:50-4278:59: static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4285:58-4285:75: static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4292:51-4292:60: static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4299:50-4299:59: static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4305:50-4305:68: static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4311:57-4311:79: static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4321:57-4321:74: static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4327:54-4327:74: static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4333:55-4333:76: static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4341:52-4341:75: static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4354:50-4354:59: static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4363:39-4363:48: static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4371:45-4371:54: static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4379:46-4379:55: static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4387:51-4387:60: static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4395:46-4395:55: static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4403:45-4403:54: static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4411:51-4411:60: static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4419:51-4419:60: static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4427:57-4427:66: static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4450:57-4450:66: static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4456:57-4456:66: static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4462:54-4462:63: static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4469:54-4469:63: static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4478:55-4478:64: static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4486:55-4486:64: static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4493:51-4493:60: static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4517:45-4517:54: static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4525:56-4525:65: static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4533:56-4533:65: static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4539:63-4539:72: static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4545:63-4545:72: static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4553:56-4553:65: static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4559:63-4559:72: static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4565:63-4565:72: static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4573:56-4573:65: static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4579:63-4579:72: static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4585:63-4585:72: static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4593:56-4593:65: static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4599:55-4599:64: static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4607:56-4607:65: static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4613:55-4613:64: static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4621:56-4621:65: static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4627:55-4627:64: static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4639:51-4639:74: static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4663:46-4663:55: static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4672:47-4672:56: static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4678:47-4678:56: static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4685:47-4685:56: static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4691:47-4691:56: static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4700:50-4700:59: static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4710:48-4710:57: static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4718:48-4718:57: static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4726:50-4726:59: static inline uint32_t A6XX_VPC_SO_BUFFER_STRIDE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4734:50-4734:59: static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4742:47-4742:56: static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4755:55-4755:64: static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4761:53-4761:62: static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4767:50-4767:59: static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4773:50-4773:59: static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4781:55-4781:64: static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4787:53-4787:62: static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4793:50-4793:59: static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4799:50-4799:59: static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4807:55-4807:64: static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4813:53-4813:62: static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4819:50-4819:59: static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4825:50-4825:59: static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4833:53-4833:62: static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4839:50-4839:59: static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4846:50-4846:59: static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4854:60-4854:69: static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4860:60-4860:69: static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4866:60-4866:69: static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4872:60-4872:69: static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4878:62-4878:71: static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4903:51-4903:60: static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4909:52-4909:61: static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4917:50-4917:73: static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4923:49-4923:71: static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4939:61-4939:70: static inline uint32_t A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4950:50-4950:59: static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4958:54-4958:63: static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4966:51-4966:60: static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4972:48-4972:68: static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4982:50-4982:73: static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:4990:51-4990:60: static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5005:58-5005:67: static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5015:54-5015:63: static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5023:58-5023:67: static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5033:54-5033:63: static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5041:58-5041:67: static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5051:54-5051:63: static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5059:58-5059:67: static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5069:54-5069:63: static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5077:65-5077:74: static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5083:64-5083:73: static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5090:59-5090:81: static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5096:55-5096:64: static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5104:63-5104:72: static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5114:53-5114:62: static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5124:51-5124:71: static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5130:54-5130:63: static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5148:48-5148:57: static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5156:57-5156:77: static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5162:61-5162:80: static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5168:56-5168:81: static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5174:58-5174:79: static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5180:58-5180:79: static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5194:53-5194:62: static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5200:57-5200:66: static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5206:54-5206:63: static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5214:46-5214:55: static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5222:46-5222:55: static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5239:53-5239:62: static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5245:54-5245:63: static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5253:53-5253:62: static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5259:54-5259:63: static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5265:56-5265:65: static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5271:56-5271:65: static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5279:62-5279:71: static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5285:62-5285:71: static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5293:58-5293:67: static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5299:62-5299:71: static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5305:55-5305:64: static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5311:55-5311:64: static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5319:48-5319:57: static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5327:58-5327:67: static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5333:48-5333:57: static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5344:55-5344:77: static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5354:54-5354:63: static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5372:44-5372:53: static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5386:50-5386:59: static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5392:53-5392:62: static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5399:53-5399:70: static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5405:51-5405:72: static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5419:59-5419:68: static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5425:55-5425:64: static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5443:56-5443:77: static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5449:62-5449:71: static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5455:62-5455:71: static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5462:57-5462:66: static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5472:54-5472:63: static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5478:62-5478:71: static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5488:51-5488:60: static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5494:54-5494:63: static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5500:51-5500:60: static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5506:54-5506:63: static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5516:55-5516:64: static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5522:55-5522:64: static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5528:55-5528:64: static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5534:55-5534:64: static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5544:45-5544:54: static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5552:64-5552:73: static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5558:70-5558:79: static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5566:48-5566:57: static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5574:64-5574:73: static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5590:47-5590:56: static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5596:48-5596:57: static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5602:47-5602:56: static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5612:66-5612:75: static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5621:56-5621:77: static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5627:62-5627:71: static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5633:62-5633:71: static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5640:57-5640:66: static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5654:45-5654:54: static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5662:64-5662:73: static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5668:70-5668:79: static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5676:48-5676:57: static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5684:64-5684:73: static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5700:47-5700:56: static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5706:48-5706:57: static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5712:47-5712:56: static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5722:66-5722:75: static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5731:56-5731:77: static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5737:62-5737:71: static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5743:62-5743:71: static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5750:57-5750:66: static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5760:54-5760:63: static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5766:62-5766:71: static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5776:51-5776:60: static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5782:54-5782:63: static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5788:51-5788:60: static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5794:54-5794:63: static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5804:55-5804:64: static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5810:55-5810:64: static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5816:55-5816:64: static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5822:55-5822:64: static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5832:45-5832:54: static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5840:64-5840:73: static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5846:70-5846:79: static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5854:48-5854:57: static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5862:64-5862:73: static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5878:47-5878:56: static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5884:48-5884:57: static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5890:47-5890:56: static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5900:66-5900:75: static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5909:56-5909:77: static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5915:62-5915:71: static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5921:62-5921:71: static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5928:57-5928:66: static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5940:54-5940:63: static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5946:62-5946:71: static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5956:51-5956:60: static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5962:54-5962:63: static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5968:51-5968:60: static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5974:54-5974:63: static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5984:55-5984:64: static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5990:55-5990:64: static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:5996:55-5996:64: static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6002:55-6002:64: static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6012:45-6012:54: static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6020:64-6020:73: static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6026:70-6026:79: static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6034:48-6034:57: static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6042:64-6042:73: static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6058:47-6058:56: static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6064:48-6064:57: static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6070:47-6070:56: static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6080:66-6080:75: static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6088:44-6088:53: static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6096:44-6096:53: static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6104:44-6104:53: static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6112:44-6112:53: static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6120:45-6120:54: static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6128:45-6128:54: static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6136:45-6136:54: static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6144:45-6144:54: static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6152:56-6152:77: static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6167:56-6167:77: static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6173:62-6173:71: static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6179:62-6179:71: static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6186:57-6186:66: static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6198:45-6198:54: static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6206:64-6206:73: static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6212:70-6212:79: static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6220:48-6220:57: static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6228:64-6228:73: static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6237:56-6237:65: static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6258:57-6258:66: static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6264:57-6264:66: static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6270:57-6270:66: static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6276:57-6276:66: static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6282:57-6282:66: static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6288:57-6288:66: static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6294:57-6294:66: static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6300:57-6300:66: static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6309:60-6309:69: static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6315:63-6315:72: static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6321:65-6321:74: static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6329:52-6329:61: static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6339:52-6339:61: static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6350:56-6350:73: static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6361:55-6361:64: static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6370:54-6370:63: static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK6(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6380:52-6380:61: static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6386:56-6386:65: static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6392:55-6392:64: static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6398:52-6398:61: static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6404:55-6404:64: static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6413:52-6413:79: static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6423:65-6423:74: static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6429:64-6429:73: static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6441:66-6441:75: static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6449:56-6449:77: static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6459:56-6459:77: static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6465:62-6465:71: static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6471:62-6471:71: static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6478:57-6478:66: static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6486:60-6486:69: static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6500:45-6500:54: static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6508:64-6508:73: static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6514:70-6514:79: static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6522:48-6522:57: static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6530:64-6530:73: static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6546:47-6546:56: static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6552:48-6552:57: static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6558:47-6558:56: static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6568:66-6568:75: static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6576:54-6576:63: static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6582:56-6582:65: static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6588:58-6588:67: static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6594:55-6594:64: static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6602:61-6602:70: static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6609:53-6609:74: static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6618:44-6618:53: static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6626:44-6626:53: static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6634:45-6634:54: static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6642:45-6642:54: static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6652:70-6652:105: static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6658:65-6658:74: static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6666:39-6666:48: static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6677:54-6677:74: static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6691:47-6691:56: static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6697:48-6697:57: static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6703:47-6703:56: static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6715:67-6715:102: static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6721:62-6721:71: static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6729:36-6729:45: static inline uint32_t A6XX_SP_IBO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6742:59-6742:76: static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6749:51-6749:60: static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6786:61-6786:70: static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6802:57-6802:80: static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6808:54-6808:63: static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6816:58-6816:81: static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6825:58-6825:67: static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6837:64-6837:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6843:64-6843:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6849:64-6849:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6855:64-6855:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6861:64-6861:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6867:64-6867:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6873:64-6873:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6879:64-6879:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6887:64-6887:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6893:64-6893:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6899:64-6899:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6905:64-6905:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6911:64-6911:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6917:64-6917:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6923:64-6923:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6929:64-6929:70: static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6937:51-6937:60: static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6943:51-6943:60: static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6951:54-6951:74: static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6957:50-6957:59: static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6965:60-6965:77: static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6971:57-6971:77: static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6977:58-6977:79: static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6985:55-6985:78: static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:6998:53-6998:62: static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7007:53-7007:62: static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7013:54-7013:63: static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7021:42-7021:51: static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7029:53-7029:62: static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7035:54-7035:63: static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7043:49-7043:58: static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7051:54-7051:63: static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7059:49-7059:58: static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7067:48-7067:57: static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7075:54-7075:63: static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7091:48-7091:57: static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7097:48-7097:57: static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7112:57-7112:66: static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7119:57-7119:66: static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7125:52-7125:61: static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7147:51-7147:60: static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7156:51-7156:60: static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7165:51-7165:60: static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7174:51-7174:60: static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7185:63-7185:72: static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7195:55-7195:76: static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7202:49-7202:58: static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7216:58-7216:67: static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7222:57-7222:66: static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7228:59-7228:68: static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7234:58-7234:67: static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7242:58-7242:67: static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7248:57-7248:66: static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7254:59-7254:68: static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7260:58-7260:67: static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7268:63-7268:72: static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7274:64-7274:73: static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7280:66-7280:75: static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7286:67-7286:76: static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7294:63-7294:72: static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7300:64-7300:73: static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7306:66-7306:75: static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7312:67-7312:76: static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7320:64-7320:73: static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7326:65-7326:74: static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7332:61-7332:70: static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7338:61-7338:70: static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7346:64-7346:73: static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7352:65-7352:74: static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7358:61-7358:70: static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7364:61-7364:70: static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7372:64-7372:73: static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7378:70-7378:79: static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7386:64-7386:73: static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7392:70-7392:79: static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7400:51-7400:60: static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7409:57-7409:66: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7415:58-7415:67: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7421:58-7421:67: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7427:58-7427:67: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7435:60-7435:69: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7443:59-7443:68: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7451:60-7451:69: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7459:59-7459:68: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7467:60-7467:69: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7475:59-7475:68: static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7483:56-7483:65: static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7489:58-7489:67: static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7495:60-7495:69: static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7501:57-7501:66: static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7509:63-7509:72: static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7516:55-7516:76: static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7533:63-7533:72: static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7545:72-7545:107: static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7551:67-7551:76: static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7559:62-7559:71: static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7569:52-7569:61: static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7577:56-7577:65: static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7585:53-7585:62: static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7591:50-7591:70: static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7609:61-7609:70: static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7615:62-7615:71: static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7623:51-7623:60: static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7637:69-7637:104: static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7643:64-7643:73: static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7651:56-7651:65: static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7657:53-7657:73: static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7681:53-7681:62: static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7689:51-7689:60: static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7697:56-7697:65: static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7705:54-7705:63: static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7714:47-7714:68: static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7720:47-7720:68: static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7726:47-7726:67: static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7732:47-7732:67: static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7738:47-7738:67: static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7744:46-7744:66: static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7750:49-7750:55: static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7759:53-7759:78: static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7768:48-7768:54: static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7774:48-7774:54: static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7782:55-7782:80: static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7789:47-7789:56: static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7799:51-7799:71: static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7806:48-7806:67: static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7812:48-7812:67: static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7818:48-7818:67: static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7824:48-7824:67: static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7830:49-7830:58: static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7838:49-7838:72: static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7844:45-7844:62: static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7850:46-7850:67: static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7858:47-7858:56: static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7864:48-7864:57: static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7872:58-7872:67: static inline uint32_t A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7878:59-7878:68: static inline uint32_t A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7884:52-7884:61: static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7890:47-7890:56: static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7896:46-7896:65: static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7904:53-7904:62: static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7910:53-7910:62: static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7920:49-7920:58: static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7928:49-7928:58: static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7934:47-7934:56: static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7942:55-7942:61: static inline uint32_t A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7948:53-7948:62: static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7956:49-7956:58: static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7964:49-7964:58: static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7972:65-7972:74: static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7980:60-7980:69: static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7986:59-7986:68: static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:7992:59-7992:68: static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8010:43-8010:52: static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8018:43-8018:52: static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8024:40-8024:49: static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8086:65-8086:74: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8092:67-8092:76: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8106:62-8106:71: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8112:60-8112:69: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8118:59-8118:68: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8126:61-8126:70: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8150:63-8150:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8156:63-8156:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8162:63-8162:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8168:63-8168:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8174:63-8174:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8180:63-8180:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8186:63-8186:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8192:63-8192:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8200:63-8200:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8206:63-8206:72: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8212:64-8212:73: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8218:64-8218:73: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8224:64-8224:73: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8230:64-8230:73: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8236:64-8236:73: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx.xml.h:8242:64-8242:73: static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:53:62-53:71: static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:59:72-59:81: static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:65:59-65:68: static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:71:61-71:70: static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:77:61-77:70: static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:83:51-83:60: static inline uint32_t A6XX_GMU_OOB_DCVS_SET_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:89:53-89:62: static inline uint32_t A6XX_GMU_OOB_DCVS_CHECK_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:95:53-95:62: static inline uint32_t A6XX_GMU_OOB_DCVS_CLEAR_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:101:50-101:59: static inline uint32_t A6XX_GMU_OOB_GPU_SET_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:107:52-107:61: static inline uint32_t A6XX_GMU_OOB_GPU_CHECK_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:113:52-113:61: static inline uint32_t A6XX_GMU_OOB_GPU_CLEAR_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:119:55-119:64: static inline uint32_t A6XX_GMU_OOB_PERFCNTR_SET_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:125:57-125:66: static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CHECK_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:131:57-131:66: static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:138:47-138:56: static inline uint32_t A6XX_HFI_IRQ_DSGQ_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:144:54-144:63: static inline uint32_t A6XX_HFI_IRQ_BLOCKED_MSG_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:150:52-150:61: static inline uint32_t A6XX_HFI_IRQ_CM3_FAULT_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:156:50-156:59: static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:162:46-162:55: static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:243:73-243:82: static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:249:74-249:83: static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h:272:50-272:59: static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
• drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:56:53-56:57: static inline int CRASHDUMP_WRITE(u64 *in, u32 reg, u32 val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:230:46-230:55: static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:236:46-236:55: static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:242:49-242:58: static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:253:50-253:59: static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:259:50-259:59: static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:277:63-277:72: static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:283:63-283:72: static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:289:62-289:71: static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:297:55-297:64: static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:303:55-303:64: static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:311:47-311:56: static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:317:46-317:55: static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:323:46-323:55: static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:331:45-331:54: static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:339:46-339:55: static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:347:47-347:56: static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:353:47-353:56: static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:406:49-406:58: static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:412:49-412:58: static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:420:50-420:59: static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:426:50-426:59: static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:434:50-434:59: static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:440:50-440:59: static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:476:45-476:54: static inline uint32_t AXXX_CP_STAT_CP_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:482:56-482:65: static inline uint32_t AXXX_CP_STAT_VS_EVENT_FIFO_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:488:56-488:65: static inline uint32_t AXXX_CP_STAT_PS_EVENT_FIFO_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:494:56-494:65: static inline uint32_t AXXX_CP_STAT_CF_EVENT_FIFO_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:500:56-500:65: static inline uint32_t AXXX_CP_STAT_RB_EVENT_FIFO_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:506:45-506:54: static inline uint32_t AXXX_CP_STAT_ME_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:512:51-512:60: static inline uint32_t AXXX_CP_STAT_MIU_WR_C_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:518:48-518:57: static inline uint32_t AXXX_CP_STAT_CP_3D_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:524:49-524:58: static inline uint32_t AXXX_CP_STAT_CP_NRT_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:530:55-530:64: static inline uint32_t AXXX_CP_STAT_RBIU_SCRATCH_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:536:50-536:59: static inline uint32_t AXXX_CP_STAT_RCIU_ME_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:542:51-542:60: static inline uint32_t AXXX_CP_STAT_RCIU_PFP_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:548:51-548:60: static inline uint32_t AXXX_CP_STAT_MEQ_RING_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:554:46-554:55: static inline uint32_t AXXX_CP_STAT_PFP_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:560:51-560:60: static inline uint32_t AXXX_CP_STAT_ST_QUEUE_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:566:58-566:67: static inline uint32_t AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:572:58-572:67: static inline uint32_t AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:578:53-578:62: static inline uint32_t AXXX_CP_STAT_RING_QUEUE_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:584:46-584:55: static inline uint32_t AXXX_CP_STAT_CSF_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:590:49-590:58: static inline uint32_t AXXX_CP_STAT_CSF_ST_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:596:48-596:57: static inline uint32_t AXXX_CP_STAT_EVENT_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:602:56-602:65: static inline uint32_t AXXX_CP_STAT_CSF_INDIRECT2_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:608:56-608:65: static inline uint32_t AXXX_CP_STAT_CSF_INDIRECTS_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:614:51-614:60: static inline uint32_t AXXX_CP_STAT_CSF_RING_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:620:47-620:56: static inline uint32_t AXXX_CP_STAT_RCIU_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:626:47-626:56: static inline uint32_t AXXX_CP_STAT_RBIU_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:632:56-632:65: static inline uint32_t AXXX_CP_STAT_MIU_RD_RETURN_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_common.xml.h:638:53-638:62: static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_gpu.h:492:30-492:34: static inline u32 PM4_PARITY(u32 val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:526:48-526:57: static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:532:50-532:72: static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:538:52-538:76: static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:544:49-544:58: static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:552:51-552:74: static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:558:53-558:62: static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:566:49-566:58: static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:572:51-572:71: static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:578:53-578:75: static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:584:50-584:59: static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:592:52-592:73: static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:598:54-598:63: static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:606:57-606:66: static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:614:49-614:58: static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:620:52-620:73: static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:626:51-626:71: static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:632:53-632:75: static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:638:50-638:59: static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:646:54-646:63: static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:654:57-654:66: static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:664:49-664:58: static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:672:49-672:69: static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:678:53-678:72: static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:684:48-684:73: static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:690:50-690:72: static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:699:53-699:62: static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:707:51-707:60: static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:715:49-715:58: static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:723:49-723:58: static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:731:51-731:60: static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:739:51-739:71: static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:745:55-745:74: static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:751:50-751:75: static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:757:52-757:74: static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:766:55-766:64: static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:774:53-774:62: static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:782:56-782:76: static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:788:60-788:79: static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:794:55-794:80: static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:800:57-800:78: static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:806:57-806:78: static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:816:60-816:69: static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:824:58-824:67: static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:832:57-832:66: static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:841:59-841:68: static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:849:59-849:68: static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:859:58-859:67: static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:867:56-867:65: static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:875:56-875:65: static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:883:58-883:78: static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:889:62-889:81: static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:895:57-895:82: static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:901:59-901:80: static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:907:59-907:80: static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:918:57-918:66: static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:927:60-927:69: static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:935:60-935:69: static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:945:63-945:83: static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:951:67-951:86: static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:957:62-957:87: static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:963:64-963:85: static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:969:64-969:85: static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:980:63-980:72: static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:988:63-988:72: static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:996:62-996:71: static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1005:66-1005:75: static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1013:66-1013:75: static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1023:65-1023:74: static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1031:65-1031:74: static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1039:65-1039:74: static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1049:64-1049:84: static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1055:68-1055:87: static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1061:63-1061:88: static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1067:65-1067:86: static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1073:65-1073:86: static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1083:61-1083:92: static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1089:62-1089:71: static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1137:47-1137:69: static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1143:48-1143:71: static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1155:51-1155:60: static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1168:54-1168:63: static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1176:53-1176:62: static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1184:53-1184:62: static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1194:40-1194:49: static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1200:40-1200:49: static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1208:40-1208:49: static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1214:40-1214:49: static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1222:56-1222:65: static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1230:59-1230:68: static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1238:52-1238:61: static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1244:49-1244:58: static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1252:60-1252:69: static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1260:60-1260:69: static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1268:63-1268:72: static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1276:63-1276:72: static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1284:60-1284:69: static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1292:60-1292:69: static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1304:59-1304:68: static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1310:56-1310:65: static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1318:66-1318:75: static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1326:66-1326:75: static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1334:67-1334:76: static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1342:45-1342:54: static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1348:44-1348:53: static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1359:42-1359:51: static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1367:42-1367:51: static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1375:44-1375:53: static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1381:44-1381:53: static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1391:45-1391:54: static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1399:48-1399:57: static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1407:55-1407:64: static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1413:55-1413:64: static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1423:56-1423:65: static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1431:59-1431:68: static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1439:59-1439:68: static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1448:55-1448:64: static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1454:55-1454:64: static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1464:56-1464:65: static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1472:59-1472:68: static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1480:61-1480:70: static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1488:61-1488:70: static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1496:44-1496:53: static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1502:44-1502:53: static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1512:44-1512:53: static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1520:47-1520:56: static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1536:43-1536:52: static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1544:43-1544:52: static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1552:43-1552:52: static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1560:43-1560:52: static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1568:43-1568:52: static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1576:48-1576:57: static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1582:52-1582:61: static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1588:48-1588:57: static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1596:48-1596:57: static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1603:52-1603:61: static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1609:48-1609:57: static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1617:51-1617:60: static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1625:47-1625:56: static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1633:47-1633:56: static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1641:49-1641:71: static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1651:50-1651:59: static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1659:44-1659:53: static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1667:45-1667:54: static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1675:51-1675:60: static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1683:51-1683:60: static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1691:50-1691:72: static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1703:54-1703:63: static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1711:54-1711:63: static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1719:45-1719:54: static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1727:46-1727:55: static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1735:55-1735:64: static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1743:55-1743:64: static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1751:52-1751:61: static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1759:51-1759:60: static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1767:55-1767:64: static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1775:55-1775:64: static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1783:46-1783:55: static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1791:51-1791:73: static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1803:55-1803:64: static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1811:55-1811:64: static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1819:46-1819:55: static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1827:47-1827:56: static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1835:60-1835:69: static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1843:48-1843:57: static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1851:48-1851:57: static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1859:47-1859:56: static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1869:48-1869:57: static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1877:48-1877:57: static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1885:48-1885:57: static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1893:50-1893:71: static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1901:55-1901:64: static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1909:55-1909:64: static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1923:56-1923:65: static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1931:55-1931:64: static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1939:55-1939:64: static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1947:58-1947:67: static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1955:58-1955:67: static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1965:59-1965:68: static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1975:58-1975:67: static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1983:58-1983:67: static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1995:58-1995:67: static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2003:58-2003:67: static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2011:47-2011:67: static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2021:51-2021:60: static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2029:51-2029:60: static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2039:37-2039:54: static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2047:41-2047:50: static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2053:41-2053:50: static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2061:41-2061:50: static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2067:41-2067:50: static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2075:41-2075:50: static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2081:41-2081:50: static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2089:41-2089:50: static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2095:41-2095:50: static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2105:47-2105:56: static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2113:47-2113:56: static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2121:47-2121:56: static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2132:56-2132:65: static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2140:62-2140:71: static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2146:62-2146:71: static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2152:62-2152:71: static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2161:59-2161:68: static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2169:59-2169:68: static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2177:62-2177:71: static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2183:62-2183:71: static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2189:62-2189:71: static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2197:50-2197:67: static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2203:52-2203:69: static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2213:61-2213:77: static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2221:53-2221:62: static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2229:53-2229:62: static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2237:47-2237:56: static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2243:47-2243:56: static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2250:52-2250:61: static inline uint32_t A6XX_CP_REG_TEST_0_PRED_BIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2263:48-2263:57: static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2269:52-2269:61: static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2278:48-2278:66: static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2286:50-2286:59: static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2294:48-2294:57: static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2302:48-2302:57: static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2310:48-2310:57: static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2318:48-2318:57: static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2326:43-2326:52: static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2334:46-2334:55: static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2342:54-2342:63: static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2350:54-2350:63: static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2358:53-2358:62: static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2364:51-2364:69: static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2372:47-2372:64: static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2384:56-2384:65: static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2392:56-2392:65: static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2398:52-2398:61: static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2406:58-2406:67: static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2414:59-2414:68: static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
• drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:2436:51-2436:66: static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val)
• drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c:92:3-92:7: u32 val,
• drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h:290:1-290:1: DECLARE_EVENT_CLASS(dpu_enc_keyval_template,
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:120:43-120:52: static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:126:43-126:52: static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:148:48-148:63: static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:154:47-154:62: static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:160:47-160:62: static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:190:54-190:78: static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:197:54-197:78: static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:204:54-204:78: static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:211:54-211:78: static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:218:54-218:78: static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:225:54-225:78: static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:232:54-232:78: static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:239:54-239:78: static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:250:53-250:77: static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:257:53-257:77: static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:264:53-264:77: static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:271:53-271:77: static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:278:53-278:77: static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:285:53-285:77: static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:292:53-292:77: static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:299:53-299:77: static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:333:46-333:55: static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:339:45-339:54: static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:365:52-365:72: static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:373:52-373:72: static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:468:46-468:59: static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:474:46-474:59: static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:480:46-480:59: static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:487:45-487:54: static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:497:49-497:58: static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:503:48-503:57: static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:515:49-515:58: static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:521:48-521:57: static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:529:51-529:60: static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:535:52-535:61: static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:545:46-545:55: static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:551:46-551:55: static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:560:60-560:84: static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:602:50-602:59: static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:608:49-608:58: static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:616:43-616:52: static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:622:43-622:52: static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:630:50-630:59: static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:636:49-636:58: static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:644:43-644:52: static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:650:43-650:52: static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:666:50-666:59: static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:672:50-672:59: static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:680:50-680:59: static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:686:50-686:59: static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:694:59-694:68: static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:700:58-700:67: static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:708:51-708:64: static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:714:51-714:64: static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:720:51-720:64: static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:726:51-726:70: static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:733:49-733:58: static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:740:58-740:67: static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:748:58-748:67: static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:755:57-755:83: static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:761:58-761:81: static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:769:51-769:60: static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:775:51-775:60: static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:781:51-781:60: static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:787:51-787:60: static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:797:58-797:79: static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:803:58-803:79: static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:855:52-855:61: static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:861:52-861:61: static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:873:54-873:63: static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:879:52-879:61: static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:891:52-891:61: static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:897:50-897:59: static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:912:54-912:63: static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:950:59-950:68: static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:956:59-956:68: static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:962:59-962:68: static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:968:59-968:68: static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:976:59-976:68: static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:982:59-982:68: static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:988:59-988:68: static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1029:51-1029:60: static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1035:51-1035:60: static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1047:53-1047:62: static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1053:51-1053:60: static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1065:51-1065:60: static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1071:49-1071:58: static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1086:53-1086:62: static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1108:51-1108:60: static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1114:51-1114:60: static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1126:53-1126:62: static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1132:51-1132:60: static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1144:51-1144:60: static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1150:49-1150:58: static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h:1165:53-1165:62: static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c:115:61-115:67: static void unref_cursor_worker(struct drm_flip_work *work, void *val)
• drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c:79:34-79:43: struct drm_property *property, uint64_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:191:45-191:54: static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:197:46-197:55: static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:203:46-203:55: static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:218:45-218:54: static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:224:46-224:55: static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:230:46-230:55: static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:238:49-238:69: static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:244:49-244:69: static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:250:49-250:69: static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:256:49-256:69: static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:281:53-281:62: static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:287:53-287:62: static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:293:53-293:62: static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:303:53-303:62: static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:309:53-309:62: static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:315:53-315:62: static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:337:45-337:54: static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:390:48-390:57: static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:396:48-396:57: static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:402:48-402:57: static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:408:48-408:57: static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:414:48-414:57: static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:420:48-420:57: static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:426:48-426:57: static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:432:48-432:57: static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:440:48-440:57: static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:446:48-446:57: static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:454:41-454:60: static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:460:45-460:63: static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:468:44-468:62: static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:535:55-535:79: static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:541:55-541:79: static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:570:62-570:84: static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:576:62-576:84: static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:591:64-591:73: static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:597:64-597:73: static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:605:64-605:73: static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:611:64-611:73: static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:619:64-619:73: static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:625:64-625:73: static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:633:64-633:73: static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:639:64-639:73: static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:647:64-647:73: static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:657:59-657:68: static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:663:58-663:67: static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:673:60-673:69: static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:679:59-679:68: static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:689:59-689:68: static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:699:60-699:69: static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:707:50-707:59: static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:713:49-713:58: static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:721:54-721:63: static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:727:53-727:62: static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:735:43-735:52: static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:741:43-741:52: static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:749:50-749:59: static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:755:49-755:58: static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:763:43-763:52: static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:769:43-769:52: static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:785:50-785:59: static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:791:50-791:59: static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:799:50-799:59: static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:805:50-805:59: static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:815:51-815:64: static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:821:51-821:64: static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:827:51-827:64: static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:833:51-833:70: static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:840:49-840:58: static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:847:58-847:67: static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:855:56-855:76: static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:861:57-861:83: static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:869:51-869:60: static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:875:51-875:60: static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:881:51-881:60: static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:887:51-887:60: static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:896:50-896:69: static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:934:50-934:59: static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:940:50-940:59: static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:959:57-959:66: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:965:57-965:65: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:971:58-971:67: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:977:58-977:66: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:985:56-985:65: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:991:56-991:64: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:997:59-997:68: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1003:59-1003:67: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1011:67-1011:76: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1017:67-1017:76: static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1027:68-1027:91: static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1033:68-1033:91: static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1039:70-1039:93: static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1045:70-1045:93: static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1051:68-1051:91: static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1057:68-1057:91: static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1101:48-1101:57: static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1107:47-1107:56: static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1134:55-1134:75: static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1144:55-1144:75: static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1176:54-1176:63: static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1182:54-1182:63: static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1190:50-1190:59: static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1196:50-1196:59: static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1204:48-1204:57: static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1210:48-1210:57: static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1218:53-1218:62: static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1226:53-1226:77: static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1236:56-1236:65: static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1242:56-1242:65: static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1251:68-1251:91: static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1285:54-1285:63: static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1331:56-1331:65: static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1343:56-1343:65: static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1349:57-1349:66: static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1359:57-1359:66: static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1365:58-1365:67: static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1373:50-1373:59: static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1379:53-1379:62: static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1420:53-1420:62: static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1426:53-1426:62: static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1432:53-1432:62: static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1438:53-1438:62: static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1445:51-1445:60: static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1451:54-1451:63: static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1460:56-1460:65: static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1467:59-1467:68: static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1473:59-1473:68: static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1479:56-1479:65: static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1488:55-1488:64: static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1494:55-1494:64: static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1500:53-1500:62: static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1508:64-1508:73: static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1514:64-1514:73: static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1521:69-1521:78: static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1527:69-1527:78: static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1533:69-1533:78: static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1541:58-1541:67: static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1547:58-1547:67: static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1553:58-1553:67: static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1559:58-1559:67: static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1575:58-1575:67: static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1581:58-1581:67: static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1589:58-1589:67: static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1595:58-1595:67: static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1625:47-1625:56: static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1631:47-1631:56: static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1641:60-1641:69: static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1647:60-1647:69: static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1655:60-1655:69: static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1661:60-1661:69: static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1669:60-1669:69: static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1675:60-1675:69: static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1683:60-1683:69: static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1689:60-1689:69: static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1697:60-1697:69: static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1707:59-1707:68: static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1713:58-1713:67: static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1723:60-1723:69: static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1729:59-1729:68: static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1739:59-1739:68: static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1749:60-1749:69: static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1774:51-1774:60: static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1780:51-1780:60: static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1804:55-1804:64: static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1813:55-1813:64: static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1825:53-1825:62: static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1831:51-1831:60: static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1839:52-1839:61: static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h:1845:50-1845:59: static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
• drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c:164:61-164:67: static void unref_cursor_worker(struct drm_flip_work *work, void *val)
• drivers/gpu/drm/msm/dp/dp_link.c:311:25-311:30: int addr, int len, u32 *val)
• drivers/gpu/drm/msm/dp/dp_link.c:355:16-355:21: int addr, u32 *val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:146:48-146:57: static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:152:48-152:57: static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:158:47-158:56: static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:213:50-213:59: static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:219:48-219:72: static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:225:50-225:72: static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:242:46-242:64: static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:250:43-250:52: static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:256:41-256:50: static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:264:43-264:52: static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:270:41-270:50: static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:278:42-278:51: static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:284:42-284:51: static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:292:47-292:56: static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:298:45-298:54: static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:306:52-306:61: static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:312:50-312:59: static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:320:52-320:61: static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:326:50-326:59: static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:339:48-339:72: static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:348:52-348:61: static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:354:46-354:64: static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:362:50-362:59: static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:368:53-368:62: static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:381:59-381:68: static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:387:65-387:74: static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:393:60-393:69: static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:401:58-401:67: static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:407:58-407:67: static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:415:59-415:68: static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:421:65-421:74: static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:427:60-427:69: static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:435:58-435:67: static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:441:58-441:67: static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:455:50-455:71: static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:461:50-461:71: static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:467:45-467:54: static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:486:51-486:60: static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:492:49-492:58: static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:500:51-500:60: static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:506:59-506:68: static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:517:57-517:66: static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:523:58-523:67: static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:552:56-552:75: static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:601:49-601:71: static inline uint32_t DSI_TPG_VIDEO_CONFIG_BPP(enum video_config_bpp val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:610:70-610:95: static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL(enum cmd_dma_pattern_sel val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:616:78-616:111: static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(enum cmd_mdp_stream0_pattern_sel val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:622:68-622:91: static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(enum video_pattern_sel val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:646:59-646:83: static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:656:56-656:74: static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:662:62-662:80: static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:671:64-671:73: static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:677:70-677:79: static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:683:65-683:74: static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:691:49-691:58: static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:700:42-700:51: static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:710:59-710:68: static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:716:65-716:74: static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:722:69-722:78: static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:728:69-728:78: static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:737:75-737:84: static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:743:79-743:88: static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:749:79-749:88: static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:756:75-756:84: static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:762:79-762:88: static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:768:79-768:88: static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:777:79-777:88: static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi.xml.h:783:79-783:88: static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:67:63-67:72: static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:73:63-73:72: static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:112:61-112:70: static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:122:57-122:66: static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:141:62-141:71: static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:149:62-149:71: static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:157:65-157:74: static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:165:63-165:72: static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:173:62-173:71: static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:181:60-181:69: static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:187:62-187:71: static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:195:62-195:71: static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h:203:65-203:74: static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:97:60-97:69: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:105:61-105:70: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:113:63-113:72: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:124:59-124:68: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:132:59-132:68: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:140:62-140:71: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:148:60-148:69: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:156:59-156:68: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:164:57-164:66: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:170:59-170:68: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:178:59-178:68: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h:186:62-186:71: static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:97:60-97:69: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:105:61-105:70: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:113:63-113:72: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:124:59-124:68: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:132:59-132:68: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:140:62-140:71: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:148:60-148:69: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:156:59-156:68: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:164:57-164:66: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:170:59-170:68: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:178:59-178:68: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:186:62-186:71: static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:273:58-273:67: static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:282:60-282:69: static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:288:60-288:69: static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:296:64-296:73: static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h:304:65-304:74: static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:85:65-85:74: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:93:66-93:75: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:101:68-101:77: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:111:64-111:73: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:119:64-119:73: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:127:67-127:76: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:135:65-135:74: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:143:64-143:73: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:151:62-151:71: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:157:64-157:73: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:165:64-165:73: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
• drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h:173:67-173:76: static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
• drivers/gpu/drm/msm/dsi/sfpb.xml.h:64:50-64:83: static inline uint32_t SFPB_GPREG_MASTER_PORT_EN(enum sfpb_ahb_arb_master_port_en val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:92:49-92:67: static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:99:55-99:64: static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:124:59-124:68: static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:130:61-130:70: static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:136:60-136:69: static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:142:63-142:72: static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:152:58-152:67: static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:160:56-160:65: static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:166:56-166:65: static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:193:39-193:48: static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:201:37-201:46: static inline uint32_t HDMI_ACR_1_N(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:209:50-209:59: static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:215:44-215:53: static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:223:44-223:53: static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:229:45-229:54: static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:264:57-264:82: static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:337:54-337:63: static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:351:54-351:63: static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:376:49-376:58: static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:382:48-382:57: static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:390:47-390:56: static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:400:52-400:77: static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:409:53-409:62: static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:417:46-417:71: static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:423:43-423:52: static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:429:44-429:53: static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:459:46-459:55: static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:469:46-469:55: static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:501:48-501:57: static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:507:46-507:55: static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:515:48-515:57: static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:521:46-521:55: static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:529:51-529:60: static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:535:49-535:58: static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:543:43-543:52: static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:549:43-549:52: static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:557:52-557:61: static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:599:58-599:67: static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:607:57-607:66: static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
• drivers/gpu/drm/msm/hdmi/hdmi.xml.h:613:61-613:70: static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
• drivers/gpu/drm/msm/msm_debugfs.c:190:24-190:29: shrink_get(void *data, u64 *val)
• drivers/gpu/drm/msm/msm_debugfs.c:198:24-198:28: shrink_set(void *data, u64 val)
• drivers/gpu/drm/msm/msm_gpu.h:595:62-595:66: static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)
• drivers/gpu/drm/mxsfb/mxsfb_kms.c:41:67-41:71: static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
• drivers/gpu/drm/nouveau/dispnv04/hw.h:71:30-71:39: int head, uint32_t reg, uint32_t val)
• drivers/gpu/drm/nouveau/dispnv04/hw.h:91:30-91:39: int head, uint32_t reg, uint32_t val)
• drivers/gpu/drm/nouveau/dispnv04/tvnv17.c:687:5-687:14: uint64_t val)
• drivers/gpu/drm/nouveau/dispnv04/tvnv17.h:131:5-131:14: uint32_t val)
• drivers/gpu/drm/nouveau/dispnv04/tvnv17.h:144:8-144:16: uint8_t val)
• drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h:121:66-121:70: nvkm_falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val)
• drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h:122:56-122:59: nvkm_wri2cr(struct i2c_adapter *adap, u8 addr, u8 reg, u8 val)
• drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h:137:56-137:60: nv_wr16i2cr(struct i2c_adapter *adap, u8 addr, u8 reg, u16 val)
• drivers/gpu/drm/nouveau/nouveau_bo.c:709:58-709:62: nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
• drivers/gpu/drm/nouveau/nouveau_bo.c:737:58-737:62: nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
• drivers/gpu/drm/nouveau/nouveau_connector.c:99:37-99:42: struct drm_property *property, u64 *val)
• drivers/gpu/drm/nouveau/nouveau_connector.c:130:37-130:41: struct drm_property *property, u64 val)
• drivers/gpu/drm/nouveau/nouveau_display.c:545:54-545:68: nouveau_display_acpi_ntfy(struct notifier_block *nb, unsigned long val,
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:352:62-352:68: nouveau_chip_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:366:62-366:68: nouveau_temp_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:415:61-415:67: nouveau_fan_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:438:60-438:66: nouveau_in_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:469:61-469:67: nouveau_pwm_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:495:63-495:69: nouveau_power_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:524:63-524:68: nouveau_temp_write(struct device *dev, u32 attr, int channel, long val)
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:558:62-558:67: nouveau_pwm_write(struct device *dev, u32 attr, int channel, long val)
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:615:21-615:27: int channel, long *val)
• drivers/gpu/drm/nouveau/nouveau_hwmon.c:637:21-637:26: int channel, long val)
• drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c:31:43-31:57: nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data)
• drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h:37:32-37:36: cp_lsr(struct nvkm_grctx *ctx, u32 val)
• drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h:121:41-121:45: gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val)
• drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c:785:42-785:46: dd_emit(struct nvkm_grctx *ctx, int num, u32 val) {
• drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c:1158:42-1158:46: xf_emit(struct nvkm_grctx *ctx, int num, u32 val) {
• drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c:192:46-192:50: init_wr32(struct nvbios_init *init, u32 reg, u32 val)
• drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c:201:56-201:60: init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
• drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c:294:66-294:69: init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
• drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h:70:44-70:48: fbmem_poke(struct io_mapping *fb, u32 off, u32 val)
• drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h:79:48-79:52: fbmem_readback(struct io_mapping *fb, u32 off, u32 val)
• drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c:466:50-466:54: gt215_ram_gpio(struct gt215_ramfuc *fuc, u8 tag, u32 val)
• drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c:191:49-191:53: nv50_ram_gpio(struct nv50_ramseq *hwsq, u8 tag, u32 val)
• drivers/gpu/drm/panel/panel-ilitek-ili9322.c:306:25-306:31: size_t reg_size, void *val, size_t val_size)
• drivers/gpu/drm/panel/panel-lg-lb035q02.c:32:65-32:69: static int lb035q02_write(struct lb035q02_device *lcd, u16 reg, u16 val)
• drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c:225:19-225:22: u8 reg, u8 val)
• drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c:234:71-234:75: static int rpi_touchscreen_write(struct rpi_touchscreen *ts, u16 reg, u32 val)
• drivers/gpu/drm/panel/panel-sitronix-st7703.c:574:40-574:44: static int allpixelson_set(void *data, u64 val)
• drivers/gpu/drm/qxl/qxl_cmd.c:280:58-280:66: static int wait_for_io_cmd_user(struct qxl_device *qdev, uint8_t val, long port, bool intr)
• drivers/gpu/drm/qxl/qxl_cmd.c:315:54-315:62: static void wait_for_io_cmd(struct qxl_device *qdev, uint8_t val, long port)
• drivers/gpu/drm/radeon/atom.c:448:15-448:24: int *ptr, uint32_t val, uint32_t saved)
• drivers/gpu/drm/radeon/cik.c:154:16-154:21: u32 reg, u32 *val)
• drivers/gpu/drm/radeon/evergreen.c:1093:15-1093:20: u32 reg, u32 *val)
• drivers/gpu/drm/radeon/ni.c:849:19-849:24: u32 reg, u32 *val)
• drivers/gpu/drm/radeon/r600.c:175:17-175:22: u32 reg, u32 *val)
• drivers/gpu/drm/radeon/r600.c:1984:26-1984:35: int r600_count_pipe_bits(uint32_t val)
• drivers/gpu/drm/radeon/radeon_acpi.c:678:9-678:23: unsigned long val,
• drivers/gpu/drm/radeon/radeon_asic.c:140:20-140:25: u32 reg, u32 *val)
• drivers/gpu/drm/radeon/radeon_connectors.c:528:7-528:16: uint64_t val)
• drivers/gpu/drm/radeon/radeon_device.c:855:66-855:75: static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
• drivers/gpu/drm/radeon/radeon_device.c:889:65-889:74: static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
• drivers/gpu/drm/radeon/radeon_device.c:905:66-905:75: static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
• drivers/gpu/drm/radeon/radeon_device.c:939:68-939:77: static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
• drivers/gpu/drm/radeon/radeon_fence.c:987:49-987:54: static int radeon_debugfs_gpu_reset(void *data, u64 *val)
• drivers/gpu/drm/radeon/radeon_i2c.c:1044:5-1044:9: u8 *val)
• drivers/gpu/drm/radeon/radeon_i2c.c:1078:5-1078:8: u8 val)
• drivers/gpu/drm/radeon/si.c:1308:15-1308:20: u32 reg, u32 *val)
• drivers/gpu/drm/rockchip/cdn-dp-core.c:70:26-70:39: unsigned int reg, unsigned int val)
• drivers/gpu/drm/rockchip/cdn-dp-reg.c:91:59-91:62: static int cdp_dp_mailbox_write(struct cdn_dp_device *dp, u8 val)
• drivers/gpu/drm/rockchip/cdn-dp-reg.c:184:65-184:69: static int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val)
• drivers/gpu/drm/rockchip/cdn-dp-reg.c:199:31-199:35: u8 start_bit, u8 bits_no, u32 val)
• drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c:359:73-359:77: static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
• drivers/gpu/drm/rockchip/inno_hdmi.c:164:68-164:72: static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
• drivers/gpu/drm/rockchip/inno_hdmi.c:170:18-170:22: u32 msk, u32 val)
• drivers/gpu/drm/rockchip/rk3066_hdmi.c:78:70-78:74: static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val)
• drivers/gpu/drm/rockchip/rk3066_hdmi.c:84:18-84:22: u32 msk, u32 val)
• drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1723:61-1723:67: static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
• drivers/gpu/drm/rockchip/rockchip_lvds.c:79:6-79:10: u32 val)
• drivers/gpu/drm/solomon/ssd130x-spi.c:49:8-49:14: void *val, size_t val_size)
• drivers/gpu/drm/sprd/megacores_pll.c:127:66-127:73: static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[])
• drivers/gpu/drm/sprd/sprd_dsi.c:144:16-144:20: u32 shift, u32 val)
• drivers/gpu/drm/sprd/sprd_dsi.c:156:5-156:9: u32 val)
• drivers/gpu/drm/sprd/sprd_dsi.c:163:56-163:60: static int regmap_tst_io_write(void *context, u32 reg, u32 val)
• drivers/gpu/drm/sprd/sprd_dsi.c:185:55-185:60: static int regmap_tst_io_read(void *context, u32 reg, u32 *val)
• drivers/gpu/drm/sun4i/sun4i_frontend.c:248:12-248:17: u32 *val)
• drivers/gpu/drm/sun4i/sun4i_frontend.c:268:25-268:30: uint64_t modifier, u32 *val)
• drivers/gpu/drm/sun4i/sun4i_frontend.c:294:10-294:15: u32 *val)
• drivers/gpu/drm/sun4i/sun4i_frontend.c:348:66-348:71: static int sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt, u32 *val)
• drivers/gpu/drm/tidss/tidss_dispc.c:360:62-360:66: static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val)
• drivers/gpu/drm/tidss/tidss_dispc.c:371:73-371:77: void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)
• drivers/gpu/drm/tidss/tidss_dispc.c:386:17-386:21: u16 reg, u32 val)
• drivers/gpu/drm/tidss/tidss_dispc.c:401:16-401:20: u16 reg, u32 val)
• drivers/gpu/drm/tidss/tidss_dispc.c:425:20-425:24: static u32 FLD_VAL(u32 val, u32 start, u32 end)
• drivers/gpu/drm/tidss/tidss_dispc.c:430:20-430:24: static u32 FLD_GET(u32 val, u32 start, u32 end)
• drivers/gpu/drm/tidss/tidss_dispc.c:435:30-435:34: static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end)
• drivers/gpu/drm/tidss/tidss_dispc.c:445:62-445:66: static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val,
• drivers/gpu/drm/tidss/tidss_dispc.c:459:8-459:12: u32 val, u32 start, u32 end)
• drivers/gpu/drm/tidss/tidss_dispc.c:472:73-472:77: static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val,
• drivers/gpu/drm/tidss/tidss_dispc.c:487:8-487:12: u32 val, u32 start, u32 end)
• drivers/gpu/drm/tiny/bochs.c:98:70-98:73: static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
• drivers/gpu/drm/tiny/bochs.c:141:68-141:72: static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
• drivers/gpu/drm/tiny/cirrus.c:106:60-106:63: static void wreg_seq(struct cirrus_device *cirrus, u8 reg, u8 val)
• drivers/gpu/drm/tiny/cirrus.c:121:60-121:63: static void wreg_crt(struct cirrus_device *cirrus, u8 reg, u8 val)
• drivers/gpu/drm/tiny/cirrus.c:130:60-130:63: static void wreg_gfx(struct cirrus_device *cirrus, u8 reg, u8 val)
• drivers/gpu/drm/tiny/cirrus.c:138:52-138:55: static void wreg_hdr(struct cirrus_device *cirrus, u8 val)
• drivers/gpu/drm/tiny/repaper.c:163:62-163:65: static int repaper_write_val(struct spi_device *spi, u8 reg, u8 val)
• drivers/gpu/drm/udl/udl_modeset.c:36:50-36:53: static char *udl_set_register(char *buf, u8 reg, u8 val)
• drivers/gpu/drm/vc4/vc4_dsi.c:614:59-614:63: dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
• drivers/gpu/drm/vc4/vc4_hdmi.c:592:9-592:19: uint64_t *val)
• drivers/gpu/drm/vc4/vc4_hdmi.c:614:9-614:18: uint64_t val)
• drivers/gpu/drm/vc4/vc4_plane.c:348:64-348:68: static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
• drivers/gpu/drm/vc4/vc4_render_cl.c:56:56-56:59: static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val)
• drivers/gpu/drm/vc4/vc4_render_cl.c:62:57-62:61: static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val)
• drivers/gpu/drm/vc4/vc4_render_cl.c:68:57-68:61: static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val)
• drivers/gpu/drm/vc4/vc4_vec.c:372:11-372:20: uint64_t val)
• drivers/gpu/drm/vc4/vc4_vec.c:420:11-420:21: uint64_t *val)
• drivers/gpu/drm/vmwgfx/vmwgfx_drv.c:1455:58-1455:72: static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
• drivers/gpu/drm/vmwgfx/vmwgfx_mob.c:434:44-434:55: static void vmw_mob_assign_ppn(u32 **addr, dma_addr_t val)
• drivers/gpu/drm/vmwgfx/vmwgfx_validation.h:156:49-156:62: static inline unsigned int vmw_validation_align(unsigned int val)
• drivers/gpu/drm/xlnx/zynqmp_disp.c:362:72-362:76: static void zynqmp_disp_avbuf_write(struct zynqmp_disp *disp, int reg, u32 val)
• drivers/gpu/drm/xlnx/zynqmp_disp.c:588:72-588:76: static void zynqmp_disp_blend_write(struct zynqmp_disp *disp, int reg, u32 val)
• drivers/gpu/drm/xlnx/zynqmp_disp.c:814:72-814:76: static void zynqmp_disp_audio_write(struct zynqmp_disp *disp, int reg, u32 val)
• drivers/gpu/drm/xlnx/zynqmp_dp.c:326:63-326:67: static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val)
• drivers/gpu/host1x/hw/debug_hw.c:41:60-41:64: static unsigned int show_channel_command(struct output *o, u32 val,
• drivers/greybus/interface.c:49:20-49:25: u16 attr, u32 *val)
• drivers/hid/hid-asus.c:704:5-704:33: union power_supply_propval *val)
• drivers/hid/hid-cougar.c:303:41-303:53: static int cougar_param_set_g6_is_space(const char *val,
• drivers/hid/hid-elan.c:109:38-109:43: static unsigned int elan_convert_res(char val)
• drivers/hid/hid-input.c:463:7-463:35: union power_supply_propval *val)
• drivers/hid/hid-logitech-hidpp.c:1785:11-1785:39: union power_supply_propval *val)
• drivers/hid/hid-magicmouse.c:35:35-35:47: static int param_set_scroll_speed(const char *val,
• drivers/hid/hid-mcp2221.c:625:26-625:29: unsigned int offset, u8 val)
• drivers/hid/hid-mcp2221.c:932:45-932:50: struct iio_chan_spec const *channel, int *val,
• drivers/hid/hid-mcp2221.c:973:9-973:13: int val, int val2, long mask)
• drivers/hid/hid-nintendo.c:1019:63-1019:67: static s32 joycon_map_stick_val(struct joycon_stick_cal *cal, s32 val)
• drivers/hid/hid-nintendo.c:1999:12-1999:40: union power_supply_propval *val)
• drivers/hid/hid-nvidia-shield.c:456:12-456:40: union power_supply_propval *val)
• drivers/hid/hid-playstation.c:626:3-626:31: union power_supply_propval *val)
• drivers/hid/hid-sony.c:1624:10-1624:38: union power_supply_propval *val)
• drivers/hid/hid-steam.c:406:5-406:33: union power_supply_propval *val)
• drivers/hid/hid-steam.c:1430:40-1430:52: static int steam_param_set_lizard_mode(const char *val,
• drivers/hid/hid-steelseries.c:425:5-425:33: union power_supply_propval *val)
• drivers/hid/hid-wiimote-modules.c:201:12-201:40: union power_supply_propval *val)
• drivers/hid/wacom_sys.c:1716:11-1716:39: union power_supply_propval *val)
• drivers/hv/hv_balloon.c:646:58-646:72: static int hv_memory_notifier(struct notifier_block *nb, unsigned long val,
• drivers/hv/hv_common.c:175:10-175:24: unsigned long val, void *args)
• drivers/hv/hv_debugfs.c:16:45-16:50: static int hv_debugfs_delay_get(void *data, u64 *val)
• drivers/hv/hv_debugfs.c:22:45-22:49: static int hv_debugfs_delay_set(void *data, u64 val)
• drivers/hv/hv_debugfs.c:33:45-33:50: static int hv_debugfs_state_get(void *data, u64 *val)
• drivers/hv/hv_debugfs.c:39:45-39:49: static int hv_debugfs_state_set(void *data, u64 val)
• drivers/hv/vmbus_drv.c:67:61-67:75: static int hv_panic_vmbus_unload(struct notifier_block *nb, unsigned long val,
• drivers/hwmon/adm1031.c:242:33-242:37: static int AUTO_TEMP_MAX_TO_REG(int val, int reg, int pwm)
• drivers/hwmon/adm1031.c:285:59-285:62: get_fan_auto_nearest(struct adm1031_data *data, int chan, u8 val, u8 reg)
• drivers/hwmon/adm1177.c:72:27-72:33: u32 attr, int channel, long *val)
• drivers/hwmon/adm1177.c:122:28-122:33: u32 attr, int channel, long val)
• drivers/hwmon/adm9240.c:71:25-71:30: static inline int SCALE(long val, int mul, int div)
• drivers/hwmon/adm9240.c:87:28-87:42: static inline u8 IN_TO_REG(unsigned long val, int n)
• drivers/hwmon/adm9240.c:94:30-94:35: static inline s8 TEMP_TO_REG(long val)
• drivers/hwmon/adm9240.c:113:30-113:44: static inline u8 AOUT_TO_REG(unsigned long val)
• drivers/hwmon/adm9240.c:167:74-167:79: static int adm9240_fan_min_write(struct adm9240_data *data, int channel, long val)
• drivers/hwmon/adm9240.c:381:60-381:66: static int adm9240_chip_read(struct device *dev, u32 attr, long *val)
• drivers/hwmon/adm9240.c:400:65-400:71: static int adm9240_intrusion_read(struct device *dev, u32 attr, long *val)
• drivers/hwmon/adm9240.c:419:66-419:71: static int adm9240_intrusion_write(struct device *dev, u32 attr, long val)
• drivers/hwmon/adm9240.c:439:71-439:77: static int adm9240_in_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/adm9240.c:478:72-478:77: static int adm9240_in_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/adm9240.c:496:72-496:78: static int adm9240_fan_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/adm9240.c:543:73-543:78: static int adm9240_fan_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/adm9240.c:560:73-560:79: static int adm9240_temp_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/adm9240.c:602:74-602:79: static int adm9240_temp_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/adm9240.c:621:17-621:23: int channel, long *val)
• drivers/hwmon/adm9240.c:640:18-640:23: int channel, long val)
• drivers/hwmon/ads7871.c:85:64-85:67: static int ads7871_write_reg8(struct spi_device *spi, int reg, u8 val)
• drivers/hwmon/adt7310.c:83:62-83:76: static int adt7310_reg_read(void *context, unsigned int reg, unsigned int *val)
• drivers/hwmon/adt7310.c:105:63-105:76: static int adt7310_reg_write(void *context, unsigned int reg, unsigned int val)
• drivers/hwmon/adt7410.c:27:62-27:76: static int adt7410_reg_read(void *context, unsigned int reg, unsigned int *val)
• drivers/hwmon/adt7410.c:49:63-49:76: static int adt7410_reg_write(void *context, unsigned int reg, unsigned int val)
• drivers/hwmon/adt7411.c:215:67-215:73: static int adt7411_read_in_alarm(struct device *dev, int channel, long *val)
• drivers/hwmon/adt7411.c:228:62-228:68: static int adt7411_read_in_vdd(struct device *dev, u32 attr, long *val)
• drivers/hwmon/adt7411.c:288:5-288:11: long *val)
• drivers/hwmon/adt7411.c:338:7-338:13: long *val)
• drivers/hwmon/adt7411.c:348:8-348:14: long *val)
• drivers/hwmon/adt7411.c:379:9-379:15: long *val)
• drivers/hwmon/adt7411.c:418:27-418:33: u32 attr, int channel, long *val)
• drivers/hwmon/adt7411.c:430:63-430:68: static int adt7411_write_in_vdd(struct device *dev, u32 attr, long val)
• drivers/hwmon/adt7411.c:454:6-454:11: long val)
• drivers/hwmon/adt7411.c:486:8-486:13: long val)
• drivers/hwmon/adt7411.c:495:10-495:15: long val)
• drivers/hwmon/adt7411.c:519:28-519:33: u32 attr, int channel, long val)
• drivers/hwmon/adt7470.c:180:7-180:21: unsigned int *val)
• drivers/hwmon/adt7470.c:195:8-195:21: unsigned int val)
• drivers/hwmon/adt7470.c:536:73-536:79: static int adt7470_temp_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/adt7470.c:563:74-563:79: static int adt7470_temp_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/adt7470.c:624:72-624:78: static int adt7470_fan_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/adt7470.c:660:73-660:78: static int adt7470_fan_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/adt7470.c:757:72-757:78: static int adt7470_pwm_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/adt7470.c:814:73-814:78: static int adt7470_pwm_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/adt7470.c:1098:17-1098:23: int channel, long *val)
• drivers/hwmon/adt7470.c:1113:18-1113:23: int channel, long val)
• drivers/hwmon/adt7475.c:228:55-228:60: static inline u16 temp2reg(struct adt7475_data *data, long val)
• drivers/hwmon/adt7475.c:321:68-321:72: static void adt7475_write_word(struct i2c_client *client, int reg, u16 val)
• drivers/hwmon/adt7x10.c:135:68-135:74: static int adt7x10_temp_read(struct adt7x10_data *data, int index, long *val)
• drivers/hwmon/adt7x10.c:171:68-171:74: static int adt7x10_hyst_read(struct adt7x10_data *data, int index, long *val)
• drivers/hwmon/adt7x10.c:224:69-224:75: static int adt7x10_alarm_read(struct adt7x10_data *data, int index, long *val)
• drivers/hwmon/adt7x10.c:263:27-263:33: u32 attr, int channel, long *val)
• drivers/hwmon/adt7x10.c:294:28-294:33: u32 attr, int channel, long val)
• drivers/hwmon/aht10.c:223:9-223:14: long val)
• drivers/hwmon/aht10.c:234:8-234:14: long *val)
• drivers/hwmon/aht10.c:243:61-243:67: static int aht10_temperature1_read(struct aht10_data *data, long *val)
• drivers/hwmon/aht10.c:258:58-258:64: static int aht10_humidity1_read(struct aht10_data *data, long *val)
• drivers/hwmon/aht10.c:285:31-285:37: u32 attr, int channel, long *val)
• drivers/hwmon/aht10.c:302:32-302:37: u32 attr, int channel, long val)
• drivers/hwmon/applesmc.c:165:24-165:27: static int wait_status(u8 val, u8 mask)
• drivers/hwmon/aquacomputer_d5next.c:591:31-591:35: static int aqc_percent_to_pwm(u16 val)
• drivers/hwmon/aquacomputer_d5next.c:597:31-597:36: static int aqc_pwm_to_percent(long val)
• drivers/hwmon/aquacomputer_d5next.c:606:46-606:50: static int aqc_aquastreamxt_convert_pump_rpm(u16 val)
• drivers/hwmon/aquacomputer_d5next.c:614:45-614:49: static int aqc_aquastreamxt_convert_fan_rpm(u16 val)
• drivers/hwmon/aquacomputer_d5next.c:690:64-690:70: static int aqc_get_ctrl_val(struct aqc_data *priv, int offset, long *val, int type)
• drivers/hwmon/aquacomputer_d5next.c:749:64-749:69: static int aqc_set_ctrl_val(struct aqc_data *priv, int offset, long val, int type)
• drivers/hwmon/aquacomputer_d5next.c:977:20-977:26: int channel, long *val)
• drivers/hwmon/aquacomputer_d5next.c:1118:8-1118:13: long val)
• drivers/hwmon/asb100.c:102:21-102:30: static u8 IN_TO_REG(unsigned val)
• drivers/hwmon/asb100.c:123:25-123:28: static int FAN_FROM_REG(u8 val, int div)
• drivers/hwmon/asb100.c:169:22-169:27: static u8 DIV_TO_REG(long val)
• drivers/hwmon/aspeed-pwm-tacho.c:346:11-346:24: unsigned int val)
• drivers/hwmon/aspeed-pwm-tacho.c:355:10-355:24: unsigned int *val)
• drivers/hwmon/aspeed-pwm-tacho.c:373:60-373:65: static void aspeed_set_clock_enable(struct regmap *regmap, bool val)
• drivers/hwmon/aspeed-pwm-tacho.c:380:60-380:64: static void aspeed_set_clock_source(struct regmap *regmap, int val)
• drivers/hwmon/asus-ec-sensors.c:864:33-864:39: u32 attr, int channel, long *val)
• drivers/hwmon/asus_atk0110.c:657:42-657:47: static int atk_debugfs_gitm_get(void *p, u64 *val)
• drivers/hwmon/asus_wmi_sensors.c:447:34-447:40: u32 attr, int channel, long *val)
• drivers/hwmon/axi-fan-control.c:62:32-62:42: static inline void axi_iowrite(const u32 val, const u32 reg,
• drivers/hwmon/axi-fan-control.c:118:41-118:52: static int axi_fan_control_set_pwm_duty(const long val,
• drivers/hwmon/axi-fan-control.c:150:68-150:74: static int axi_fan_control_read_temp(struct device *dev, u32 attr, long *val)
• drivers/hwmon/axi-fan-control.c:171:67-171:73: static int axi_fan_control_read_fan(struct device *dev, u32 attr, long *val)
• drivers/hwmon/axi-fan-control.c:189:67-189:73: static int axi_fan_control_read_pwm(struct device *dev, u32 attr, long *val)
• drivers/hwmon/axi-fan-control.c:202:68-202:73: static int axi_fan_control_write_pwm(struct device *dev, u32 attr, long val)
• drivers/hwmon/axi-fan-control.c:232:28-232:34: u32 attr, int channel, long *val)
• drivers/hwmon/axi-fan-control.c:248:29-248:34: u32 attr, int channel, long val)
• drivers/hwmon/bt1-pvt.c:291:5-291:11: long *val)
• drivers/hwmon/bt1-pvt.c:311:19-311:25: bool is_low, long *val)
• drivers/hwmon/bt1-pvt.c:332:20-332:25: bool is_low, long val)
• drivers/hwmon/bt1-pvt.c:372:19-372:25: bool is_low, long *val)
• drivers/hwmon/bt1-pvt.c:612:49-612:55: static int pvt_read_trim(struct pvt_hwmon *pvt, long *val)
• drivers/hwmon/bt1-pvt.c:622:50-622:55: static int pvt_write_trim(struct pvt_hwmon *pvt, long val)
• drivers/hwmon/bt1-pvt.c:643:52-643:58: static int pvt_read_timeout(struct pvt_hwmon *pvt, long *val)
• drivers/hwmon/bt1-pvt.c:659:53-659:58: static int pvt_write_timeout(struct pvt_hwmon *pvt, long val)
• drivers/hwmon/bt1-pvt.c:712:24-712:30: u32 attr, int ch, long *val)
• drivers/hwmon/bt1-pvt.c:796:25-796:30: u32 attr, int ch, long val)
• drivers/hwmon/corsair-cpro.c:167:57-167:62: static int set_pwm(struct ccp_device *ccp, int channel, long val)
• drivers/hwmon/corsair-cpro.c:187:60-187:65: static int set_target(struct ccp_device *ccp, int channel, long val)
• drivers/hwmon/corsair-cpro.c:224:30-224:36: u32 attr, int channel, long *val)
• drivers/hwmon/corsair-cpro.c:293:31-293:36: u32 attr, int channel, long val)
• drivers/hwmon/corsair-psu.c:143:39-143:49: static int corsairpsu_linear11_to_int(const u16 val, const int scale)
• drivers/hwmon/corsair-psu.c:246:80-246:86: static int corsairpsu_get_value(struct corsairpsu_data *priv, u8 cmd, u8 rail, long *val)
• drivers/hwmon/corsair-psu.c:475:11-475:17: long *val)
• drivers/hwmon/corsair-psu.c:494:91-494:97: static int corsairpsu_hwmon_pwm_read(struct corsairpsu_data *priv, u32 attr, int channel, long *val)
• drivers/hwmon/corsair-psu.c:509:12-509:18: long *val)
• drivers/hwmon/corsair-psu.c:525:90-525:96: static int corsairpsu_hwmon_in_read(struct corsairpsu_data *priv, u32 attr, int channel, long *val)
• drivers/hwmon/corsair-psu.c:554:11-554:17: long *val)
• drivers/hwmon/corsair-psu.c:581:23-581:29: int channel, long *val)
• drivers/hwmon/dell-smm-hwmon.c:740:5-740:11: long *val)
• drivers/hwmon/dell-smm-hwmon.c:866:6-866:11: long val)
• drivers/hwmon/dme1737.c:267:29-267:34: static inline int IN_TO_REG(long val, int nominal)
• drivers/hwmon/dme1737.c:284:31-284:36: static inline int TEMP_TO_REG(long val)
• drivers/hwmon/dme1737.c:300:30-300:35: static int TEMP_RANGE_TO_REG(long val, int reg)
• drivers/hwmon/dme1737.c:340:30-340:35: static inline int FAN_TO_REG(long val, int tpc)
• drivers/hwmon/dme1737.c:372:35-372:40: static inline int FAN_TYPE_TO_REG(long val, int reg)
• drivers/hwmon/dme1737.c:395:27-395:32: static int FAN_MAX_TO_REG(long val)
• drivers/hwmon/dme1737.c:426:33-426:37: static inline int PWM_EN_TO_REG(int val, int reg)
• drivers/hwmon/dme1737.c:453:34-453:39: static inline int PWM_ACZ_TO_REG(long val, int reg)
• drivers/hwmon/dme1737.c:469:28-469:33: static int PWM_FREQ_TO_REG(long val, int reg)
• drivers/hwmon/dme1737.c:503:26-503:31: static int PWM_RR_TO_REG(long val, int ix, int reg)
• drivers/hwmon/dme1737.c:521:36-521:41: static inline int PWM_RR_EN_TO_REG(long val, int ix, int reg)
• drivers/hwmon/dme1737.c:538:34-538:38: static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
• drivers/hwmon/dme1737.c:573:67-573:70: static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
• drivers/hwmon/dme1737.c:2031:59-2031:63: static inline void dme1737_sio_outb(int sio_cip, int reg, int val)
• drivers/hwmon/drivetemp.c:256:71-256:77: static int drivetemp_get_scttemp(struct drivetemp_data *st, u32 attr, long *val)
• drivers/hwmon/drivetemp.c:449:28-449:34: u32 attr, int channel, long *val)
• drivers/hwmon/emc2305.c:272:48-272:53: static int emc2305_set_pwm(struct device *dev, long val, int channel)
• drivers/hwmon/emc2305.c:393:88-393:93: emc2305_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long val)
• drivers/hwmon/emc2305.c:434:87-434:93: emc2305_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val)
• drivers/hwmon/emc6w201.c:80:64-80:68: static int emc6w201_write16(struct i2c_client *client, u8 reg, u16 val)
• drivers/hwmon/emc6w201.c:110:63-110:66: static int emc6w201_write8(struct i2c_client *client, u8 reg, u8 val)
• drivers/hwmon/f71805f.c:202:28-202:33: static inline u8 in_to_reg(long val)
• drivers/hwmon/f71805f.c:217:29-217:34: static inline u8 in0_to_reg(long val)
• drivers/hwmon/f71805f.c:257:34-257:48: static inline u8 pwm_freq_to_reg(unsigned long val)
• drivers/hwmon/f71805f.c:279:30-279:35: static inline u8 temp_to_reg(long val)
• drivers/hwmon/f71805f.c:300:63-300:66: static void f71805f_write8(struct f71805f_data *data, u8 reg, u8 val)
• drivers/hwmon/f71805f.c:324:64-324:68: static void f71805f_write16(struct f71805f_data *data, u8 reg, u16 val)
• drivers/hwmon/f71882fg.c:318:65-318:68: static void f71882fg_write8(struct f71882fg_data *data, u8 reg, u8 val)
• drivers/hwmon/f71882fg.c:324:66-324:70: static void f71882fg_write16(struct f71882fg_data *data, u8 reg, u16 val)
• drivers/hwmon/f75375s.c:361:69-361:73: static int set_pwm_enable_direct(struct i2c_client *client, int nr, int val)
• drivers/hwmon/ftsteutates.c:378:7-378:13: long *val)
• drivers/hwmon/ftsteutates.c:455:8-455:13: long val)
• drivers/hwmon/g760a.c:61:41-61:44: static inline unsigned int rpm_from_cnt(u8 val, u32 clk, u16 div)
• drivers/hwmon/g762.c:255:48-255:62: static int do_set_clk_freq(struct device *dev, unsigned long val)
• drivers/hwmon/g762.c:270:48-270:62: static int do_set_pwm_mode(struct device *dev, unsigned long val)
• drivers/hwmon/g762.c:300:47-300:61: static int do_set_fan_div(struct device *dev, unsigned long val)
• drivers/hwmon/g762.c:340:53-340:67: static int do_set_fan_gear_mode(struct device *dev, unsigned long val)
• drivers/hwmon/g762.c:376:50-376:64: static int do_set_fan_pulses(struct device *dev, unsigned long val)
• drivers/hwmon/g762.c:406:50-406:64: static int do_set_pwm_enable(struct device *dev, unsigned long val)
• drivers/hwmon/g762.c:447:52-447:66: static int do_set_pwm_polarity(struct device *dev, unsigned long val)
• drivers/hwmon/g762.c:480:43-480:57: static int do_set_pwm(struct device *dev, unsigned long val)
• drivers/hwmon/g762.c:501:50-501:64: static int do_set_fan_target(struct device *dev, unsigned long val)
• drivers/hwmon/g762.c:523:50-523:64: static int do_set_fan_startv(struct device *dev, unsigned long val)
• drivers/hwmon/gsc-hwmon.c:147:22-147:28: int channel, long *val)
• drivers/hwmon/gxp-fan-ctrl.c:58:69-58:74: static int gxp_pwm_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/gxp-fan-ctrl.c:74:33-74:38: u32 attr, int channel, long val)
• drivers/hwmon/gxp-fan-ctrl.c:84:68-84:74: static int gxp_fan_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/gxp-fan-ctrl.c:98:68-98:74: static int gxp_pwm_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/gxp-fan-ctrl.c:120:32-120:38: u32 attr, int channel, long *val)
• drivers/hwmon/hp-wmi-sensors.c:1403:33-1403:38: u32 attr, int channel, long val)
• drivers/hwmon/hs3001.c:109:33-109:39: u32 attr, int channel, long *val)
• drivers/hwmon/hwmon-vid.c:69:18-69:22: int vid_from_reg(int val, u8 vrm)
• drivers/hwmon/i5500_temp.c:39:9-39:15: long *val)
• drivers/hwmon/i5k_amb.c:121:7-121:10: u8 val)
• drivers/hwmon/ina209.c:108:43-108:53: static long ina209_from_reg(const u8 reg, const u16 val)
• drivers/hwmon/ina209.c:158:43-158:48: static int ina209_to_reg(u8 reg, u16 old, long val)
• drivers/hwmon/ina238.c:113:71-113:76: static int ina238_read_reg24(const struct i2c_client *client, u8 reg, u32 *val)
• drivers/hwmon/ina238.c:130:6-130:12: long *val)
• drivers/hwmon/ina238.c:215:7-215:12: long val)
• drivers/hwmon/ina238.c:263:62-263:68: static int ina238_read_current(struct device *dev, u32 attr, long *val)
• drivers/hwmon/ina238.c:286:60-286:66: static int ina238_read_power(struct device *dev, u32 attr, long *val)
• drivers/hwmon/ina238.c:333:61-333:66: static int ina238_write_power(struct device *dev, u32 attr, long val)
• drivers/hwmon/ina238.c:354:59-354:65: static int ina238_read_temp(struct device *dev, u32 attr, long *val)
• drivers/hwmon/ina238.c:391:60-391:65: static int ina238_write_temp(struct device *dev, u32 attr, long val)
• drivers/hwmon/ina238.c:407:33-407:39: u32 attr, int channel, long *val)
• drivers/hwmon/ina238.c:425:33-425:38: u32 attr, int channel, long val)
• drivers/hwmon/ina2xx.c:344:66-344:70: static s16 ina226_alert_to_reg(struct ina2xx_data *data, u8 bit, int val)
• drivers/hwmon/ina2xx.c:460:55-460:60: static int ina2xx_set_shunt(struct ina2xx_data *data, long val)
• drivers/hwmon/ina3221.c:218:10-218:15: int *val)
• drivers/hwmon/ina3221.c:249:60-249:66: static int ina3221_read_chip(struct device *dev, u32 attr, long *val)
• drivers/hwmon/ina3221.c:269:71-269:77: static int ina3221_read_in(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/ina3221.c:327:22-327:28: int channel, long *val)
• drivers/hwmon/ina3221.c:388:61-388:66: static int ina3221_write_chip(struct device *dev, u32 attr, long val)
• drivers/hwmon/ina3221.c:431:23-431:28: int channel, long val)
• drivers/hwmon/ina3221.c:525:27-525:33: u32 attr, int channel, long *val)
• drivers/hwmon/ina3221.c:554:28-554:33: u32 attr, int channel, long val)
• drivers/hwmon/intel-m10-bmc-hwmon.c:590:27-590:33: unsigned int regoff, long *val)
• drivers/hwmon/intel-m10-bmc-hwmon.c:615:32-615:38: u32 attr, int channel, long *val)
• drivers/hwmon/it87.c:97:53-97:57: static inline void superio_outb(int ioreg, int reg, int val)
• drivers/hwmon/it87.c:656:59-656:64: static u8 in_to_reg(const struct it87_data *data, int nr, long val)
• drivers/hwmon/it87.c:662:62-662:66: static int in_from_reg(const struct it87_data *data, int nr, int val)
• drivers/hwmon/it87.c:692:52-692:57: static u8 pwm_to_reg(const struct it87_data *data, long val)
• drivers/hwmon/it87.c:708:23-708:27: static int DIV_TO_REG(int val)
• drivers/hwmon/jc42.c:236:31-236:37: u32 attr, int channel, long *val)
• drivers/hwmon/jc42.c:327:32-327:37: u32 attr, int channel, long val)
• drivers/hwmon/k10temp.c:132:41-132:46: unsigned int base, int offset, u32 *val)
• drivers/hwmon/k10temp.c:205:9-205:15: long *val)
• drivers/hwmon/k10temp.c:252:27-252:33: u32 attr, int channel, long *val)
• drivers/hwmon/k8temp.c:87:29-87:35: u32 attr, int channel, long *val)
• drivers/hwmon/lan966x-hwmon.c:78:56-78:62: static int lan966x_hwmon_read_temp(struct device *dev, long *val)
• drivers/hwmon/lan966x-hwmon.c:97:55-97:61: static int lan966x_hwmon_read_fan(struct device *dev, long *val)
• drivers/hwmon/lan966x-hwmon.c:116:55-116:61: static int lan966x_hwmon_read_pwm(struct device *dev, long *val)
• drivers/hwmon/lan966x-hwmon.c:131:60-131:66: static int lan966x_hwmon_read_pwm_freq(struct device *dev, long *val)
• drivers/hwmon/lan966x-hwmon.c:154:33-154:39: u32 attr, int channel, long *val)
• drivers/hwmon/lan966x-hwmon.c:175:56-175:61: static int lan966x_hwmon_write_pwm(struct device *dev, long val)
• drivers/hwmon/lan966x-hwmon.c:187:61-187:66: static int lan966x_hwmon_write_pwm_freq(struct device *dev, long val)
• drivers/hwmon/lan966x-hwmon.c:204:34-204:39: u32 attr, int channel, long val)
• drivers/hwmon/lm63.c:190:59-190:64: static inline int lut_temp_to_reg(struct lm63_data *data, long val)
• drivers/hwmon/lm75.c:342:31-342:37: u32 attr, int channel, long *val)
• drivers/hwmon/lm75.c:417:53-417:58: static int lm75_update_interval(struct device *dev, long val)
• drivers/hwmon/lm75.c:460:58-460:63: static int lm75_write_chip(struct device *dev, u32 attr, long val)
• drivers/hwmon/lm75.c:472:32-472:37: u32 attr, int channel, long val)
• drivers/hwmon/lm78.c:72:28-72:42: static inline u8 IN_TO_REG(unsigned long val)
• drivers/hwmon/lm78.c:88:32-88:35: static inline int FAN_FROM_REG(u8 val, int div)
• drivers/hwmon/lm78.c:97:30-97:35: static inline s8 TEMP_TO_REG(long val)
• drivers/hwmon/lm78.c:103:33-103:36: static inline int TEMP_FROM_REG(s8 val)
• drivers/hwmon/lm83.c:109:66-109:80: static int lm83_regmap_reg_read(void *context, unsigned int reg, unsigned int *val)
• drivers/hwmon/lm83.c:128:67-128:80: static int lm83_regmap_reg_write(void *context, unsigned int reg, unsigned int val)
• drivers/hwmon/lm83.c:176:70-176:76: static int lm83_temp_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/lm83.c:225:71-225:76: static int lm83_temp_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/lm83.c:250:70-250:76: static int lm83_chip_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/lm83.c:275:31-275:37: u32 attr, int channel, long *val)
• drivers/hwmon/lm83.c:288:32-288:37: u32 attr, int channel, long val)
• drivers/hwmon/lm85.c:136:30-136:44: static inline u16 FAN_TO_REG(unsigned long val)
• drivers/hwmon/lm90.c:784:62-784:65: static int lm90_write_reg(struct i2c_client *client, u8 reg, u8 val)
• drivers/hwmon/lm90.c:794:70-794:74: static int lm90_write16(struct i2c_client *client, u8 regh, u8 regl, u16 val)
• drivers/hwmon/lm90.c:878:56-878:60: static int lm90_write_convrate(struct lm90_data *data, int val)
• drivers/hwmon/lm90.c:925:35-925:39: struct lm90_data *data, int val)
• drivers/hwmon/lm90.c:1362:40-1362:45: static u16 lm90_temp_to_reg(u32 flags, long val, u8 resolution)
• drivers/hwmon/lm90.c:1381:74-1381:79: static int lm90_set_temp(struct lm90_data *data, int index, int channel, long val)
• drivers/hwmon/lm90.c:1437:54-1437:59: static int lm90_set_temphyst(struct lm90_data *data, long val)
• drivers/hwmon/lm90.c:1455:81-1455:86: static int lm90_set_temp_offset(struct lm90_data *data, int index, int channel, long val)
• drivers/hwmon/lm90.c:1509:70-1509:76: static int lm90_temp_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/lm90.c:1581:71-1581:76: static int lm90_temp_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/lm90.c:1653:70-1653:76: static int lm90_chip_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/lm90.c:1700:71-1700:76: static int lm90_chip_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/lm90.c:1744:31-1744:37: u32 attr, int channel, long *val)
• drivers/hwmon/lm90.c:1767:32-1767:37: u32 attr, int channel, long val)
• drivers/hwmon/lm92.c:69:31-69:36: static inline s16 TEMP_TO_REG(long val)
• drivers/hwmon/lm93.c:358:34-358:43: static u8 LM93_IN_TO_REG(int nr, unsigned val)
• drivers/hwmon/lm93.c:397:30-397:39: static u8 LM93_IN_REL_TO_REG(unsigned val, int upper, int vid)
• drivers/hwmon/lm95241.c:130:9-130:15: long *val)
• drivers/hwmon/lm95241.c:144:9-144:15: long *val)
• drivers/hwmon/lm95241.c:187:27-187:33: u32 attr, int channel, long *val)
• drivers/hwmon/lm95241.c:200:10-200:15: long val)
• drivers/hwmon/lm95241.c:239:10-239:15: long val)
• drivers/hwmon/lm95241.c:323:28-323:33: u32 attr, int channel, long val)
• drivers/hwmon/lm95245.c:160:9-160:15: long *val)
• drivers/hwmon/lm95245.c:277:10-277:15: long val)
• drivers/hwmon/lm95245.c:338:9-338:15: long *val)
• drivers/hwmon/lm95245.c:352:10-352:15: long val)
• drivers/hwmon/lm95245.c:369:27-369:33: u32 attr, int channel, long *val)
• drivers/hwmon/lm95245.c:382:28-382:33: u32 attr, int channel, long val)
• drivers/hwmon/lochnagar-hwmon.c:174:34-174:40: unsigned int precision, long *val)
• drivers/hwmon/lochnagar-hwmon.c:203:53-203:59: static int read_power(struct device *dev, int chan, long *val)
• drivers/hwmon/lochnagar-hwmon.c:256:26-256:32: u32 attr, int chan, long *val)
• drivers/hwmon/lochnagar-hwmon.c:300:27-300:32: u32 attr, int chan, long val)
• drivers/hwmon/ltc2945.c:170:9-170:28: unsigned long long val)
• drivers/hwmon/ltc2947-core.c:133:5-133:10: u64 *val)
• drivers/hwmon/ltc2947-core.c:148:5-148:10: u64 *val)
• drivers/hwmon/ltc2947-core.c:163:5-163:10: u64 *val)
• drivers/hwmon/ltc2947-core.c:178:42-178:47: const u8 page, const size_t size, s64 *val)
• drivers/hwmon/ltc2947-core.c:222:6-222:16: const u64 val)
• drivers/hwmon/ltc2947-core.c:231:6-231:16: const u16 val)
• drivers/hwmon/ltc2947-core.c:240:43-240:53: const u8 page, const size_t size, const u64 val)
• drivers/hwmon/ltc2947-core.c:288:26-288:32: const u32 mask, long *val)
• drivers/hwmon/ltc2947-core.c:339:66-339:72: static int ltc2947_read_temp(struct device *dev, const u32 attr, long *val,
• drivers/hwmon/ltc2947-core.c:404:67-404:73: static int ltc2947_read_power(struct device *dev, const u32 attr, long *val)
• drivers/hwmon/ltc2947-core.c:451:66-451:72: static int ltc2947_read_curr(struct device *dev, const u32 attr, long *val)
• drivers/hwmon/ltc2947-core.c:498:64-498:70: static int ltc2947_read_in(struct device *dev, const u32 attr, long *val,
• drivers/hwmon/ltc2947-core.c:591:27-591:33: u32 attr, int channel, long *val)
• drivers/hwmon/ltc2947-core.c:608:10-608:15: long val, const int channel)
• drivers/hwmon/ltc2947-core.c:659:11-659:16: long val)
• drivers/hwmon/ltc2947-core.c:685:10-685:15: long val)
• drivers/hwmon/ltc2947-core.c:710:65-710:70: static int ltc2947_write_in(struct device *dev, const u32 attr, long val,
• drivers/hwmon/ltc2947-core.c:762:28-762:33: u32 attr, int channel, long val)
• drivers/hwmon/ltc2992.c:205:83-205:87: static int ltc2992_write_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len, u32 val)
• drivers/hwmon/ltc2992.c:408:78-408:84: static int ltc2992_get_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long *val)
• drivers/hwmon/ltc2992.c:422:78-422:83: static int ltc2992_set_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long val)
• drivers/hwmon/ltc2992.c:430:85-430:91: static int ltc2992_read_gpio_alarm(struct ltc2992_state *st, int nr_gpio, u32 attr, long *val)
• drivers/hwmon/ltc2992.c:450:77-450:83: static int ltc2992_read_gpios_in(struct device *dev, u32 attr, int nr_gpio, long *val)
• drivers/hwmon/ltc2992.c:481:73-481:79: static int ltc2992_read_in_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
• drivers/hwmon/ltc2992.c:501:71-501:77: static int ltc2992_read_in(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/ltc2992.c:535:80-535:86: static int ltc2992_get_current(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
• drivers/hwmon/ltc2992.c:549:80-549:85: static int ltc2992_set_current(struct ltc2992_state *st, u32 reg, u32 channel, long val)
• drivers/hwmon/ltc2992.c:559:75-559:81: static int ltc2992_read_curr_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
• drivers/hwmon/ltc2992.c:579:73-579:79: static int ltc2992_read_curr(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/ltc2992.c:610:78-610:84: static int ltc2992_get_power(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
• drivers/hwmon/ltc2992.c:624:78-624:83: static int ltc2992_set_power(struct ltc2992_state *st, u32 reg, u32 channel, long val)
• drivers/hwmon/ltc2992.c:634:76-634:82: static int ltc2992_read_power_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
• drivers/hwmon/ltc2992.c:654:74-654:80: static int ltc2992_read_power(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/ltc2992.c:686:4-686:10: long *val)
• drivers/hwmon/ltc2992.c:700:74-700:79: static int ltc2992_write_curr(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/ltc2992.c:719:78-719:83: static int ltc2992_write_gpios_in(struct device *dev, u32 attr, int nr_gpio, long val)
• drivers/hwmon/ltc2992.c:738:72-738:77: static int ltc2992_write_in(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/ltc2992.c:760:75-760:80: static int ltc2992_write_power(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/ltc2992.c:779:74-779:79: static int ltc2992_write_chip(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/ltc2992.c:793:5-793:10: long val)
• drivers/hwmon/ltc4245.c:269:9-269:15: long *val)
• drivers/hwmon/ltc4245.c:285:71-285:77: static int ltc4245_read_in(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/ltc4245.c:315:10-315:16: long *val)
• drivers/hwmon/ltc4245.c:333:27-333:33: u32 attr, int channel, long *val)
• drivers/hwmon/max127.c:72:59-72:65: static int max127_read_channel(struct i2c_client *client, long *val)
• drivers/hwmon/max127.c:117:69-117:75: static int max127_read_input(struct max127_data *data, int channel, long *val)
• drivers/hwmon/max127.c:141:67-141:73: static int max127_read_min(struct max127_data *data, int channel, long *val)
• drivers/hwmon/max127.c:155:67-155:73: static int max127_read_max(struct max127_data *data, int channel, long *val)
• drivers/hwmon/max127.c:169:68-169:73: static int max127_write_min(struct max127_data *data, int channel, long val)
• drivers/hwmon/max127.c:191:68-191:73: static int max127_write_max(struct max127_data *data, int channel, long val)
• drivers/hwmon/max127.c:227:27-227:33: u32 attr, int channel, long *val)
• drivers/hwmon/max127.c:257:27-257:32: u32 attr, int channel, long val)
• drivers/hwmon/max1619.c:55:26-55:30: static int temp_from_reg(int val)
• drivers/hwmon/max1619.c:60:24-60:28: static int temp_to_reg(int val)
• drivers/hwmon/max31730.c:116:28-116:34: u32 attr, int channel, long *val)
• drivers/hwmon/max31730.c:186:29-186:34: u32 attr, int channel, long val)
• drivers/hwmon/max31760.c:78:28-78:34: u32 attr, int channel, long *val)
• drivers/hwmon/max31760.c:237:29-237:34: u32 attr, int channel, long val)
• drivers/hwmon/max31790.c:166:9-166:15: long *val)
• drivers/hwmon/max31790.c:214:10-214:15: long val)
• drivers/hwmon/max31790.c:303:9-303:15: long *val)
• drivers/hwmon/max31790.c:331:10-331:15: long val)
• drivers/hwmon/max31790.c:409:28-409:34: u32 attr, int channel, long *val)
• drivers/hwmon/max31790.c:422:29-422:34: u32 attr, int channel, long val)
• drivers/hwmon/max31827.c:58:7-58:12: long val)
• drivers/hwmon/max31827.c:130:28-130:34: u32 attr, int channel, long *val)
• drivers/hwmon/max31827.c:284:29-284:34: u32 attr, int channel, long val)
• drivers/hwmon/max6620.c:145:36-145:39: static u8 max6620_fan_div_from_reg(u8 val)
• drivers/hwmon/max6620.c:245:20-245:26: int channel, long *val)
• drivers/hwmon/max6620.c:322:21-322:26: int channel, long val)
• drivers/hwmon/max6621.c:133:33-133:38: static long max6621_temp_mc2reg(long val)
• drivers/hwmon/max6621.c:202:20-202:26: int channel, long *val)
• drivers/hwmon/max6621.c:311:21-311:26: int channel, long val)
• drivers/hwmon/max6650.c:520:27-520:33: u32 attr, int channel, long *val)
• drivers/hwmon/max6650.c:611:28-611:33: u32 attr, int channel, long val)
• drivers/hwmon/max6697.c:176:44-176:48: static inline int max6581_offset_to_millic(int val)
• drivers/hwmon/mc13783-adc.c:41:37-41:51: struct device_attribute *devattr, unsigned int *val)
• drivers/hwmon/mc34vr500.c:98:5-98:11: long *val)
• drivers/hwmon/mc34vr500.c:113:29-113:35: u32 attr, int channel, long *val)
• drivers/hwmon/mcp3021.c:54:61-54:65: static inline u16 volts_from_reg(struct mcp3021_data *data, u16 val)
• drivers/hwmon/mcp3021.c:60:27-60:33: u32 attr, int channel, long *val)
• drivers/hwmon/mlxreg-fan.c:121:16-121:22: int channel, long *val)
• drivers/hwmon/mlxreg-fan.c:206:17-206:22: int channel, long val)
• drivers/hwmon/mr75203.c:277:69-277:75: static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/mr75203.c:311:67-311:73: static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/mr75203.c:361:30-361:36: u32 attr, int channel, long *val)
• drivers/hwmon/nct6683.c:77:34-77:38: superio_outb(int ioreg, int reg, int val)
• drivers/hwmon/nct6775-core.c:1007:28-1007:32: static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scales)
• drivers/hwmon/nct6775-core.c:1212:66-1212:71: static int nct6775_read_temp(struct nct6775_data *data, u16 reg, u16 *val)
• drivers/hwmon/nct6775-i2c.c:28:58-28:72: static int nct6775_i2c_read(void *ctx, unsigned int reg, unsigned int *val)
• drivers/hwmon/nct6775-platform.c:129:76-129:79: static int nct6775_asuswmi_evaluate_method(u32 method_id, u8 bank, u8 reg, u8 val, u32 *retval)
• drivers/hwmon/nct6775-platform.c:162:58-162:61: static inline int nct6775_asuswmi_write(u8 bank, u8 reg, u8 val)
• drivers/hwmon/nct6775-platform.c:168:57-168:61: static inline int nct6775_asuswmi_read(u8 bank, u8 reg, u8 *val)
• drivers/hwmon/nct6775-platform.c:187:74-187:78: static void superio_wmi_outb(struct nct6775_sio_data *sio_data, int reg, int val)
• drivers/hwmon/nct6775-platform.c:207:70-207:74: static void superio_outb(struct nct6775_sio_data *sio_data, int reg, int val)
• drivers/hwmon/nct6775-platform.c:264:62-264:76: static int nct6775_wmi_reg_read(void *ctx, unsigned int reg, unsigned int *val)
• drivers/hwmon/nct6775-platform.c:326:58-326:72: static int nct6775_reg_read(void *ctx, unsigned int reg, unsigned int *val)
• drivers/hwmon/nct7904.c:207:46-207:49: unsigned int bank, unsigned int reg, u8 val)
• drivers/hwmon/nct7904.c:221:8-221:14: long *val)
• drivers/hwmon/nct7904.c:300:7-300:13: long *val)
• drivers/hwmon/nct7904.c:388:9-388:15: long *val)
• drivers/hwmon/nct7904.c:540:8-540:14: long *val)
• drivers/hwmon/nct7904.c:565:10-565:15: long val)
• drivers/hwmon/nct7904.c:610:9-610:14: long val)
• drivers/hwmon/nct7904.c:637:8-637:13: long val)
• drivers/hwmon/nct7904.c:696:9-696:14: long val)
• drivers/hwmon/nct7904.c:732:27-732:33: u32 attr, int channel, long *val)
• drivers/hwmon/nct7904.c:749:28-749:33: u32 attr, int channel, long val)
• drivers/hwmon/npcm750-pwm-fan.c:211:20-211:24: int channel, u16 val)
• drivers/hwmon/npcm750-pwm-fan.c:505:8-505:14: long *val)
• drivers/hwmon/npcm750-pwm-fan.c:522:9-522:14: long val)
• drivers/hwmon/npcm750-pwm-fan.c:557:8-557:14: long *val)
• drivers/hwmon/npcm750-pwm-fan.c:595:27-595:33: u32 attr, int channel, long *val)
• drivers/hwmon/npcm750-pwm-fan.c:608:28-608:33: u32 attr, int channel, long val)
• drivers/hwmon/ntc_thermistor.c:507:30-507:36: u32 attr, int channel, long *val)
• drivers/hwmon/nzxt-kraken2.c:46:27-46:33: u32 attr, int channel, long *val)
• drivers/hwmon/nzxt-smart2.c:209:29-209:34: static long scale_pwm_value(long val, long orig_max, long new_max)
• drivers/hwmon/nzxt-smart2.c:339:30-339:36: u32 attr, int channel, long *val)
• drivers/hwmon/nzxt-smart2.c:464:58-464:63: static int set_pwm(struct drvdata *drvdata, int channel, long val)
• drivers/hwmon/nzxt-smart2.c:509:65-509:70: static int set_pwm_enable(struct drvdata *drvdata, int channel, long val)
• drivers/hwmon/nzxt-smart2.c:560:57-560:62: static int set_update_interval(struct drvdata *drvdata, long val)
• drivers/hwmon/nzxt-smart2.c:601:21-601:26: int channel, long val)
• drivers/hwmon/oxp-sensors.c:140:43-140:49: static int read_from_ec(u8 reg, int size, long *val)
• drivers/hwmon/oxp-sensors.c:313:32-313:38: u32 attr, int channel, long *val)
• drivers/hwmon/oxp-sensors.c:360:33-360:38: u32 attr, int channel, long val)
• drivers/hwmon/pc87360.c:87:55-87:59: static inline void superio_outb(int sioaddr, int reg, int val)
• drivers/hwmon/pc87360.c:136:29-136:33: static inline u8 PWM_TO_REG(int val, int inv)
• drivers/hwmon/pc87427.c:108:55-108:59: static inline void superio_outb(int sioaddr, int reg, int val)
• drivers/hwmon/pc87427.c:209:30-209:44: static inline u16 fan_to_reg(unsigned long val)
• drivers/hwmon/pc87427.c:263:36-263:50: static inline u8 pwm_enable_to_reg(unsigned long val, u8 pwmval)
• drivers/hwmon/peci/cputemp.c:115:88-115:94: static int get_temp_target(struct peci_cputemp *priv, enum peci_temp_target_type type, long *val)
• drivers/hwmon/peci/cputemp.c:155:23-155:27: static bool dts_valid(u16 val)
• drivers/hwmon/peci/cputemp.c:164:43-164:47: static s32 dts_ten_dot_six_to_millidegree(u16 val)
• drivers/hwmon/peci/cputemp.c:173:47-173:51: static s32 dts_eight_dot_eight_to_millidegree(u16 val)
• drivers/hwmon/peci/cputemp.c:178:52-178:58: static int get_die_temp(struct peci_cputemp *priv, long *val)
• drivers/hwmon/peci/cputemp.c:212:47-212:53: static int get_dts(struct peci_cputemp *priv, long *val)
• drivers/hwmon/peci/cputemp.c:250:69-250:75: static int get_core_temp(struct peci_cputemp *priv, int core_index, long *val)
• drivers/hwmon/peci/cputemp.c:303:27-303:33: u32 attr, int channel, long *val)
• drivers/hwmon/peci/dimmtemp.c:93:67-93:73: static int get_dimm_temp(struct peci_dimmtemp *priv, int dimm_no, long *val)
• drivers/hwmon/peci/dimmtemp.c:144:24-144:30: int dimm_no, long *val)
• drivers/hwmon/peci/dimmtemp.c:185:28-185:34: u32 attr, int channel, long *val)
• drivers/hwmon/pmbus/adm1266.c:378:64-378:70: static int adm1266_nvmem_read(void *priv, unsigned int offset, void *val, size_t bytes)
• drivers/hwmon/pmbus/mp2975.c:139:28-139:32: mp2975_vid2direct(int vrf, int val)
• drivers/hwmon/pmbus/mp2975.c:164:37-164:41: static u16 mp2975_data2reg_linear11(s64 val)
• drivers/hwmon/pmbus/pmbus_core.c:852:36-852:41: struct pmbus_sensor *sensor, long val)
• drivers/hwmon/pmbus/pmbus_core.c:916:35-916:39: struct pmbus_sensor *sensor, s64 val)
• drivers/hwmon/pmbus/pmbus_core.c:981:35-981:39: struct pmbus_sensor *sensor, s64 val)
• drivers/hwmon/pmbus/pmbus_core.c:1016:39-1016:43: struct pmbus_sensor *sensor, s64 val)
• drivers/hwmon/pmbus/pmbus_core.c:1024:35-1024:39: struct pmbus_sensor *sensor, s64 val)
• drivers/hwmon/pmbus/pmbus_core.c:3189:82-3189:85: static int pmbus_write_smbalert_mask(struct i2c_client *client, u8 page, u8 reg, u8 val)
• drivers/hwmon/pmbus/pmbus_core.c:3264:42-3264:47: static int pmbus_debugfs_get(void *data, u64 *val)
• drivers/hwmon/pmbus/pmbus_core.c:3285:49-3285:54: static int pmbus_debugfs_get_status(void *data, u64 *val)
• drivers/hwmon/pmbus/ucd9000.c:382:28-382:32: unsigned int offset, int val)
• drivers/hwmon/pmbus/ucd9000.c:451:60-451:65: static int ucd9000_debugfs_show_mfr_status_bit(void *data, u64 *val)
• drivers/hwmon/pmbus/zl6100.c:85:23-85:28: static u16 zl6100_d2l(long val)
• drivers/hwmon/powr1220.c:223:27-223:33: attr, int channel, long *val)
• drivers/hwmon/pwm-fan.c:245:59-245:64: static int pwm_fan_update_enable(struct pwm_fan_ctx *ctx, long val)
• drivers/hwmon/pwm-fan.c:293:28-293:33: u32 attr, int channel, long val)
• drivers/hwmon/pwm-fan.c:322:27-322:33: u32 attr, int channel, long *val)
• drivers/hwmon/raspberrypi-hwmon.c:76:30-76:36: u32 attr, int channel, long *val)
• drivers/hwmon/sbrmi.c:192:32-192:38: u32 attr, int channel, long *val)
• drivers/hwmon/sbrmi.c:226:33-226:38: u32 attr, int channel, long val)
• drivers/hwmon/sbtsi_temp.c:73:32-73:38: u32 attr, int channel, long *val)
• drivers/hwmon/sbtsi_temp.c:130:33-130:38: u32 attr, int channel, long val)
• drivers/hwmon/sch5627.c:236:4-236:10: long *val)
• drivers/hwmon/sch5627.c:345:5-345:10: long val)
• drivers/hwmon/sch56xx-common.c:202:50-202:53: int sch56xx_write_virtual_reg(u16 addr, u16 reg, u8 val)
• drivers/hwmon/scmi-hwmon.c:74:6-74:12: long *val)
• drivers/hwmon/scmi-hwmon.c:91:30-91:36: u32 attr, int channel, long *val)
• drivers/hwmon/sfctemp.c:156:53-156:59: static int sfctemp_convert(struct sfctemp *sfctemp, long *val)
• drivers/hwmon/sfctemp.c:195:27-195:33: u32 attr, int channel, long *val)
• drivers/hwmon/sfctemp.c:216:28-216:33: u32 attr, int channel, long val)
• drivers/hwmon/sht15.c:227:60-227:64: static inline void sht15_send_bit(struct sht15_data *data, int val)
• drivers/hwmon/sht3x.c:407:61-407:65: static int temp1_limit_write(struct device *dev, int index, int val)
• drivers/hwmon/sht3x.c:423:65-423:69: static int humidity1_limit_write(struct device *dev, int index, int val)
• drivers/hwmon/sht3x.c:550:54-550:58: static int update_interval_write(struct device *dev, int val)
• drivers/hwmon/sht3x.c:703:32-703:38: u32 attr, int channel, long *val)
• drivers/hwmon/sht3x.c:781:33-781:38: u32 attr, int channel, long val)
• drivers/hwmon/sht4x.c:130:62-130:67: static ssize_t sht4x_interval_write(struct sht4x_data *data, long val)
• drivers/hwmon/sht4x.c:138:60-138:66: static size_t sht4x_interval_read(struct sht4x_data *data, long *val)
• drivers/hwmon/sht4x.c:145:61-145:67: static int sht4x_temperature1_read(struct sht4x_data *data, long *val)
• drivers/hwmon/sht4x.c:159:58-159:64: static int sht4x_humidity1_read(struct sht4x_data *data, long *val)
• drivers/hwmon/sht4x.c:188:31-188:37: u32 attr, int channel, long *val)
• drivers/hwmon/sht4x.c:205:32-205:37: u32 attr, int channel, long val)
• drivers/hwmon/sis5595.c:120:28-120:42: static inline u8 IN_TO_REG(unsigned long val)
• drivers/hwmon/sis5595.c:136:32-136:35: static inline int FAN_FROM_REG(u8 val, int div)
• drivers/hwmon/sis5595.c:145:33-145:36: static inline int TEMP_FROM_REG(s8 val)
• drivers/hwmon/sis5595.c:149:30-149:35: static inline s8 TEMP_TO_REG(long val)
• drivers/hwmon/sis5595.c:159:29-159:33: static inline u8 DIV_TO_REG(int val)
• drivers/hwmon/smpro-hwmon.c:206:71-206:77: static int smpro_read_temp(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/smpro-hwmon.c:231:69-231:75: static int smpro_read_in(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/smpro-hwmon.c:250:71-250:77: static int smpro_read_curr(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/smpro-hwmon.c:294:32-294:38: u32 attr, int channel, long *val)
• drivers/hwmon/smsc47b397.c:44:42-44:46: static inline void superio_outb(int reg, int val)
• drivers/hwmon/smsc47m1.c:47:23-47:27: superio_outb(int reg, int val)
• drivers/hwmon/smsc47m192.c:47:25-47:30: static inline int SCALE(long val, int mul, int div)
• drivers/hwmon/smsc47m192.c:65:28-65:42: static inline u8 IN_TO_REG(unsigned long val, int n)
• drivers/hwmon/smsc47m192.c:75:30-75:35: static inline s8 TEMP_TO_REG(long val)
• drivers/hwmon/smsc47m192.c:80:33-80:36: static inline int TEMP_FROM_REG(s8 val)
• drivers/hwmon/stts751.c:112:26-112:30: static s32 stts751_to_hw(int val)
• drivers/hwmon/tc654.c:383:46-383:60: static int _set_pwm(struct tc654_data *data, unsigned long val)
• drivers/hwmon/tmp102.c:61:36-61:40: static inline int tmp102_reg_to_mC(s16 val)
• drivers/hwmon/tmp102.c:67:36-67:40: static inline u16 tmp102_mC_to_reg(int val)
• drivers/hwmon/tmp103.c:44:36-44:39: static inline int tmp103_reg_to_mc(s8 val)
• drivers/hwmon/tmp103.c:49:35-49:39: static inline u8 tmp103_mc_to_reg(int val)
• drivers/hwmon/tmp108.c:80:41-80:45: static inline int tmp108_temp_reg_to_mC(s16 val)
• drivers/hwmon/tmp108.c:86:41-86:45: static inline u16 tmp108_mC_to_temp_reg(int val)
• drivers/hwmon/tmp401.c:143:61-143:75: static int tmp401_reg_read(void *context, unsigned int reg, unsigned int *val)
• drivers/hwmon/tmp401.c:228:62-228:75: static int tmp401_reg_write(void *context, unsigned int reg, unsigned int val)
• drivers/hwmon/tmp401.c:307:72-307:78: static int tmp401_temp_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/tmp401.c:360:9-360:14: long val)
• drivers/hwmon/tmp401.c:400:72-400:78: static int tmp401_chip_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/tmp401.c:423:55-423:60: static int tmp401_set_convrate(struct regmap *regmap, long val)
• drivers/hwmon/tmp401.c:440:73-440:78: static int tmp401_chip_write(struct device *dev, u32 attr, int channel, long val)
• drivers/hwmon/tmp401.c:472:33-472:39: u32 attr, int channel, long *val)
• drivers/hwmon/tmp401.c:485:27-485:32: u32 attr, int channel, long val)
• drivers/hwmon/tmp421.c:197:33-197:39: u32 attr, int channel, long *val)
• drivers/hwmon/tmp421.c:242:27-242:32: u32 attr, int channel, long val)
• drivers/hwmon/tmp464.c:133:72-133:78: static int tmp464_chip_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/tmp464.c:146:72-146:78: static int tmp464_temp_read(struct device *dev, u32 attr, int channel, long *val)
• drivers/hwmon/tmp464.c:248:33-248:39: u32 attr, int channel, long *val)
• drivers/hwmon/tmp464.c:295:79-295:84: static int tmp464_chip_write(struct tmp464_data *data, u32 attr, int channel, long val)
• drivers/hwmon/tmp464.c:305:79-305:84: static int tmp464_temp_write(struct tmp464_data *data, u32 attr, int channel, long val)
• drivers/hwmon/tmp464.c:346:27-346:32: u32 attr, int channel, long val)
• drivers/hwmon/tmp513.c:183:29-183:35: unsigned int regval, long *val)
• drivers/hwmon/tmp513.c:243:63-243:68: static int tmp51x_set_value(struct tmp51x_data *data, u8 reg, long val)
• drivers/hwmon/tmp513.c:396:33-396:39: u32 attr, int channel, long *val)
• drivers/hwmon/tmp513.c:418:27-418:32: u32 attr, int channel, long val)
• drivers/hwmon/tps23861.c:126:59-126:65: static int tps23861_read_temp(struct tps23861_data *data, long *val)
• drivers/hwmon/tps23861.c:141:6-141:12: long *val)
• drivers/hwmon/tps23861.c:166:6-166:12: long *val)
• drivers/hwmon/tps23861.c:249:29-249:34: u32 attr, int channel, long val)
• drivers/hwmon/tps23861.c:277:28-277:34: u32 attr, int channel, long *val)
• drivers/hwmon/via686a.c:116:28-116:33: static inline u8 IN_TO_REG(long val, int in_num)
• drivers/hwmon/via686a.c:136:32-136:35: static inline long IN_FROM_REG(u8 val, int in_num)
• drivers/hwmon/via686a.c:273:30-273:35: static inline u8 TEMP_TO_REG(long val)
• drivers/hwmon/via686a.c:283:36-283:40: static inline long TEMP_FROM_REG10(u16 val)
• drivers/hwmon/vt1211.c:236:68-236:71: static inline void vt1211_write8(struct vt1211_data *data, u8 reg, u8 val)
• drivers/hwmon/w83627ehf.c:95:34-95:38: superio_outb(int ioreg, int reg, int val)
• drivers/hwmon/w83627ehf.c:296:28-296:32: static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
• drivers/hwmon/w83627ehf.c:713:1-713:1: store_in_reg(MIN, min)
• drivers/hwmon/w83627ehf.c:714:1-714:1: store_in_reg(MAX, max)
• drivers/hwmon/w83627ehf.c:718:8-718:13: long val)
• drivers/hwmon/w83627ehf.c:799:1-799:1: store_temp_reg(reg_temp_over, temp_max);
• drivers/hwmon/w83627ehf.c:800:1-800:1: store_temp_reg(reg_temp_hyst, temp_max_hyst);
• drivers/hwmon/w83627ehf.c:804:5-804:10: long val)
• drivers/hwmon/w83627ehf.c:817:9-817:14: long val)
• drivers/hwmon/w83627ehf.c:837:4-837:9: long val)
• drivers/hwmon/w83627ehf.c:850:4-850:9: long val)
• drivers/hwmon/w83627ehf.c:1090:9-1090:14: long val)
• drivers/hwmon/w83627ehf.c:1431:23-1431:29: int channel, long *val)
• drivers/hwmon/w83627ehf.c:1466:21-1466:27: int channel, long *val)
• drivers/hwmon/w83627ehf.c:1495:22-1495:28: int channel, long *val)
• drivers/hwmon/w83627ehf.c:1523:22-1523:28: int channel, long *val)
• drivers/hwmon/w83627ehf.c:1543:21-1543:27: int channel, long *val)
• drivers/hwmon/w83627ehf.c:1554:27-1554:33: u32 attr, int channel, long *val)
• drivers/hwmon/w83627ehf.c:1604:27-1604:32: u32 attr, int channel, long val)
• drivers/hwmon/w83627hf.c:100:54-100:58: superio_outb(struct w83627hf_sio_data *sio, int reg, int val)
• drivers/hwmon/w83627hf.c:290:40-290:54: static inline u8 pwm_freq_to_reg_627hf(unsigned long val)
• drivers/hwmon/w83627hf.c:316:34-316:48: static inline u8 pwm_freq_to_reg(unsigned long val)
• drivers/hwmon/w83627hf.c:334:29-334:34: static inline u8 DIV_TO_REG(long val)
• drivers/hwmon/w83773g.c:61:50-61:56: static int get_local_temp(struct regmap *regmap, long *val)
• drivers/hwmon/w83773g.c:74:62-74:68: static int get_remote_temp(struct regmap *regmap, int index, long *val)
• drivers/hwmon/w83773g.c:92:56-92:62: static int get_fault(struct regmap *regmap, int index, long *val)
• drivers/hwmon/w83773g.c:105:57-105:63: static int get_offset(struct regmap *regmap, int index, long *val)
• drivers/hwmon/w83773g.c:123:57-123:62: static int set_offset(struct regmap *regmap, int index, long val)
• drivers/hwmon/w83773g.c:142:55-142:61: static int get_update_interval(struct regmap *regmap, long *val)
• drivers/hwmon/w83773g.c:155:55-155:60: static int set_update_interval(struct regmap *regmap, long val)
• drivers/hwmon/w83773g.c:173:33-173:39: u32 attr, int channel, long *val)
• drivers/hwmon/w83773g.c:198:27-198:32: u32 attr, int channel, long val)
• drivers/hwmon/w83781d.c:162:14-162:17: FAN_FROM_REG(u8 val, int div)
• drivers/hwmon/w83781d.c:182:12-182:17: DIV_TO_REG(long val, enum chips type)
• drivers/hwmon/w83791d.c:255:30-255:35: static u8 div_to_reg(int nr, long val)
• drivers/hwmon/w83792d.c:248:12-248:17: DIV_TO_REG(long val)
• drivers/hwmon/w83793.c:170:42-170:46: static inline unsigned long FAN_FROM_REG(u16 val)
• drivers/hwmon/w83793.c:189:30-189:44: static inline u8 TIME_TO_REG(unsigned long val)
• drivers/hwmon/w83793.c:199:30-199:35: static inline s8 TEMP_TO_REG(long val, s8 min, s8 max)
• drivers/hwmon/w83795.c:225:41-225:45: static inline u16 in_from_reg(u8 index, u16 val)
• drivers/hwmon/w83795.c:234:39-234:43: static inline u16 in_to_reg(u8 index, u16 val)
• drivers/hwmon/w83795.c:242:42-242:46: static inline unsigned long fan_from_reg(u16 val)
• drivers/hwmon/w83795.c:261:30-261:44: static inline u8 time_to_reg(unsigned long val)
• drivers/hwmon/w83795.c:271:30-271:35: static inline s8 temp_to_reg(long val, s8 min, s8 max)
• drivers/hwmon/w83795.c:292:27-292:41: static u8 pwm_freq_to_reg(unsigned long val, u16 clkin)
• drivers/hwmon/w83l786ng.c:100:12-100:17: DIV_TO_REG(long val)
• drivers/hwmon/xgene-hwmon.c:277:65-277:70: static int xgene_hwmon_get_cpu_pwr(struct xgene_hwmon_dev *ctx, u32 *val)
• drivers/hwmon/xgene-hwmon.c:294:64-294:69: static int xgene_hwmon_get_io_pwr(struct xgene_hwmon_dev *ctx, u32 *val)
• drivers/hwmon/xgene-hwmon.c:311:62-311:67: static int xgene_hwmon_get_temp(struct xgene_hwmon_dev *ctx, u32 *val)
• drivers/hwtracing/intel_th/gth.c:252:7-252:20: unsigned int val)
• drivers/hwtracing/ptt/hisi_ptt.c:874:43-874:47: static int hisi_ptt_trace_valid_direction(u32 val)
• drivers/hwtracing/ptt/hisi_ptt.c:897:38-897:42: static int hisi_ptt_trace_valid_type(u32 val)
• drivers/hwtracing/ptt/hisi_ptt.c:924:40-924:44: static int hisi_ptt_trace_valid_format(u32 val)
• drivers/i2c/busses/i2c-at91-core.c:33:61-33:70: void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
• drivers/i2c/busses/i2c-axxia.c:641:57-641:61: static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-bcm-iproc.c:252:21-252:25: u32 offset, u32 val)
• drivers/i2c/busses/i2c-bcm2835.c:74:20-74:24: u32 reg, u32 val)
• drivers/i2c/busses/i2c-davinci.c:145:16-145:20: int reg, u16 val)
• drivers/i2c/busses/i2c-davinci.c:156:9-156:13: int val)
• drivers/i2c/busses/i2c-davinci.c:318:59-318:63: static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-davinci.c:705:10-705:24: unsigned long val, void *data)
• drivers/i2c/busses/i2c-designware-common.c:62:57-62:71: static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
• drivers/i2c/busses/i2c-designware-common.c:71:58-71:71: static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
• drivers/i2c/busses/i2c-designware-common.c:80:62-80:76: static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
• drivers/i2c/busses/i2c-designware-common.c:89:63-89:76: static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
• drivers/i2c/busses/i2c-designware-common.c:98:62-98:76: static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
• drivers/i2c/busses/i2c-designware-common.c:108:63-108:76: static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
• drivers/i2c/busses/i2c-designware-platdrv.c:73:58-73:72: static int bt1_i2c_read(void *context, unsigned int reg, unsigned int *val)
• drivers/i2c/busses/i2c-designware-platdrv.c:90:59-90:72: static int bt1_i2c_write(void *context, unsigned int reg, unsigned int val)
• drivers/i2c/busses/i2c-fsi.c:340:55-340:59: static void fsi_i2c_set_scl(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-fsi.c:363:55-363:59: static void fsi_i2c_set_sda(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-gpio.c:103:1-103:1: WIRE_ATTRIBUTE(scl);
• drivers/i2c/busses/i2c-gpio.c:104:1-104:1: WIRE_ATTRIBUTE(sda);
• drivers/i2c/busses/i2c-gpio.c:103:1-103:1: WIRE_ATTRIBUTE(scl);
• drivers/i2c/busses/i2c-gpio.c:104:1-104:1: WIRE_ATTRIBUTE(sda);
• drivers/i2c/busses/i2c-imx.c:315:38-315:51: static inline void imx_i2c_write_reg(unsigned int val,
• drivers/i2c/busses/i2c-imx.c:715:33-715:37: enum i2c_slave_event event, u8 *val)
• drivers/i2c/busses/i2c-jz4780.c:178:32-178:47: unsigned long offset, unsigned short val)
• drivers/i2c/busses/i2c-meson.c:112:11-112:15: u32 val)
• drivers/i2c/busses/i2c-mt65xx.c:546:49-546:53: static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
• drivers/i2c/busses/i2c-ocores.c:280:28-280:31: int reg, u8 mask, u8 val,
• drivers/i2c/busses/i2c-octeon-core.c:735:58-735:62: static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-octeon-core.h:125:44-125:48: static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
• drivers/i2c/busses/i2c-omap.c:266:20-266:24: int reg, u16 val)
• drivers/i2c/busses/i2c-omap.c:1300:56-1300:60: static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-owl.c:107:51-107:64: static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state)
• drivers/i2c/busses/i2c-pasemi-core.c:45:67-45:71: static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val)
• drivers/i2c/busses/i2c-pca-platform.c:57:54-57:58: static void i2c_pca_pf_writebyte8(void *pd, int reg, int val)
• drivers/i2c/busses/i2c-pca-platform.c:63:55-63:59: static void i2c_pca_pf_writebyte16(void *pd, int reg, int val)
• drivers/i2c/busses/i2c-pca-platform.c:69:55-69:59: static void i2c_pca_pf_writebyte32(void *pd, int reg, int val)
• drivers/i2c/busses/i2c-pxa.c:292:67-292:71: decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
• drivers/i2c/busses/i2c-pxa.c:318:24-318:37: static void decode_ISR(unsigned int val)
• drivers/i2c/busses/i2c-pxa.c:342:24-342:37: static void decode_ICR(unsigned int val)
• drivers/i2c/busses/i2c-rcar.c:150:65-150:69: static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
• drivers/i2c/busses/i2c-rcar.c:160:60-160:64: static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val)
• drivers/i2c/busses/i2c-rcar.c:173:56-173:60: static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-rcar.c:185:56-185:60: static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-rzv2m.c:78:49-78:53: static inline void bit_setl(void __iomem *addr, u32 val)
• drivers/i2c/busses/i2c-rzv2m.c:83:49-83:53: static inline void bit_clrl(void __iomem *addr, u32 val)
• drivers/i2c/busses/i2c-uniphier-f.c:450:61-450:65: static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-uniphier.c:264:60-264:64: static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
• drivers/i2c/busses/i2c-xlp9xx.c:102:25-102:29: unsigned long reg, u32 val)
• drivers/i2c/i2c-core-base.c:181:58-181:62: static void set_scl_gpio_value(struct i2c_adapter *adap, int val)
• drivers/i2c/i2c-core-base.c:191:58-191:62: static void set_sda_gpio_value(struct i2c_adapter *adap, int val)
• drivers/i2c/i2c-core-slave.c:86:35-86:39: enum i2c_slave_event event, u8 *val)
• drivers/i2c/i2c-slave-eeprom.c:46:38-46:42: enum i2c_slave_event event, u8 *val)
• drivers/i2c/i2c-slave-testunit.c:89:38-89:42: enum i2c_slave_event event, u8 *val)
• drivers/i2c/i2c-smbus.c:207:37-207:41: enum i2c_slave_event event, u8 *val)
• drivers/i2c/muxes/i2c-mux-gpio.c:26:57-26:66: static void i2c_mux_gpio_set(const struct gpiomux *mux, unsigned val)
• drivers/i2c/muxes/i2c-mux-mlxcpld.c:61:31-61:35: struct mlxcpld_mux *mux, u32 val)
• drivers/i2c/muxes/i2c-mux-pca9541.c:99:69-99:72: static int pca9541_reg_write(struct i2c_client *client, u8 command, u8 val)
• drivers/i2c/muxes/i2c-mux-pca954x.c:283:36-283:39: struct i2c_client *client, u8 val)
• drivers/iio/accel/adis16201.c:99:10-99:15: int *val, int *val2,
• drivers/iio/accel/adis16201.c:179:11-179:15: int val,
• drivers/iio/accel/adis16209.c:106:11-106:15: int val,
• drivers/iio/accel/adis16209.c:131:10-131:15: int *val, int *val2,
• drivers/iio/accel/adxl313_core.c:253:8-253:13: int *val, int *val2, long mask)
• drivers/iio/accel/adxl313_core.c:301:9-301:13: int val, int val2, long mask)
• drivers/iio/accel/adxl355_core.c:361:10-361:20: const int val, const int val2)
• drivers/iio/accel/adxl355_core.c:486:8-486:13: int *val, int *val2, long mask)
• drivers/iio/accel/adxl355_core.c:553:9-553:13: int val, int val2, long mask)
• drivers/iio/accel/adxl367.c:710:55-710:59: static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,
• drivers/iio/accel/adxl367.c:729:57-729:61: static int adxl367_find_range(struct adxl367_state *st, int val, int val2,
• drivers/iio/accel/adxl367.c:750:11-750:16: int *val)
• drivers/iio/accel/adxl367.c:880:8-880:13: int *val, int *val2, long info)
• drivers/iio/accel/adxl367.c:930:9-930:13: int val, int val2, long info)
• drivers/iio/accel/adxl367.c:1003:9-1003:14: int *val, int *val2)
• drivers/iio/accel/adxl367.c:1051:10-1051:14: int val, int val2)
• drivers/iio/accel/adxl367.c:1202:61-1202:74: static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val)
• drivers/iio/accel/adxl372.c:399:30-399:34: unsigned int size, int val)
• drivers/iio/accel/adxl372.c:759:8-759:13: int *val, int *val2, long info)
• drivers/iio/accel/adxl372.c:795:9-795:13: int val, int val2, long info)
• drivers/iio/accel/adxl372.c:842:35-842:40: enum iio_event_info info, int *val, int *val2)
• drivers/iio/accel/adxl372.c:891:36-891:40: enum iio_event_info info, int val, int val2)
• drivers/iio/accel/adxl372.c:1017:61-1017:74: static int adxl372_set_watermark(struct iio_dev *indio_dev, unsigned int val)
• drivers/iio/accel/bma220_spi.c:116:7-116:12: int *val, int *val2, long mask)
• drivers/iio/accel/bma220_spi.c:145:8-145:12: int val, int val2, long mask)
• drivers/iio/accel/bma400_core.c:415:58-415:63: static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2)
• drivers/iio/accel/bma400_core.c:440:5-440:10: int *val)
• drivers/iio/accel/bma400_core.c:474:55-474:69: static void bma400_output_data_rate_from_raw(int raw, unsigned int *val,
• drivers/iio/accel/bma400_core.c:619:13-619:17: int val)
• drivers/iio/accel/bma400_core.c:671:10-671:23: unsigned int val)
• drivers/iio/accel/bma400_core.c:706:61-706:74: static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val)
• drivers/iio/accel/bma400_core.c:780:58-780:62: static int bma400_enable_steps(struct bma400_data *data, int val)
• drivers/iio/accel/bma400_core.c:796:59-796:64: static int bma400_get_steps_reg(struct bma400_data *data, int *val)
• drivers/iio/accel/bma400_core.c:936:41-936:46: struct iio_chan_spec const *chan, int *val,
• drivers/iio/accel/bma400_core.c:1046:42-1046:46: struct iio_chan_spec const *chan, int val, int val2,
• drivers/iio/accel/bma400_core.c:1356:8-1356:13: int *val, int *val2)
• drivers/iio/accel/bma400_core.c:1444:9-1444:13: int val, int val2)
• drivers/iio/accel/bma400_spi.c:22:7-22:13: void *val, size_t val_size)
• drivers/iio/accel/bmc150-accel-core.c:247:64-247:68: static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
• drivers/iio/accel/bmc150-accel-core.c:304:64-304:69: static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
• drivers/iio/accel/bmc150-accel-core.c:616:67-616:71: static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
• drivers/iio/accel/bmc150-accel-core.c:639:66-639:71: static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
• drivers/iio/accel/bmc150-accel-core.c:662:6-662:11: int *val)
• drivers/iio/accel/bmc150-accel-core.c:696:6-696:11: int *val, int *val2, long mask)
• drivers/iio/accel/bmc150-accel-core.c:757:7-757:11: int val, int val2, long mask)
• drivers/iio/accel/bmc150-accel-core.c:788:8-788:13: int *val, int *val2)
• drivers/iio/accel/bmc150-accel-core.c:812:9-812:13: int val, int val2)
• drivers/iio/accel/bmc150-accel-core.c:944:66-944:75: static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
• drivers/iio/accel/bmi088-accel-core.c:202:6-202:11: int *val, int *val2)
• drivers/iio/accel/bmi088-accel-core.c:225:73-225:77: static int bmi088_accel_set_sample_freq(struct bmi088_accel_data *data, int val)
• drivers/iio/accel/bmi088-accel-core.c:243:67-243:71: static int bmi088_accel_set_scale(struct bmi088_accel_data *data, int val, int val2)
• drivers/iio/accel/bmi088-accel-core.c:258:66-258:71: static int bmi088_accel_get_temp(struct bmi088_accel_data *data, int *val)
• drivers/iio/accel/bmi088-accel-core.c:278:6-278:11: int *val)
• drivers/iio/accel/bmi088-accel-core.c:297:6-297:11: int *val, int *val2, long mask)
• drivers/iio/accel/bmi088-accel-core.c:411:7-411:11: int val, int val2, long mask)
• drivers/iio/accel/bmi088-accel-spi.c:25:22-25:28: size_t reg_size, void *val, size_t val_size)
• drivers/iio/accel/cros_ec_accel_legacy.c:76:10-76:15: int *val, int *val2, long mask)
• drivers/iio/accel/cros_ec_accel_legacy.c:121:11-121:15: int val, int val2, long mask)
• drivers/iio/accel/da280.c:63:5-63:10: int *val, int *val2, long mask)
• drivers/iio/accel/da311.c:186:5-186:10: int *val, int *val2, long mask)
• drivers/iio/accel/dmard06.c:69:8-69:13: int *val, int *val2, long mask)
• drivers/iio/accel/dmard09.c:51:8-51:13: int *val, int *val2, long mask)
• drivers/iio/accel/dmard10.c:140:5-140:10: int *val, int *val2, long mask)
• drivers/iio/accel/fxls8962af-core.c:252:44-252:49: struct iio_chan_spec const *chan, int *val)
• drivers/iio/accel/fxls8962af-core.c:319:18-319:21: u8 mask, u8 val)
• drivers/iio/accel/fxls8962af-core.c:361:13-361:18: int *val)
• drivers/iio/accel/fxls8962af-core.c:378:67-378:71: static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val,
• drivers/iio/accel/fxls8962af-core.c:397:12-397:17: int *val, int *val2)
• drivers/iio/accel/fxls8962af-core.c:417:11-417:16: int *val, int *val2, long mask)
• drivers/iio/accel/fxls8962af-core.c:448:5-448:9: int val, int val2, long mask)
• drivers/iio/accel/fxls8962af-core.c:489:64-489:73: static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val)
• drivers/iio/accel/fxls8962af-core.c:504:12-504:16: int val)
• drivers/iio/accel/fxls8962af-core.c:525:6-525:11: int *val, int *val2)
• drivers/iio/accel/fxls8962af-core.c:560:7-560:11: int val, int val2)
• drivers/iio/accel/hid-sensor-accel-3d.c:136:10-136:15: int *val, int *val2,
• drivers/iio/accel/hid-sensor-accel-3d.c:198:11-198:15: int val,
• drivers/iio/accel/kionix-kx022a.c:314:29-314:42: static void kx022a_reg2freq(unsigned int val, int *val1, int *val2)
• drivers/iio/accel/kionix-kx022a.c:320:30-320:43: static void kx022a_reg2scale(unsigned int val, unsigned int *val1,
• drivers/iio/accel/kionix-kx022a.c:371:8-371:12: int val, int val2, long mask)
• drivers/iio/accel/kionix-kx022a.c:455:7-455:12: int *val)
• drivers/iio/accel/kionix-kx022a.c:471:7-471:12: int *val, int *val2, long mask)
• drivers/iio/accel/kionix-kx022a.c:519:55-519:68: static int kx022a_set_watermark(struct iio_dev *idev, unsigned int val)
• drivers/iio/accel/kxcjk-1013.c:765:49-765:53: const struct kx_odr_map *map, size_t map_size, int val, int val2)
• drivers/iio/accel/kxcjk-1013.c:779:12-779:17: int *val, int *val2)
• drivers/iio/accel/kxcjk-1013.c:794:59-794:63: static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
• drivers/iio/accel/kxcjk-1013.c:846:59-846:64: static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
• drivers/iio/accel/kxcjk-1013.c:873:61-873:65: static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val)
• drivers/iio/accel/kxcjk-1013.c:906:44-906:49: struct iio_chan_spec const *chan, int *val,
• drivers/iio/accel/kxcjk-1013.c:957:45-957:49: struct iio_chan_spec const *chan, int val,
• drivers/iio/accel/kxcjk-1013.c:989:8-989:13: int *val, int *val2)
• drivers/iio/accel/kxcjk-1013.c:1013:9-1013:13: int val, int val2)
• drivers/iio/accel/kxsd9.c:137:7-137:11: int val,
• drivers/iio/accel/kxsd9.c:161:6-161:11: int *val, int *val2, long mask)
• drivers/iio/accel/mc3230.c:84:5-84:10: int *val, int *val2, long mask)
• drivers/iio/accel/mma7455_core.c:116:8-116:13: int *val, int *val2, long mask)
• drivers/iio/accel/mma7455_core.c:166:9-166:13: int val, int val2, long mask)
• drivers/iio/accel/mma7660.c:142:5-142:10: int *val, int *val2, long mask)
• drivers/iio/accel/mma8452.c:279:11-279:15: int val, int val2)
• drivers/iio/accel/mma8452.c:442:12-442:16: int val, int val2)
• drivers/iio/accel/mma8452.c:449:63-449:67: static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
• drivers/iio/accel/mma8452.c:456:12-456:16: int val, int val2)
• drivers/iio/accel/mma8452.c:491:8-491:13: int *val, int *val2, long mask)
• drivers/iio/accel/mma8452.c:598:69-598:72: static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
• drivers/iio/accel/mma8452.c:690:9-690:13: int val, int val2)
• drivers/iio/accel/mma8452.c:711:9-711:13: int val, int val2, long mask)
• drivers/iio/accel/mma8452.c:827:11-827:16: int *val, int *val2)
• drivers/iio/accel/mma8452.c:890:5-890:9: int val, int val2)
• drivers/iio/accel/mma9551.c:54:8-54:13: int *val)
• drivers/iio/accel/mma9551.c:108:8-108:13: int *val, int *val2, long mask)
• drivers/iio/accel/mma9551.c:250:10-250:14: int val, int val2)
• drivers/iio/accel/mma9551.c:277:9-277:14: int *val, int *val2)
• drivers/iio/accel/mma9551_core.c:217:18-217:22: u16 reg, u8 *val)
• drivers/iio/accel/mma9551_core.c:242:19-242:22: u16 reg, u8 val)
• drivers/iio/accel/mma9551_core.c:267:18-267:22: u16 reg, u8 *val)
• drivers/iio/accel/mma9551_core.c:292:18-292:23: u16 reg, u16 *val)
• drivers/iio/accel/mma9551_core.c:326:19-326:23: u16 reg, u16 val)
• drivers/iio/accel/mma9551_core.c:353:18-353:23: u16 reg, u16 *val)
• drivers/iio/accel/mma9551_core.c:499:29-499:32: u16 reg, u8 mask, u8 val)
• drivers/iio/accel/mma9551_core.c:727:8-727:13: int *val, int *val2)
• drivers/iio/accel/mma9551_core.c:775:30-775:35: int mma9551_read_accel_scale(int *val, int *val2)
• drivers/iio/accel/mma9553.c:194:28-194:32: static u8 mma9553_get_bits(u16 val, u16 mask)
• drivers/iio/accel/mma9553.c:199:46-199:50: static u16 mma9553_set_bits(u16 current_val, u16 val, u16 mask)
• drivers/iio/accel/mma9553.c:264:26-264:30: u16 *p_reg_val, u16 val, u16 mask)
• drivers/iio/accel/mma9553.c:464:8-464:13: int *val, int *val2, long mask)
• drivers/iio/accel/mma9553.c:607:9-607:13: int val, int val2, long mask)
• drivers/iio/accel/mma9553.c:771:9-771:14: int *val, int *val2)
• drivers/iio/accel/mma9553.c:811:10-811:14: int val, int val2)
• drivers/iio/accel/msa311.c:589:5-589:10: int *val, int *val2)
• drivers/iio/accel/msa311.c:629:57-629:62: static int msa311_read_scale(struct iio_dev *indio_dev, int *val, int *val2)
• drivers/iio/accel/msa311.c:651:6-651:11: int *val, int *val2)
• drivers/iio/accel/msa311.c:675:7-675:12: int *val, int *val2, long mask)
• drivers/iio/accel/msa311.c:717:58-717:62: static int msa311_write_scale(struct iio_dev *indio_dev, int val, int val2)
• drivers/iio/accel/msa311.c:751:62-751:66: static int msa311_write_samp_freq(struct iio_dev *indio_dev, int val, int val2)
• drivers/iio/accel/msa311.c:794:8-794:12: int val, int val2, long mask)
• drivers/iio/accel/mxc4005.c:186:57-186:61: static int mxc4005_set_scale(struct mxc4005_data *data, int val)
• drivers/iio/accel/mxc4005.c:211:8-211:13: int *val, int *val2, long mask)
• drivers/iio/accel/mxc4005.c:247:9-247:13: int val, int val2, long mask)
• drivers/iio/accel/mxc6255.c:51:8-51:13: int *val, int *val2, long mask)
• drivers/iio/accel/sca3000.c:277:68-277:71: static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
• drivers/iio/accel/sca3000.c:366:7-366:15: uint8_t val)
• drivers/iio/accel/sca3000.c:605:65-605:70: static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val)
• drivers/iio/accel/sca3000.c:639:66-639:70: static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val)
• drivers/iio/accel/sca3000.c:664:60-664:65: static int sca3000_read_3db_freq(struct sca3000_state *st, int *val)
• drivers/iio/accel/sca3000.c:691:61-691:65: static int sca3000_write_3db_freq(struct sca3000_state *st, int val)
• drivers/iio/accel/sca3000.c:718:8-718:13: int *val,
• drivers/iio/accel/sca3000.c:786:9-786:13: int val, int val2, long mask)
• drivers/iio/accel/sca3000.c:878:9-878:14: int *val, int *val2)
• drivers/iio/accel/sca3000.c:930:10-930:14: int val, int val2)
• drivers/iio/accel/sca3000.c:1003:38-1003:41: static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev)
• drivers/iio/accel/sca3300.c:251:60-251:65: static int sca3300_transfer(struct sca3300_data *sca_data, int *val)
• drivers/iio/accel/sca3300.c:324:68-324:73: static int sca3300_read_reg(struct sca3300_data *sca_data, u8 reg, int *val)
• drivers/iio/accel/sca3300.c:338:69-338:73: static int sca3300_write_reg(struct sca3300_data *sca_data, u8 reg, int val)
• drivers/iio/accel/sca3300.c:385:61-385:65: static int sca3300_set_frequency(struct sca3300_data *data, int val)
• drivers/iio/accel/sca3300.c:416:9-416:13: int val, int val2, long mask)
• drivers/iio/accel/sca3300.c:447:8-447:13: int *val, int *val2, long mask)
• drivers/iio/accel/ssp_accel_sensor.c:28:45-28:50: struct iio_chan_spec const *chan, int *val,
• drivers/iio/accel/ssp_accel_sensor.c:47:45-47:49: struct iio_chan_spec const *chan, int val,
• drivers/iio/accel/st_accel_core.c:1185:36-1185:41: struct iio_chan_spec const *ch, int *val,
• drivers/iio/accel/st_accel_core.c:1214:37-1214:41: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/accel/stk8312.c:336:8-336:13: int *val, int *val2, long mask)
• drivers/iio/accel/stk8312.c:380:9-380:13: int val, int val2, long mask)
• drivers/iio/accel/stk8ba50.c:209:9-209:14: int *val, int *val2, long mask)
• drivers/iio/accel/stk8ba50.c:251:10-251:14: int val, int val2, long mask)
• drivers/iio/adc/ad4130.c:417:62-417:75: static int ad4130_reg_write(void *context, unsigned int reg, unsigned int val)
• drivers/iio/adc/ad4130.c:446:61-446:75: static int ad4130_reg_read(void *context, unsigned int reg, unsigned int *val)
• drivers/iio/adc/ad4130.c:545:46-545:59: static unsigned int ad4130_watermark_reg_val(unsigned int val)
• drivers/iio/adc/ad4130.c:839:10-839:14: int val, int val2, unsigned int *fs)
• drivers/iio/adc/ad4130.c:862:27-862:32: unsigned int fs, int *val, int *val2)
• drivers/iio/adc/ad4130.c:879:7-879:20: unsigned int val)
• drivers/iio/adc/ad4130.c:969:7-969:11: int val, int val2)
• drivers/iio/adc/ad4130.c:1002:30-1002:34: unsigned int channel, int val, int val2)
• drivers/iio/adc/ad4130.c:1030:11-1030:16: int *val)
• drivers/iio/adc/ad4130.c:1066:10-1066:15: int *val)
• drivers/iio/adc/ad4130.c:1086:7-1086:12: int *val, int *val2, long info)
• drivers/iio/adc/ad4130.c:1166:8-1166:12: int val, int val2, long info)
• drivers/iio/adc/ad4130.c:1218:65-1218:78: static int ad4130_set_fifo_watermark(struct iio_dev *indio_dev, unsigned int val)
• drivers/iio/adc/ad4130.c:1392:9-1392:22: unsigned int val)
• drivers/iio/adc/ad7091r-base.c:123:7-123:12: int *val, int *val2, long m)
• drivers/iio/adc/ad7124.c:211:29-211:33: unsigned int size, int val)
• drivers/iio/adc/ad7124.c:233:6-233:19: unsigned int val,
• drivers/iio/adc/ad7124.c:573:7-573:12: int *val, int *val2, long info)
• drivers/iio/adc/ad7124.c:631:8-631:12: int val, int val2, long info)
• drivers/iio/adc/ad7192.c:611:11-611:15: int val, int val2)
• drivers/iio/adc/ad7192.c:681:7-681:12: int *val,
• drivers/iio/adc/ad7192.c:730:8-730:12: int val,
• drivers/iio/adc/ad7266.c:132:56-132:61: static int ad7266_read_single(struct ad7266_state *st, int *val,
• drivers/iio/adc/ad7266.c:146:36-146:41: struct iio_chan_spec const *chan, int *val, int *val2, long m)
• drivers/iio/adc/ad7280a.c:190:63-190:76: static unsigned char ad7280_calc_crc8(unsigned char *crc_tab, unsigned int val)
• drivers/iio/adc/ad7280a.c:200:54-200:67: static int ad7280_check_crc(struct ad7280_state *st, unsigned int val)
• drivers/iio/adc/ad7280a.c:226:53-226:67: static int __ad7280_read32(struct ad7280_state *st, unsigned int *val)
• drivers/iio/adc/ad7280a.c:247:33-247:46: unsigned int addr, bool all, unsigned int val)
• drivers/iio/adc/ad7280a.c:690:37-690:42: enum iio_event_info info, int *val, int *val2)
• drivers/iio/adc/ad7280a.c:729:5-729:9: int val, int val2)
• drivers/iio/adc/ad7280a.c:883:7-883:12: int *val,
• drivers/iio/adc/ad7280a.c:923:8-923:12: int val, int val2, long mask)
• drivers/iio/adc/ad7291.c:204:8-204:13: int *val, int *val2)
• drivers/iio/adc/ad7291.c:229:9-229:13: int val, int val2)
• drivers/iio/adc/ad7291.c:320:7-320:12: int *val,
• drivers/iio/adc/ad7292.c:206:7-206:12: int *val, int *val2, long info)
• drivers/iio/adc/ad7298.c:179:54-179:59: static int ad7298_scan_temp(struct ad7298_state *st, int *val)
• drivers/iio/adc/ad7298.c:225:7-225:12: int *val,
• drivers/iio/adc/ad7476.c:131:7-131:12: int *val,
• drivers/iio/adc/ad7606.c:168:7-168:12: int *val,
• drivers/iio/adc/ad7606.c:228:69-228:73: static int ad7606_write_scale_hw(struct iio_dev *indio_dev, int ch, int val)
• drivers/iio/adc/ad7606.c:237:58-237:62: static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val)
• drivers/iio/adc/ad7606.c:256:8-256:12: int val,
• drivers/iio/adc/ad7606_spi.c:149:5-149:18: unsigned int val)
• drivers/iio/adc/ad7606_spi.c:162:6-162:19: unsigned int val)
• drivers/iio/adc/ad7606_spi.c:176:69-176:73: static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
• drivers/iio/adc/ad7606_spi.c:204:58-204:62: static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val)
• drivers/iio/adc/ad7606_spi.c:212:69-212:73: static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
• drivers/iio/adc/ad7606_spi.c:222:58-222:62: static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val)
• drivers/iio/adc/ad7766.c:128:36-128:41: const struct iio_chan_spec *chan, int *val, int *val2, long info)
• drivers/iio/adc/ad7768-1.c:198:5-198:18: unsigned int val)
• drivers/iio/adc/ad7768-1.c:361:7-361:12: int *val, int *val2, long info)
• drivers/iio/adc/ad7768-1.c:403:8-403:12: int val, int val2, long info)
• drivers/iio/adc/ad7780.c:107:7-107:12: int *val,
• drivers/iio/adc/ad7780.c:141:8-141:12: int val,
• drivers/iio/adc/ad7791.c:260:36-260:41: const struct iio_chan_spec *chan, int *val, int *val2, long info)
• drivers/iio/adc/ad7791.c:313:36-313:40: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/adc/ad7793.c:398:7-398:12: int *val,
• drivers/iio/adc/ad7793.c:467:11-467:15: int val,
• drivers/iio/adc/ad7887.c:146:7-146:12: int *val,
• drivers/iio/adc/ad7923.c:254:7-254:12: int *val,
• drivers/iio/adc/ad7949.c:93:69-93:73: static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
• drivers/iio/adc/ad7949.c:127:72-127:77: static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
• drivers/iio/adc/ad7949.c:210:7-210:12: int *val, int *val2, long mask)
• drivers/iio/adc/ad799x.c:138:57-138:61: static int ad799x_write_config(struct ad799x_state *st, u16 val)
• drivers/iio/adc/ad799x.c:284:7-284:12: int *val,
• drivers/iio/adc/ad799x.c:458:9-458:13: int val, int val2)
• drivers/iio/adc/ad799x.c:478:9-478:14: int *val, int *val2)
• drivers/iio/adc/ad9467.c:146:8-146:21: unsigned int val)
• drivers/iio/adc/ad9467.c:196:11-196:25: unsigned int *val, unsigned int *val2)
• drivers/iio/adc/ad9467.c:270:60-270:65: static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2)
• drivers/iio/adc/ad9467.c:294:60-294:64: static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2)
• drivers/iio/adc/ad9467.c:321:7-321:12: int *val, int *val2, long m)
• drivers/iio/adc/ad9467.c:339:8-339:12: int val, int val2, long mask)
• drivers/iio/adc/ad_sigma_delta.c:59:21-59:34: unsigned int size, unsigned int val)
• drivers/iio/adc/ad_sigma_delta.c:101:39-101:48: unsigned int reg, unsigned int size, uint8_t *val)
• drivers/iio/adc/ad_sigma_delta.c:146:39-146:53: unsigned int reg, unsigned int size, unsigned int *val)
• drivers/iio/adc/ad_sigma_delta.c:277:36-277:41: const struct iio_chan_spec *chan, int *val)
• drivers/iio/adc/adi-axi-adc.c:95:10-95:23: unsigned int val)
• drivers/iio/adc/adi-axi-adc.c:123:5-123:10: int *val, int *val2, long mask)
• drivers/iio/adc/adi-axi-adc.c:136:6-136:10: int val, int val2, long mask)
• drivers/iio/adc/aspeed_adc.c:282:11-282:16: int *val, int *val2, long mask)
• drivers/iio/adc/aspeed_adc.c:337:5-337:9: int val, int val2, long mask)
• drivers/iio/adc/at91-sama5d2_adc.c:903:63-903:68: static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
• drivers/iio/adc/at91-sama5d2_adc.c:1084:72-1084:77: static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
• drivers/iio/adc/at91-sama5d2_adc.c:1099:72-1099:77: static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
• drivers/iio/adc/at91-sama5d2_adc.c:1735:41-1735:46: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/at91-sama5d2_adc.c:1814:44-1814:49: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/at91-sama5d2_adc.c:1866:44-1866:49: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/at91-sama5d2_adc.c:1924:9-1924:14: int *val, int *val2, long mask)
• drivers/iio/adc/at91-sama5d2_adc.c:1959:10-1959:14: int val, int val2, long mask)
• drivers/iio/adc/at91-sama5d2_adc.c:2100:62-2100:75: static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
• drivers/iio/adc/at91_adc.c:707:9-707:14: int *val, int *val2, long mask)
• drivers/iio/adc/axp20x_adc.c:235:40-235:45: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/axp20x_adc.c:259:40-259:45: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/axp20x_adc.c:273:40-273:45: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/axp20x_adc.c:286:50-286:55: static int axp20x_adc_scale_voltage(int channel, int *val, int *val2)
• drivers/iio/adc/axp20x_adc.c:322:50-322:55: static int axp22x_adc_scale_voltage(int channel, int *val, int *val2)
• drivers/iio/adc/axp20x_adc.c:341:50-341:55: static int axp813_adc_scale_voltage(int channel, int *val, int *val2)
• drivers/iio/adc/axp20x_adc.c:365:50-365:55: static int axp20x_adc_scale_current(int channel, int *val, int *val2)
• drivers/iio/adc/axp20x_adc.c:389:63-389:68: static int axp20x_adc_scale(struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/axp20x_adc.c:408:63-408:68: static int axp22x_adc_scale(struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/axp20x_adc.c:428:63-428:68: static int axp813_adc_scale(struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/axp20x_adc.c:449:10-449:15: int *val)
• drivers/iio/adc/axp20x_adc.c:477:43-477:48: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/axp20x_adc.c:493:41-493:46: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/axp20x_adc.c:512:41-512:46: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/axp20x_adc.c:533:41-533:46: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/axp20x_adc.c:553:42-553:46: struct iio_chan_spec const *chan, int val, int val2,
• drivers/iio/adc/axp288_adc.c:116:36-116:41: static int axp288_adc_read_channel(int *val, unsigned long address,
• drivers/iio/adc/axp288_adc.c:162:4-162:9: int *val, int *val2, long mask)
• drivers/iio/adc/bcm_iproc_adc.c:454:6-454:11: int *val,
• drivers/iio/adc/berlin2-adc.c:205:39-205:44: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/cc10001_adc.c:67:16-67:20: u32 reg, u32 val)
• drivers/iio/adc/cc10001_adc.c:215:6-215:11: int *val, int *val2, long mask)
• drivers/iio/adc/cpcap-adc.c:849:21-849:26: int addr, int *val)
• drivers/iio/adc/cpcap-adc.c:866:6-866:11: int *val, int *val2, long mask)
• drivers/iio/adc/da9150-gpadc.c:157:25-157:30: int hw_chan, int *val)
• drivers/iio/adc/da9150-gpadc.c:190:49-190:54: static int da9150_gpadc_read_scale(int channel, int *val, int *val2)
• drivers/iio/adc/da9150-gpadc.c:207:50-207:55: static int da9150_gpadc_read_offset(int channel, int *val)
• drivers/iio/adc/da9150-gpadc.c:224:6-224:11: int *val, int *val2, long mask)
• drivers/iio/adc/dln2-adc.c:323:9-323:14: int *val,
• drivers/iio/adc/dln2-adc.c:377:10-377:14: int val,
• drivers/iio/adc/envelope-detector.c:188:11-188:16: int *val, int *val2, long mask)
• drivers/iio/adc/exynos_adc.c:536:5-536:10: int *val,
• drivers/iio/adc/fsl-imx25-gcq.c:108:7-108:12: int *val)
• drivers/iio/adc/fsl-imx25-gcq.c:141:43-141:48: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/hi8435.c:55:59-55:63: static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val)
• drivers/iio/adc/hi8435.c:61:59-61:64: static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val)
• drivers/iio/adc/hi8435.c:73:59-73:64: static int hi8435_readl(struct hi8435_priv *priv, u8 reg, u32 *val)
• drivers/iio/adc/hi8435.c:85:60-85:63: static int hi8435_writeb(struct hi8435_priv *priv, u8 reg, u8 val)
• drivers/iio/adc/hi8435.c:93:60-93:64: static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val)
• drivers/iio/adc/hi8435.c:104:7-104:12: int *val, int *val2, long mask)
• drivers/iio/adc/hi8435.c:162:8-162:13: int *val, int *val2)
• drivers/iio/adc/hi8435.c:194:9-194:13: int val, int val2)
• drivers/iio/adc/hi8435.c:413:57-413:70: static void hi8435_iio_push_event(struct iio_dev *idev, unsigned int val)
• drivers/iio/adc/hx711.c:272:5-272:10: int *val, int *val2, long mask)
• drivers/iio/adc/hx711.c:303:5-303:9: int val,
• drivers/iio/adc/imx7d_adc.c:287:4-287:9: int *val,
• drivers/iio/adc/imx8qxp-adc.c:203:5-203:10: int *val, int *val2, long mask)
• drivers/iio/adc/imx93_adc.c:235:5-235:10: int *val, int *val2, long mask)
• drivers/iio/adc/ina2xx-adc.c:182:7-182:12: int *val, int *val2, long mask)
• drivers/iio/adc/ina2xx-adc.c:288:62-288:75: static int ina226_set_average(struct ina2xx_chip_info *chip, unsigned int val,
• drivers/iio/adc/ina2xx-adc.c:479:8-479:12: int val, int val2, long mask)
• drivers/iio/adc/ina2xx-adc.c:578:62-578:75: static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val)
• drivers/iio/adc/ingenic-adc.c:171:8-171:17: uint32_t val)
• drivers/iio/adc/ingenic-adc.c:239:6-239:10: int val,
• drivers/iio/adc/ingenic-adc.c:633:8-633:13: int *val)
• drivers/iio/adc/ingenic-adc.c:688:5-688:10: int *val,
• drivers/iio/adc/intel_mrfld_adc.c:125:10-125:15: int *val, int *val2, long mask)
• drivers/iio/adc/lp8788_adc.c:49:5-49:10: int *val)
• drivers/iio/adc/lp8788_adc.c:96:4-96:9: int *val, int *val2, long mask)
• drivers/iio/adc/lpc18xx_adc.c:89:5-89:10: int *val, int *val2, long mask)
• drivers/iio/adc/lpc32xx_adc.c:61:8-61:13: int *val,
• drivers/iio/adc/ltc2471.c:47:8-47:13: int *val, int *val2, long info)
• drivers/iio/adc/ltc2485.c:37:52-37:57: static int ltc2485_read(struct ltc2485_data *data, int *val)
• drivers/iio/adc/ltc2485.c:58:8-58:13: int *val, int *val2, long mask)
• drivers/iio/adc/ltc2496.c:36:23-36:28: u8 address, int *val)
• drivers/iio/adc/ltc2497-core.c:49:79-49:84: static int ltc2497core_read(struct ltc2497core_driverdata *ddata, u8 address, int *val)
• drivers/iio/adc/ltc2497-core.c:78:8-78:13: int *val, int *val2, long mask)
• drivers/iio/adc/ltc2497.c:42:23-42:28: u8 address, int *val)
• drivers/iio/adc/max1027.c:334:10-334:15: int *val)
• drivers/iio/adc/max1027.c:380:8-380:13: int *val, int *val2, long mask)
• drivers/iio/adc/max11100.c:50:60-50:65: static int max11100_read_single(struct iio_dev *indio_dev, int *val)
• drivers/iio/adc/max11100.c:74:9-74:14: int *val, int *val2, long info)
• drivers/iio/adc/max1118.c:138:4-138:9: int *val, int *val2, long mask)
• drivers/iio/adc/max11205.c:44:9-44:14: int *val, int *val2, long mask)
• drivers/iio/adc/max11410.c:173:10-173:23: unsigned int val)
• drivers/iio/adc/max11410.c:183:9-183:14: int *val)
• drivers/iio/adc/max11410.c:455:9-455:14: int *val, int *val2, long info)
• drivers/iio/adc/max11410.c:512:10-512:14: int val, int val2, long mask)
• drivers/iio/adc/max1241.c:67:4-67:9: int *val, int *val2, long mask)
• drivers/iio/adc/max1363.c:357:9-357:14: int *val,
• drivers/iio/adc/max1363.c:420:8-420:13: int *val,
• drivers/iio/adc/max1363.c:729:58-729:63: enum iio_event_direction dir, enum iio_event_info info, int *val,
• drivers/iio/adc/max1363.c:742:58-742:62: enum iio_event_direction dir, enum iio_event_info info, int val,
• drivers/iio/adc/max77541-adc.c:31:11-31:16: int *val, int *val2)
• drivers/iio/adc/max77541-adc.c:44:10-44:15: int *val, int *val2)
• drivers/iio/adc/max77541-adc.c:88:8-88:13: int *val)
• drivers/iio/adc/max77541-adc.c:136:6-136:11: int *val, int *val2, long mask)
• drivers/iio/adc/max9611.c:290:8-290:13: int *val, int *val2, long mask)
• drivers/iio/adc/mcp320x.c:121:44-121:49: bool differential, int device_index, int *val)
• drivers/iio/adc/mcp320x.c:195:45-195:50: struct iio_chan_spec const *channel, int *val,
• drivers/iio/adc/mcp3911.c:87:54-87:59: static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
• drivers/iio/adc/mcp3911.c:103:55-103:59: static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len)
• drivers/iio/adc/mcp3911.c:115:3-115:7: u32 val, u8 len)
• drivers/iio/adc/mcp3911.c:165:45-165:50: struct iio_chan_spec const *channel, int *val,
• drivers/iio/adc/mcp3911.c:215:45-215:49: struct iio_chan_spec const *channel, int val,
• drivers/iio/adc/men_z188_adc.c:49:4-49:9: int *val,
• drivers/iio/adc/meson_saradc.c:396:63-396:67: static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
• drivers/iio/adc/meson_saradc.c:440:7-440:12: int *val)
• drivers/iio/adc/meson_saradc.c:640:9-640:14: int *val)
• drivers/iio/adc/meson_saradc.c:677:9-677:14: int *val, int *val2, long mask)
• drivers/iio/adc/mp2629_adc.c:66:4-66:9: int *val, int *val2, long mask)
• drivers/iio/adc/mt6360-adc.c:66:78-66:83: static int mt6360_adc_read_channel(struct mt6360_adc_data *mad, int channel, int *val)
• drivers/iio/adc/mt6360-adc.c:144:76-144:81: static int mt6360_adc_read_scale(struct mt6360_adc_data *mad, int channel, int *val, int *val2)
• drivers/iio/adc/mt6360-adc.c:188:77-188:82: static int mt6360_adc_read_offset(struct mt6360_adc_data *mad, int channel, int *val)
• drivers/iio/adc/mt6360-adc.c:195:11-195:16: int *val, int *val2, long mask)
• drivers/iio/adc/mt6370-adc.c:68:28-68:33: unsigned long addr, int *val)
• drivers/iio/adc/mt6370-adc.c:213:17-213:22: int chan, int *val)
• drivers/iio/adc/mt6370-adc.c:222:11-222:16: int *val, int *val2, long mask)
• drivers/iio/adc/mt6577_auxadc.c:186:7-186:12: int *val,
• drivers/iio/adc/mxs-lradc-adc.c:132:10-132:15: int *val)
• drivers/iio/adc/mxs-lradc-adc.c:200:61-200:66: static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
• drivers/iio/adc/mxs-lradc-adc.c:219:10-219:15: int *val, int *val2, long m)
• drivers/iio/adc/mxs-lradc-adc.c:271:8-271:12: int val, int val2, long m)
• drivers/iio/adc/nau7802.c:207:4-207:9: int *val)
• drivers/iio/adc/nau7802.c:245:4-245:9: int *val)
• drivers/iio/adc/nau7802.c:292:8-292:13: int *val, int *val2, long mask)
• drivers/iio/adc/nau7802.c:362:9-362:13: int val, int val2, long mask)
• drivers/iio/adc/npcm_adc.c:116:49-116:54: static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
• drivers/iio/adc/npcm_adc.c:156:43-156:48: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/palmas_gpadc.c:432:21-432:25: int adc_chan, int val)
• drivers/iio/adc/palmas_gpadc.c:462:50-462:54: static int palmas_gpadc_threshold_with_tolerance(int val, const int INL,
• drivers/iio/adc/palmas_gpadc.c:542:36-542:41: struct iio_chan_spec const *chan, int *val, int *val2, long mask)
• drivers/iio/adc/palmas_gpadc.c:705:7-705:12: int *val, int *val2)
• drivers/iio/adc/palmas_gpadc.c:738:8-738:12: int val, int val2)
• drivers/iio/adc/qcom-pm8xxx-xoadc.c:651:7-651:12: int *val, int *val2, long mask)
• drivers/iio/adc/qcom-spmi-adc5.c:168:74-168:77: static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val)
• drivers/iio/adc/qcom-spmi-adc5.c:436:39-436:44: struct iio_chan_spec const *chan, int *val, int *val2,
• drivers/iio/adc/qcom-spmi-adc5.c:467:39-467:44: struct iio_chan_spec const *chan, int *val, int *val2,
• drivers/iio/adc/qcom-spmi-adc5.c:475:39-475:44: struct iio_chan_spec const *chan, int *val, int *val2,
• drivers/iio/adc/qcom-spmi-iadc.c:311:5-311:10: int *val, int *val2, long mask)
• drivers/iio/adc/qcom-spmi-rradc.c:603:72-603:77: static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val,
• drivers/iio/adc/qcom-spmi-rradc.c:660:73-660:78: static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val)
• drivers/iio/adc/qcom-spmi-rradc.c:730:45-730:50: struct iio_chan_spec const *chan_spec, int *val,
• drivers/iio/adc/qcom-spmi-vadc.c:447:39-447:44: struct iio_chan_spec const *chan, int *val, int *val2,
• drivers/iio/adc/rcar-gyroadc.c:176:6-176:11: int *val, int *val2, long mask)
• drivers/iio/adc/rn5t618-adc.c:67:67-67:72: static int rn5t618_read_adc_reg(struct rn5t618 *rn5t618, int reg, u16 *val)
• drivers/iio/adc/rn5t618-adc.c:105:8-105:13: int *val, int *val2, long mask)
• drivers/iio/adc/rockchip_saradc.c:168:9-168:14: int *val, int *val2, long mask)
• drivers/iio/adc/rtq6056.c:156:9-156:14: int *val)
• drivers/iio/adc/rtq6056.c:179:67-179:72: static int rtq6056_adc_read_scale(struct iio_chan_spec const *ch, int *val,
• drivers/iio/adc/rtq6056.c:212:42-212:46: struct iio_chan_spec const *ch, int val)
• drivers/iio/adc/rtq6056.c:251:63-251:67: static int rtq6056_adc_set_average(struct rtq6056_priv *priv, int val)
• drivers/iio/adc/rtq6056.c:272:44-272:49: struct iio_chan_spec const *ch, int *val)
• drivers/iio/adc/rtq6056.c:291:39-291:44: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/rtq6056.c:333:40-333:44: struct iio_chan_spec const *chan, int val,
• drivers/iio/adc/rzg2l_adc.c:98:71-98:75: static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)
• drivers/iio/adc/rzg2l_adc.c:232:10-232:15: int *val, int *val2, long mask)
• drivers/iio/adc/sc27xx_adc.c:485:18-485:23: int scale, int *val)
• drivers/iio/adc/sc27xx_adc.c:647:34-647:39: int channel, int scale, int *val)
• drivers/iio/adc/sc27xx_adc.c:661:11-661:16: int *val, int *val2, long mask)
• drivers/iio/adc/sc27xx_adc.c:702:5-702:9: int val, int val2, long mask)
• drivers/iio/adc/spear_adc.c:99:62-99:66: static void spear_adc_set_status(struct spear_adc_state *st, u32 val)
• drivers/iio/adc/spear_adc.c:104:59-104:63: static void spear_adc_set_clk(struct spear_adc_state *st, u32 val)
• drivers/iio/adc/spear_adc.c:119:11-119:15: u32 val)
• drivers/iio/adc/spear_adc.c:149:10-149:15: int *val,
• drivers/iio/adc/spear_adc.c:189:11-189:15: int val,
• drivers/iio/adc/stm32-adc.c:594:62-594:66: static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
• drivers/iio/adc/stm32-adc.c:1466:10-1466:15: int *val, int *val2, long mask)
• drivers/iio/adc/stm32-adc.c:1593:63-1593:76: static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
• drivers/iio/adc/stm32-dfsdm-adc.c:784:10-784:23: unsigned int val)
• drivers/iio/adc/stm32-dfsdm-adc.c:1170:6-1170:10: int val, int val2, long mask)
• drivers/iio/adc/stm32-dfsdm-adc.c:1223:39-1223:44: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/stmpe-adc.c:62:37-62:42: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/stmpe-adc.c:97:37-97:42: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/stmpe-adc.c:135:6-135:11: int *val,
• drivers/iio/adc/sun20i-gpadc-iio.c:63:40-63:45: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/sun20i-gpadc-iio.c:111:40-111:45: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/sun4i-gpadc-iio.c:219:69-219:74: static int sun4i_gpadc_read(struct iio_dev *indio_dev, int channel, int *val,
• drivers/iio/adc/sun4i-gpadc-iio.c:262:5-262:10: int *val)
• drivers/iio/adc/sun4i-gpadc-iio.c:269:61-269:66: static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
• drivers/iio/adc/sun4i-gpadc-iio.c:287:63-287:68: static int sun4i_gpadc_temp_offset(struct iio_dev *indio_dev, int *val)
• drivers/iio/adc/sun4i-gpadc-iio.c:296:62-296:67: static int sun4i_gpadc_temp_scale(struct iio_dev *indio_dev, int *val)
• drivers/iio/adc/sun4i-gpadc-iio.c:306:39-306:44: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/ti-adc084s021.c:90:44-90:49: struct iio_chan_spec const *channel, int *val,
• drivers/iio/adc/ti-adc108s102.c:178:11-178:16: int *val, int *val2, long m)
• drivers/iio/adc/ti-adc128s052.c:60:44-60:49: struct iio_chan_spec const *channel, int *val,
• drivers/iio/adc/ti-adc161s626.c:78:42-78:47: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/ti-adc161s626.c:133:7-133:12: int *val, int *val2, long mask)
• drivers/iio/adc/ti-ads1015.c:396:65-396:70: int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
• drivers/iio/adc/ti-ads1015.c:537:42-537:47: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/ti-ads1015.c:598:43-598:47: struct iio_chan_spec const *chan, int val,
• drivers/iio/adc/ti-ads1015.c:623:58-623:63: enum iio_event_direction dir, enum iio_event_info info, int *val,
• drivers/iio/adc/ti-ads1015.c:663:58-663:62: enum iio_event_direction dir, enum iio_event_info info, int val,
• drivers/iio/adc/ti-ads1100.c:92:72-92:77: static int ads1100_get_adc_result(struct ads1100_data *data, int chan, int *val)
• drivers/iio/adc/ti-ads1100.c:126:57-126:61: static int ads1100_set_scale(struct ads1100_data *data, int val, int val2)
• drivers/iio/adc/ti-ads1100.c:216:42-216:47: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/ti-ads1100.c:255:43-255:47: struct iio_chan_spec const *chan, int val,
• drivers/iio/adc/ti-ads124s08.c:224:8-224:13: int *val, int *val2, long m)
• drivers/iio/adc/ti-ads7924.c:193:41-193:46: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/ti-ads7924.c:222:42-222:47: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/ti-ads7950.c:369:11-369:16: int *val, int *val2, long m)
• drivers/iio/adc/ti-ads8688.c:187:10-187:23: unsigned int val)
• drivers/iio/adc/ti-ads8688.c:245:8-245:13: int *val, int *val2, long m)
• drivers/iio/adc/ti-ads8688.c:292:9-292:13: int val, int val2, long mask)
• drivers/iio/adc/ti-lmp92064.c:156:43-156:48: struct iio_chan_spec const *chan, int *val,
• drivers/iio/adc/ti-tlc4541.c:125:8-125:13: int *val,
• drivers/iio/adc/ti-tsc2046.c:456:5-456:10: int *val, int *val2, long m)
• drivers/iio/adc/ti_am335x_adc.c:60:5-60:18: unsigned int val)
• drivers/iio/adc/ti_am335x_adc.c:431:40-431:45: struct iio_chan_spec const *chan, int *val, int *val2,
• drivers/iio/adc/twl4030-madc.c:177:9-177:14: int *val, int *val2, long mask)
• drivers/iio/adc/twl6030-gpadc.c:352:47-352:50: static inline int twl6030_gpadc_write(u8 reg, u8 val)
• drivers/iio/adc/twl6030-gpadc.c:357:46-357:50: static inline int twl6030_gpadc_read(u8 reg, u8 *val)
• drivers/iio/adc/twl6030-gpadc.c:488:16-488:21: int channel, int *val)
• drivers/iio/adc/twl6030-gpadc.c:517:9-517:14: int *val, int *val2, long mask)
• drivers/iio/adc/vf610_adc.c:630:43-630:48: struct iio_chan_spec const *chan, int *val)
• drivers/iio/adc/vf610_adc.c:683:4-683:9: int *val,
• drivers/iio/adc/vf610_adc.c:718:4-718:8: int val,
• drivers/iio/adc/viperboard_adc.c:51:5-51:10: int *val,
• drivers/iio/adc/xilinx-ams.c:311:60-311:64: static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val)
• drivers/iio/adc/xilinx-ams.c:679:4-679:9: int *val, int *val2, long mask)
• drivers/iio/adc/xilinx-ams.c:919:31-919:36: enum iio_event_info info, int *val, int *val2)
• drivers/iio/adc/xilinx-ams.c:940:32-940:36: enum iio_event_info info, int val, int val2)
• drivers/iio/adc/xilinx-xadc-core.c:124:2-124:11: uint32_t val)
• drivers/iio/adc/xilinx-xadc-core.c:130:2-130:12: uint32_t *val)
• drivers/iio/adc/xilinx-xadc-core.c:167:2-167:15: unsigned int val)
• drivers/iio/adc/xilinx-xadc-core.c:177:2-177:11: uint16_t val)
• drivers/iio/adc/xilinx-xadc-core.c:211:2-211:12: uint16_t *val)
• drivers/iio/adc/xilinx-xadc-core.c:470:2-470:12: uint16_t *val)
• drivers/iio/adc/xilinx-xadc-core.c:482:2-482:11: uint16_t val)
• drivers/iio/adc/xilinx-xadc-core.c:595:17-595:26: uint16_t mask, uint16_t val)
• drivers/iio/adc/xilinx-xadc-core.c:608:17-608:26: uint16_t mask, uint16_t val)
• drivers/iio/adc/xilinx-xadc-core.c:916:36-916:41: struct iio_chan_spec const *chan, int *val, int *val2, long info)
• drivers/iio/adc/xilinx-xadc-core.c:982:53-982:57: static int xadc_write_samplerate(struct xadc *xadc, int val)
• drivers/iio/adc/xilinx-xadc-core.c:1020:36-1020:40: struct iio_chan_spec const *chan, int val, int val2, long info)
• drivers/iio/adc/xilinx-xadc-events.c:161:2-161:7: int *val, int *val2)
• drivers/iio/adc/xilinx-xadc-events.c:186:2-186:6: int val, int val2)
• drivers/iio/adc/xilinx-xadc.h:93:2-93:12: uint16_t *val)
• drivers/iio/adc/xilinx-xadc.h:100:2-100:11: uint16_t val)
• drivers/iio/adc/xilinx-xadc.h:107:2-107:12: uint16_t *val)
• drivers/iio/adc/xilinx-xadc.h:118:2-118:11: uint16_t val)
• drivers/iio/addac/ad74115.c:397:8-397:21: unsigned int val, unsigned int *index)
• drivers/iio/addac/ad74115.c:418:46-418:50: static void ad74115_format_reg_write(u8 reg, u16 val, u8 *buf)
• drivers/iio/addac/ad74115.c:425:63-425:76: static int ad74115_reg_write(void *context, unsigned int reg, unsigned int val)
• drivers/iio/addac/ad74115.c:448:62-448:76: static int ad74115_reg_read(void *context, unsigned int reg, unsigned int *val)
• drivers/iio/addac/ad74115.c:560:64-560:77: static int ad74115_set_comp_debounce(struct ad74115_state *st, unsigned int val)
• drivers/iio/addac/ad74115.c:776:34-776:39: enum ad74115_adc_ch channel, int *val)
• drivers/iio/addac/ad74115.c:796:35-796:40: enum ad74115_adc_ch channel, int *val)
• drivers/iio/addac/ad74115.c:865:34-865:39: enum ad74115_adc_ch channel, int *val)
• drivers/iio/addac/ad74115.c:883:53-883:58: static int ad74115_adc_code_to_resistance(int code, int *val, int *val2)
• drivers/iio/addac/ad74115.c:895:34-895:38: enum ad74115_dac_ch channel, int val)
• drivers/iio/addac/ad74115.c:916:34-916:39: enum ad74115_dac_ch channel, int *val)
• drivers/iio/addac/ad74115.c:934:34-934:38: enum ad74115_adc_ch channel, int val)
• drivers/iio/addac/ad74115.c:953:59-953:64: static int ad74115_get_dac_rate(struct ad74115_state *st, int *val)
• drivers/iio/addac/ad74115.c:980:59-980:63: static int ad74115_set_dac_rate(struct ad74115_state *st, int val)
• drivers/iio/addac/ad74115.c:1006:6-1006:11: int *val, int *val2)
• drivers/iio/addac/ad74115.c:1034:41-1034:46: struct iio_chan_spec const *chan, int *val)
• drivers/iio/addac/ad74115.c:1052:35-1052:49: enum ad74115_adc_ch channel, unsigned int *val)
• drivers/iio/addac/ad74115.c:1070:10-1070:15: int *val, int *val2)
• drivers/iio/addac/ad74115.c:1085:6-1085:11: int *val, int *val2)
• drivers/iio/addac/ad74115.c:1108:11-1108:16: int *val, int *val2)
• drivers/iio/addac/ad74115.c:1139:7-1139:12: int *val, int *val2)
• drivers/iio/addac/ad74115.c:1163:8-1163:13: int *val, int *val2, long info)
• drivers/iio/addac/ad74115.c:1201:43-1201:47: struct iio_chan_spec const *chan, int val, int val2,
• drivers/iio/addac/ad74413r.c:165:47-165:51: static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf)
• drivers/iio/addac/ad74413r.c:172:64-172:77: static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val)
• drivers/iio/addac/ad74413r.c:194:63-194:77: static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val)
• drivers/iio/addac/ad74413r.c:280:31-280:35: unsigned int offset, int val)
• drivers/iio/addac/ad74413r.c:492:7-492:21: unsigned int *val)
• drivers/iio/addac/ad74413r.c:507:11-507:25: unsigned int *val)
• drivers/iio/addac/ad74413r.c:522:11-522:24: unsigned int val)
• drivers/iio/addac/ad74413r.c:532:29-532:34: unsigned int rej, int *val)
• drivers/iio/addac/ad74413r.c:554:21-554:35: int rate, unsigned int *val)
• drivers/iio/addac/ad74413r.c:576:29-576:34: unsigned int range, int *val)
• drivers/iio/addac/ad74413r.c:596:30-596:35: unsigned int range, int *val)
• drivers/iio/addac/ad74413r.c:614:27-614:32: unsigned int range, int *val)
• drivers/iio/addac/ad74413r.c:634:11-634:16: int *val, int *val2)
• drivers/iio/addac/ad74413r.c:643:11-643:16: int *val, int *val2)
• drivers/iio/addac/ad74413r.c:653:10-653:15: int *val, int *val2)
• drivers/iio/addac/ad74413r.c:672:33-672:38: unsigned int channel, int *val)
• drivers/iio/addac/ad74413r.c:689:32-689:37: unsigned int channel, int *val,
• drivers/iio/addac/ad74413r.c:709:32-709:37: unsigned int channel, int *val)
• drivers/iio/addac/ad74413r.c:734:28-734:33: unsigned int channel, int *val)
• drivers/iio/addac/ad74413r.c:751:28-751:32: unsigned int channel, int val)
• drivers/iio/addac/ad74413r.c:802:31-802:36: unsigned int channel, int *val)
• drivers/iio/addac/ad74413r.c:843:30-843:35: unsigned int channel, int *val)
• drivers/iio/addac/ad74413r.c:861:63-861:68: static void ad74413r_adc_to_resistance_result(int adc_result, int *val)
• drivers/iio/addac/ad74413r.c:964:9-964:14: int *val, int *val2, long info)
• drivers/iio/addac/ad74413r.c:1026:10-1026:14: int val, int val2, long info)
• drivers/iio/addac/stx104.c:172:36-172:41: struct iio_chan_spec const *chan, int *val, int *val2, long mask)
• drivers/iio/addac/stx104.c:261:36-261:40: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/afe/iio-rescale.c:23:6-23:11: int *val, int *val2)
• drivers/iio/afe/iio-rescale.c:114:7-114:12: int *val, int *val2)
• drivers/iio/afe/iio-rescale.c:148:8-148:13: int *val, int *val2, long mask)
• drivers/iio/amplifiers/ad8366.c:114:7-114:12: int *val,
• drivers/iio/amplifiers/ad8366.c:161:8-161:12: int val,
• drivers/iio/amplifiers/ada4250.c:167:8-167:13: int *val, int *val2, long info)
• drivers/iio/amplifiers/ada4250.c:205:9-205:13: int val, int val2, long info)
• drivers/iio/amplifiers/hmc425a.c:57:42-57:47: struct iio_chan_spec const *chan, int *val,
• drivers/iio/amplifiers/hmc425a.c:89:43-89:47: struct iio_chan_spec const *chan, int val,
• drivers/iio/cdc/ad7150.c:103:7-103:12: int *val,
• drivers/iio/cdc/ad7150.c:329:8-329:13: int *val, int *val2)
• drivers/iio/cdc/ad7150.c:361:9-361:13: int val, int val2)
• drivers/iio/cdc/ad7746.c:411:12-411:16: int val)
• drivers/iio/cdc/ad7746.c:429:11-429:15: int val)
• drivers/iio/cdc/ad7746.c:461:8-461:12: int val,
• drivers/iio/cdc/ad7746.c:582:11-582:16: int *val)
• drivers/iio/cdc/ad7746.c:619:7-619:12: int *val, int *val2,
• drivers/iio/chemical/ams-iaq-core.c:94:39-94:44: struct iio_chan_spec const *chan, int *val,
• drivers/iio/chemical/atlas-ezo-sensor.c:115:6-115:11: int *val, int *val2, long mask)
• drivers/iio/chemical/atlas-sensor.c:479:69-479:77: static int atlas_read_measurement(struct atlas_data *data, int reg, __be32 *val)
• drivers/iio/chemical/atlas-sensor.c:502:6-502:11: int *val, int *val2, long mask)
• drivers/iio/chemical/atlas-sensor.c:571:7-571:11: int val, int val2, long mask)
• drivers/iio/chemical/bme680_core.c:530:38-530:41: static u8 bme680_oversampling_to_reg(u8 val)
• drivers/iio/chemical/bme680_core.c:612:55-612:60: static int bme680_read_temp(struct bme680_data *data, int *val)
• drivers/iio/chemical/bme680_core.c:654:9-654:14: int *val, int *val2)
• drivers/iio/chemical/bme680_core.c:686:9-686:14: int *val, int *val2)
• drivers/iio/chemical/bme680_core.c:720:7-720:12: int *val)
• drivers/iio/chemical/bme680_core.c:780:7-780:12: int *val, int *val2, long mask)
• drivers/iio/chemical/bme680_core.c:824:8-824:12: int val, int val2, long mask)
• drivers/iio/chemical/bme680_spi.c:87:24-87:30: size_t reg_size, void *val, size_t val_size)
• drivers/iio/chemical/ccs811.c:219:7-219:12: int *val, int *val2, long mask)
• drivers/iio/chemical/pms7003.c:139:8-139:13: int *val, int *val2, long mask)
• drivers/iio/chemical/scd30_core.c:56:78-56:83: static int scd30_command_read(struct scd30_state *state, enum scd30_cmd cmd, u16 *val)
• drivers/iio/chemical/scd30_core.c:198:6-198:11: int *val, int *val2, long mask)
• drivers/iio/chemical/scd30_core.c:257:7-257:11: int val, int val2, long mask)
• drivers/iio/chemical/scd4x.c:340:38-340:43: struct iio_chan_spec const *chan, int *val,
• drivers/iio/chemical/scd4x.c:429:5-429:9: int val, int val2, long mask)
• drivers/iio/chemical/sgp30.c:335:38-335:43: struct iio_chan_spec const *chan, int *val,
• drivers/iio/chemical/sgp40.c:211:38-211:43: struct iio_chan_spec const *chan, int *val,
• drivers/iio/chemical/sgp40.c:270:38-270:42: struct iio_chan_spec const *chan, int val,
• drivers/iio/chemical/sps30.c:130:6-130:11: int *val, int *val2, long mask)
• drivers/iio/chemical/sunrise_co2.c:136:67-136:72: static int sunrise_read_word(struct sunrise_dev *sunrise, u8 reg, u16 *val)
• drivers/iio/chemical/sunrise_co2.c:156:68-156:71: static int sunrise_write_byte(struct sunrise_dev *sunrise, u8 reg, u8 val)
• drivers/iio/chemical/sunrise_co2.c:397:8-397:13: int *val, int *val2, long mask)
• drivers/iio/chemical/vz89x.c:243:6-243:11: int *val)
• drivers/iio/chemical/vz89x.c:262:40-262:45: struct iio_chan_spec const *chan, int *val,
• drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c:70:9-70:14: int *val, int *val2, long mask)
• drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c:38:6-38:11: int *val, int *val2, long mask)
• drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c:152:11-152:15: int val, int val2, long mask)
• drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c:754:6-754:11: int *val, int *val2, long mask)
• drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c:826:11-826:15: int val, int val2, long mask)
• drivers/iio/common/inv_sensors/inv_sensors_timestamp.c:22:67-22:76: static void inv_update_acc(struct inv_sensors_timestamp_acc *acc, uint32_t val)
• drivers/iio/common/scmi_sensors/scmi_iio.c:134:58-134:62: static int scmi_iio_set_odr_val(struct iio_dev *iio_dev, int val, int val2)
• drivers/iio/common/scmi_sensors/scmi_iio.c:201:44-201:48: struct iio_chan_spec const *chan, int val,
• drivers/iio/common/scmi_sensors/scmi_iio.c:250:58-250:63: static int scmi_iio_get_odr_val(struct iio_dev *iio_dev, int *val, int *val2)
• drivers/iio/common/scmi_sensors/scmi_iio.c:287:41-287:46: struct iio_chan_spec const *ch, int *val, int *val2)
• drivers/iio/common/scmi_sensors/scmi_iio.c:333:41-333:46: struct iio_chan_spec const *ch, int *val,
• drivers/iio/common/scmi_sensors/scmi_iio.c:497:44-497:48: static u64 scmi_iio_convert_interval_to_ns(u32 val)
• drivers/iio/common/st_sensors/st_sensors_core.c:528:37-528:42: struct iio_chan_spec const *ch, int *val)
• drivers/iio/dac/ad3552r.c:354:65-354:69: static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val)
• drivers/iio/dac/ad3552r.c:372:64-372:69: static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val)
• drivers/iio/dac/ad3552r.c:391:31-391:35: static u16 ad3552r_field_prep(u16 val, u16 mask)
• drivers/iio/dac/ad3552r.c:398:9-398:13: u16 val)
• drivers/iio/dac/ad3552r.c:416:5-416:9: u16 val)
• drivers/iio/dac/ad3552r.c:443:8-443:13: int *val,
• drivers/iio/dac/ad3552r.c:487:9-487:13: int val,
• drivers/iio/dac/ad5064.c:193:21-193:34: unsigned int addr, unsigned int val, unsigned int shift)
• drivers/iio/dac/ad5064.c:317:7-317:12: int *val,
• drivers/iio/dac/ad5064.c:343:36-343:40: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/dac/ad5064.c:796:55-796:68: static int ad5064_set_config(struct ad5064_state *st, unsigned int val)
• drivers/iio/dac/ad5064.c:906:21-906:34: unsigned int addr, unsigned int val)
• drivers/iio/dac/ad5064.c:971:21-971:34: unsigned int addr, unsigned int val)
• drivers/iio/dac/ad5360.c:194:39-194:52: unsigned int cmd, unsigned int addr, unsigned int val,
• drivers/iio/dac/ad5360.c:207:21-207:34: unsigned int addr, unsigned int val, unsigned int shift)
• drivers/iio/dac/ad5360.c:315:11-315:15: int val,
• drivers/iio/dac/ad5360.c:371:7-371:12: int *val,
• drivers/iio/dac/ad5380.c:174:36-174:40: struct iio_chan_spec const *chan, int val, int val2, long info)
• drivers/iio/dac/ad5380.c:203:36-203:41: struct iio_chan_spec const *chan, int *val, int *val2, long info)
• drivers/iio/dac/ad5421.c:135:20-135:33: unsigned int reg, unsigned int val)
• drivers/iio/dac/ad5421.c:145:2-145:15: unsigned int val)
• drivers/iio/dac/ad5421.c:315:36-315:41: struct iio_chan_spec const *chan, int *val, int *val2, long m)
• drivers/iio/dac/ad5421.c:357:36-357:40: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/dac/ad5421.c:442:58-442:63: enum iio_event_direction dir, enum iio_event_info info, int *val,
• drivers/iio/dac/ad5446.c:173:7-173:12: int *val,
• drivers/iio/dac/ad5446.c:193:11-193:15: int val,
• drivers/iio/dac/ad5446.c:298:50-298:59: static int ad5446_write(struct ad5446_state *st, unsigned val)
• drivers/iio/dac/ad5446.c:306:50-306:59: static int ad5660_write(struct ad5446_state *st, unsigned val)
• drivers/iio/dac/ad5446.c:528:50-528:59: static int ad5622_write(struct ad5446_state *st, unsigned val)
• drivers/iio/dac/ad5449.c:87:2-87:15: unsigned int val)
• drivers/iio/dac/ad5449.c:101:2-101:16: unsigned int *val)
• drivers/iio/dac/ad5449.c:133:36-133:41: struct iio_chan_spec const *chan, int *val, int *val2, long info)
• drivers/iio/dac/ad5449.c:171:36-171:40: struct iio_chan_spec const *chan, int val, int val2, long info)
• drivers/iio/dac/ad5504.c:68:63-68:67: static int ad5504_spi_write(struct ad5504_state *st, u8 addr, u16 val)
• drivers/iio/dac/ad5504.c:95:7-95:12: int *val,
• drivers/iio/dac/ad5504.c:121:11-121:15: int val,
• drivers/iio/dac/ad5592r-base.c:303:36-303:40: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/dac/ad5592r-base.c:377:7-377:12: int *val, int *val2, long m)
• drivers/iio/dac/ad5624r_spi.c:26:26-26:30: u8 cmd, u8 addr, u16 val, u8 shift)
• drivers/iio/dac/ad5624r_spi.c:47:7-47:12: int *val,
• drivers/iio/dac/ad5624r_spi.c:64:11-64:15: int val,
• drivers/iio/dac/ad5686-spi.c:17:25-17:29: u8 cmd, u8 addr, u16 val)
• drivers/iio/dac/ad5686.c:121:7-121:12: int *val,
• drivers/iio/dac/ad5686.c:148:8-148:12: int val,
• drivers/iio/dac/ad5696-i2c.c:46:25-46:29: u8 cmd, u8 addr, u16 val)
• drivers/iio/dac/ad5755.c:253:20-253:33: unsigned int reg, unsigned int val)
• drivers/iio/dac/ad5755.c:263:42-263:55: unsigned int channel, unsigned int reg, unsigned int val)
• drivers/iio/dac/ad5755.c:270:2-270:15: unsigned int val)
• drivers/iio/dac/ad5755.c:283:20-283:33: unsigned int reg, unsigned int val)
• drivers/iio/dac/ad5755.c:435:36-435:41: const struct iio_chan_spec *chan, int *val, int *val2, long info)
• drivers/iio/dac/ad5755.c:470:36-470:40: const struct iio_chan_spec *chan, int val, int val2, long info)
• drivers/iio/dac/ad5758.c:215:5-215:18: unsigned int val)
• drivers/iio/dac/ad5758.c:226:6-226:19: unsigned int val)
• drivers/iio/dac/ad5758.c:246:29-246:33: unsigned int size, int val)
• drivers/iio/dac/ad5758.c:520:7-520:12: int *val, int *val2, long info)
• drivers/iio/dac/ad5758.c:553:8-553:12: int val, int val2, long info)
• drivers/iio/dac/ad5761.c:117:64-117:68: static int _ad5761_spi_write(struct ad5761_state *st, u8 addr, u16 val)
• drivers/iio/dac/ad5761.c:124:65-124:69: static int ad5761_spi_write(struct iio_dev *indio_dev, u8 addr, u16 val)
• drivers/iio/dac/ad5761.c:136:63-136:68: static int _ad5761_spi_read(struct ad5761_state *st, u8 addr, u16 *val)
• drivers/iio/dac/ad5761.c:163:64-163:69: static int ad5761_spi_read(struct iio_dev *indio_dev, u8 addr, u16 *val)
• drivers/iio/dac/ad5761.c:201:7-201:12: int *val,
• drivers/iio/dac/ad5761.c:235:8-235:12: int val,
• drivers/iio/dac/ad5764.c:125:2-125:15: unsigned int val)
• drivers/iio/dac/ad5764.c:140:2-140:16: unsigned int *val)
• drivers/iio/dac/ad5764.c:185:36-185:40: struct iio_chan_spec const *chan, int val, int val2, long info)
• drivers/iio/dac/ad5764.c:222:36-222:41: struct iio_chan_spec const *chan, int *val, int *val2, long info)
• drivers/iio/dac/ad5766.c:145:63-145:68: static int __ad5766_spi_read(struct ad5766_state *st, u8 dac, int *val)
• drivers/iio/dac/ad5766.c:182:59-182:64: static int ad5766_read(struct iio_dev *indio_dev, u8 dac, int *val)
• drivers/iio/dac/ad5766.c:232:7-232:12: int *val,
• drivers/iio/dac/ad5766.c:263:8-263:12: int val,
• drivers/iio/dac/ad5770r.c:314:8-314:13: int *val, int *val2, long info)
• drivers/iio/dac/ad5770r.c:357:9-357:13: int val, int val2, long info)
• drivers/iio/dac/ad5791.c:108:63-108:67: static int ad5791_spi_write(struct ad5791_state *st, u8 addr, u32 val)
• drivers/iio/dac/ad5791.c:117:62-117:67: static int ad5791_spi_read(struct ad5791_state *st, u8 addr, u32 *val)
• drivers/iio/dac/ad5791.c:248:7-248:12: int *val,
• drivers/iio/dac/ad5791.c:319:8-319:12: int val,
• drivers/iio/dac/ad7293.c:169:9-169:14: u16 *val)
• drivers/iio/dac/ad7293.c:202:7-202:12: u16 *val)
• drivers/iio/dac/ad7293.c:214:10-214:14: u16 val)
• drivers/iio/dac/ad7293.c:236:8-236:12: u16 val)
• drivers/iio/dac/ad7293.c:248:19-248:23: u16 mask, u16 val)
• drivers/iio/dac/ad7293.c:263:17-263:21: u16 mask, u16 val)
• drivers/iio/dac/ad7293.c:478:7-478:12: int *val, int *val2, long info)
• drivers/iio/dac/ad7293.c:584:8-584:12: int val, int val2, long info)
• drivers/iio/dac/ad7303.c:54:2-54:10: uint8_t val)
• drivers/iio/dac/ad7303.c:114:36-114:41: struct iio_chan_spec const *chan, int *val, int *val2, long info)
• drivers/iio/dac/ad7303.c:141:36-141:40: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/dac/ad8801.c:40:36-40:40: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/dac/ad8801.c:62:36-62:41: struct iio_chan_spec const *chan, int *val, int *val2, long info)
• drivers/iio/dac/cio-dac.c:67:36-67:41: struct iio_chan_spec const *chan, int *val, int *val2, long mask)
• drivers/iio/dac/cio-dac.c:87:36-87:40: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/dac/dpot-dac.c:54:9-54:14: int *val, int *val2, long mask)
• drivers/iio/dac/dpot-dac.c:113:10-113:14: int val, int val2, long mask)
• drivers/iio/dac/ds4424.c:71:9-71:14: int *val, int channel)
• drivers/iio/dac/ds4424.c:89:9-89:13: int val, struct iio_chan_spec const *chan)
• drivers/iio/dac/ds4424.c:109:7-109:12: int *val, int *val2, long mask)
• drivers/iio/dac/ds4424.c:135:9-135:13: int val, int val2, long mask)
• drivers/iio/dac/lpc18xx_dac.c:50:5-50:10: int *val, int *val2, long mask)
• drivers/iio/dac/lpc18xx_dac.c:75:6-75:10: int val, int val2, long mask)
• drivers/iio/dac/ltc1660.c:49:3-49:8: int *val,
• drivers/iio/dac/ltc1660.c:78:3-78:7: int val,
• drivers/iio/dac/ltc2632.c:75:26-75:30: u8 cmd, u8 addr, u16 val, u8 shift)
• drivers/iio/dac/ltc2632.c:95:8-95:13: int *val,
• drivers/iio/dac/ltc2632.c:112:9-112:13: int val,
• drivers/iio/dac/ltc2688.c:101:8-101:14: void *val, size_t val_size)
• drivers/iio/dac/ltc2688.c:157:69-157:74: static int ltc2688_scale_get(const struct ltc2688_state *st, int c, int *val)
• drivers/iio/dac/ltc2688.c:175:70-175:75: static int ltc2688_offset_get(const struct ltc2688_state *st, int c, int *val)
• drivers/iio/dac/ltc2688.c:275:42-275:47: struct iio_chan_spec const *chan, int *val,
• drivers/iio/dac/ltc2688.c:323:43-323:47: struct iio_chan_spec const *chan, int val,
• drivers/iio/dac/m62332.c:31:56-31:59: static int m62332_set_value(struct iio_dev *indio_dev, u8 val, int channel)
• drivers/iio/dac/m62332.c:75:7-75:12: int *val,
• drivers/iio/dac/m62332.c:109:42-109:46: struct iio_chan_spec const *chan, int val, int val2,
• drivers/iio/dac/max517.c:44:2-44:7: long val, int channel)
• drivers/iio/dac/max517.c:68:7-68:12: int *val,
• drivers/iio/dac/max517.c:87:36-87:40: struct iio_chan_spec const *chan, int val, int val2, long mask)
• drivers/iio/dac/max5522.c:79:8-79:13: int *val, int *val2, long info)
• drivers/iio/dac/max5522.c:104:9-104:13: int val, int val2, long info)
• drivers/iio/dac/max5821.c:170:9-170:14: int *val, int channel)
• drivers/iio/dac/max5821.c:211:9-211:13: int val, int channel)
• drivers/iio/dac/max5821.c:239:7-239:12: int *val, int *val2, long mask)
• drivers/iio/dac/max5821.c:257:9-257:13: int val, int val2, long mask)
• drivers/iio/dac/mcp4725.c:277:57-277:61: static int mcp4725_set_value(struct iio_dev *indio_dev, int val)
• drivers/iio/dac/mcp4725.c:322:7-322:12: int *val, int *val2, long mask)
• drivers/iio/dac/mcp4725.c:349:11-349:15: int val, int val2, long mask)
• drivers/iio/dac/mcp4728.c:301:36-301:41: struct mcp4728_data *data, int *val,
• drivers/iio/dac/mcp4728.c:308:71-308:76: static void mcp4728_get_scale(int channel, struct mcp4728_data *data, int *val,
• drivers/iio/dac/mcp4728.c:327:67-327:71: static int mcp4728_find_matching_scale(struct mcp4728_data *data, int val,
• drivers/iio/dac/mcp4728.c:338:70-338:74: static int mcp4728_set_scale(int channel, struct mcp4728_data *data, int val,
• drivers/iio/dac/mcp4728.c:364:42-364:47: struct iio_chan_spec const *chan, int *val,
• drivers/iio/dac/mcp4728.c:381:43-381:47: struct iio_chan_spec const *chan, int val,
• drivers/iio/dac/mcp4922.c:52:68-52:72: static int mcp4922_spi_write(struct mcp4922_state *state, u8 addr, u32 val)
• drivers/iio/dac/mcp4922.c:63:3-63:8: int *val,
• drivers/iio/dac/mcp4922.c:84:3-84:7: int val,
• drivers/iio/dac/stm32-dac.c:113:68-113:73: static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
• drivers/iio/dac/stm32-dac.c:125:68-125:72: static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
• drivers/iio/dac/stm32-dac.c:139:10-139:15: int *val, int *val2, long mask)
• drivers/iio/dac/stm32-dac.c:157:11-157:15: int val, int val2, long mask)
• drivers/iio/dac/ti-dac082s085.c:66:59-66:63: static int ti_dac_cmd(struct ti_dac_chip *ti_dac, u8 cmd, u16 val)
• drivers/iio/dac/ti-dac082s085.c:188:7-188:12: int *val, int *val2, long mask)
• drivers/iio/dac/ti-dac082s085.c:218:8-218:12: int val, int val2, long mask)
• drivers/iio/dac/ti-dac5571.c:66:71-66:75: static int dac5571_cmd_single(struct dac5571_data *data, int channel, u16 val)
• drivers/iio/dac/ti-dac5571.c:80:69-8