Symbol: _p

function local

Defined...

• drivers/firewire/ohci.c:410:1-413:1: static char _p(u32 *s, int shift)

function parameter

Defined...

• drivers/net/dsa/mv88e6xxx/chip.c:1300:38-1300:44: struct ethtool_regs *regs, void *_p)
• drivers/net/dsa/mv88e6xxx/serdes.c:223:71-223:77: void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p)
• drivers/net/dsa/mv88e6xxx/serdes.c:492:71-492:77: void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p)
• drivers/net/ethernet/asix/ax88796c_ioctl.c:97:71-97:77: ax88796c_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *_p)
• drivers/net/ethernet/broadcom/bnx2.c:7043:66-7043:72: bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
• drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c:964:34-964:40: struct ethtool_regs *regs, void *_p)
• drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c:1403:6-1403:12: void *_p)
• drivers/net/ethernet/broadcom/tg3.c:11954:30-11954:36: struct ethtool_regs *regs, void *_p)
• net/dsa/slave.c:997:71-997:77: dsa_slave_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)

variable

Defined...

• drivers/clk/sunxi-ng/ccu_mp.c:19:2-19:19: unsigned int _m, _p;
• drivers/clk/sunxi-ng/ccu_mp.c:51:2-51:19: unsigned int _m, _p, div;
• drivers/clk/sunxi-ng/ccu_nkmp.c:37:2-37:28: unsigned long _n, _k, _m, _p;
• drivers/gpu/drm/bridge/samsung-dsim.c:558:2-558:5: u8 _p, best_p;
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1122:2-1122:2: PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1207:3-1207:3: PUSH_NVSQ(push, NV05F, 0x012c, 0);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1208:3-1208:3: PUSH_NVSQ(push, NV05F, 0x0134, head);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1209:3-1209:3: PUSH_NVSQ(push, NV05F, 0x0100, 0);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1210:3-1210:3: PUSH_NVSQ(push, NV05F, 0x0130, 0);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1122:2-1122:2: PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1207:3-1207:3: PUSH_NVSQ(push, NV05F, 0x012c, 0);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1208:3-1208:3: PUSH_NVSQ(push, NV05F, 0x0134, head);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1209:3-1209:3: PUSH_NVSQ(push, NV05F, 0x0100, 0);
• drivers/gpu/drm/nouveau/dispnv04/crtc.c:1210:3-1210:3: PUSH_NVSQ(push, NV05F, 0x0130, 0);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:44:2-44:2: PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:57:2-57:2: PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:61:2-61:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:74:2-74:2: PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:78:2-78:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:81:3-81:3: PUSH_MTHD(push, NV507C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:88:3-88:3: PUSH_MTHD(push, NV507C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:96:2-96:2: PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:98:2-98:2: PUSH_MTHD(push, NV507C, SURFACE_SET_SIZE(0),
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:127:2-127:2: PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:141:2-141:2: PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:167:2-167:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:180:2-180:2: PUSH_MTHD(push, NV507C, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:204:2-204:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:217:2-217:2: PUSH_MTHD(push, NV507C, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:44:2-44:2: PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:57:2-57:2: PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:61:2-61:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:74:2-74:2: PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:78:2-78:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:81:3-81:3: PUSH_MTHD(push, NV507C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:88:3-88:3: PUSH_MTHD(push, NV507C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:96:2-96:2: PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:98:2-98:2: PUSH_MTHD(push, NV507C, SURFACE_SET_SIZE(0),
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:127:2-127:2: PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:141:2-141:2: PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:167:2-167:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:180:2-180:2: PUSH_MTHD(push, NV507C, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:204:2-204:2: PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base507c.c:217:2-217:2: PUSH_MTHD(push, NV507C, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:37:2-37:2: PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:41:2-41:2: PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:44:3-44:3: PUSH_MTHD(push, NV827C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:51:3-51:3: PUSH_MTHD(push, NV827C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:59:2-59:2: PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:37:2-37:2: PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:41:2-41:2: PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:44:3-44:3: PUSH_MTHD(push, NV827C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:51:3-51:3: PUSH_MTHD(push, NV827C, SET_PROCESSING,
• drivers/gpu/drm/nouveau/dispnv50/base827c.c:59:2-59:2: PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:37:2-37:2: PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:42:2-42:2: PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:44:2-44:2: PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:74:2-74:2: PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:77:2-77:2: PUSH_MTHD(push, NV907C, SET_OUTPUT_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:80:2-80:2: PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:93:2-93:2: PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:102:2-102:2: PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, asyw->xlut.handle);
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:165:2-165:2: PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:179:2-179:2: PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:37:2-37:2: PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:42:2-42:2: PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:44:2-44:2: PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:74:2-74:2: PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:77:2-77:2: PUSH_MTHD(push, NV907C, SET_OUTPUT_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:80:2-80:2: PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:93:2-93:2: PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:102:2-102:2: PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, asyw->xlut.handle);
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:165:2-165:2: PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
• drivers/gpu/drm/nouveau/dispnv50/base907c.c:179:2-179:2: PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:43:3-43:3: PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:49:2-49:2: PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] |
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:90:2-90:2: PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:95:2-95:2: PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:97:2-97:2: PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:139:2-139:2: PUSH_MTHD(push, NV507D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:43:3-43:3: PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:49:2-49:2: PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] |
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:90:2-90:2: PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:95:2-95:2: PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:97:2-97:2: PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/core507d.c:139:2-139:2: PUSH_MTHD(push, NV507D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:44:3-44:3: PUSH_MTHD(push, NVC37D, WINDOW_SET_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:61:3-61:3: PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:67:2-67:2: PUSH_MTHD(push, NVC37D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS],
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:69:2-69:2: PUSH_MTHD(push, NVC37D, UPDATE, 0x00000001 |
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:74:3-74:3: PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:137:2-137:2: PUSH_MTHD(push, NVC37D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:140:3-140:3: PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:149:3-149:3: PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:44:3-44:3: PUSH_MTHD(push, NVC37D, WINDOW_SET_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:61:3-61:3: PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:67:2-67:2: PUSH_MTHD(push, NVC37D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS],
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:69:2-69:2: PUSH_MTHD(push, NVC37D, UPDATE, 0x00000001 |
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:74:3-74:3: PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:137:2-137:2: PUSH_MTHD(push, NVC37D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:140:3-140:3: PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec37d.c:149:3-149:3: PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec57d.c:39:2-39:2: PUSH_MTHD(push, NVC57D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
• drivers/gpu/drm/nouveau/dispnv50/corec57d.c:42:3-42:3: PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec57d.c:50:3-50:3: PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec57d.c:39:2-39:2: PUSH_MTHD(push, NVC57D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
• drivers/gpu/drm/nouveau/dispnv50/corec57d.c:42:3-42:3: PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/corec57d.c:50:3-50:3: PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:64:3-64:3: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:65:3-65:3: PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:67:3-67:3: PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:68:3-68:3: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:84:2-84:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:64:3-64:3: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:65:3-65:3: PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:67:3-67:3: PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:68:3-68:3: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crc907d.c:84:2-84:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:44:3-44:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:45:3-45:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:47:3-47:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:48:3-48:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:63:2-63:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:44:3-44:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:45:3-45:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:47:3-47:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:48:3-48:3: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc37d.c:63:2-63:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:40:3-40:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:41:3-41:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:43:3-43:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:44:3-44:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:40:3-40:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:41:3-41:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), crc_args);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:43:3-43:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/crcc57d.c:44:3-44:3: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
• drivers/gpu/drm/nouveau/dispnv50/dac507d.c:44:2-44:2: PUSH_MTHD(push, NV507D, DAC_SET_CONTROL(or), ctrl,
• drivers/gpu/drm/nouveau/dispnv50/dac507d.c:44:2-44:2: PUSH_MTHD(push, NV507D, DAC_SET_CONTROL(or), ctrl,
• drivers/gpu/drm/nouveau/dispnv50/dac907d.c:38:2-38:2: PUSH_MTHD(push, NV907D, DAC_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/dac907d.c:38:2-38:2: PUSH_MTHD(push, NV907D, DAC_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/disp.c:183:2-183:2: PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
• drivers/gpu/drm/nouveau/dispnv50/disp.c:183:2-183:2: PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:39:2-39:2: PUSH_MTHD(push, NV507D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:58:2-58:2: PUSH_MTHD(push, NV507D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:90:2-90:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:118:2-118:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:132:2-132:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:149:2-149:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:198:2-198:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTEXT_DMA_ISO(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:212:2-212:2: PUSH_MTHD(push, NV507D, HEAD_SET_OFFSET(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:215:2-215:2: PUSH_MTHD(push, NV507D, HEAD_SET_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:233:2-233:2: PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:288:2-288:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:303:2-303:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:356:2-356:2: PUSH_MTHD(push, NV507D, HEAD_SET_PIXEL_CLOCK(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:365:2-365:2: PUSH_MTHD(push, NV507D, HEAD_SET_OVERSCAN_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:393:2-393:2: PUSH_MTHD(push, NV507D, HEAD_SET_DEFAULT_BASE_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:410:2-410:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:416:2-416:2: PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:420:2-420:2: PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:39:2-39:2: PUSH_MTHD(push, NV507D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:58:2-58:2: PUSH_MTHD(push, NV507D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:90:2-90:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:118:2-118:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:132:2-132:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:149:2-149:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:198:2-198:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTEXT_DMA_ISO(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:212:2-212:2: PUSH_MTHD(push, NV507D, HEAD_SET_OFFSET(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:215:2-215:2: PUSH_MTHD(push, NV507D, HEAD_SET_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:233:2-233:2: PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:288:2-288:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:303:2-303:2: PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:356:2-356:2: PUSH_MTHD(push, NV507D, HEAD_SET_PIXEL_CLOCK(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:365:2-365:2: PUSH_MTHD(push, NV507D, HEAD_SET_OVERSCAN_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:393:2-393:2: PUSH_MTHD(push, NV507D, HEAD_SET_DEFAULT_BASE_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:410:2-410:2: PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:416:2-416:2: PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/head507d.c:420:2-420:2: PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:39:2-39:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:44:2-44:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:58:2-58:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:69:2-69:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:83:2-83:2: PUSH_MTHD(push, NV827D, HEAD_SET_OFFSET(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:86:2-86:2: PUSH_MTHD(push, NV827D, HEAD_SET_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:104:2-104:2: PUSH_MTHD(push, NV827D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:120:2-120:2: PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:123:2-123:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:137:2-137:2: PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:145:2-145:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:39:2-39:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:44:2-44:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:58:2-58:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:69:2-69:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:83:2-83:2: PUSH_MTHD(push, NV827D, HEAD_SET_OFFSET(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:86:2-86:2: PUSH_MTHD(push, NV827D, HEAD_SET_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:104:2-104:2: PUSH_MTHD(push, NV827D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:120:2-120:2: PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:123:2-123:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:137:2-137:2: PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head827d.c:145:2-145:2: PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:46:2-46:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:67:2-67:2: PUSH_MTHD(push, NV907D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:87:2-87:2: PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:120:2-120:2: PUSH_MTHD(push, NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:148:2-148:2: PUSH_MTHD(push, NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:162:2-162:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:167:2-167:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:181:2-181:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:191:2-191:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:205:2-205:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMAS_ISO(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:219:2-219:2: PUSH_MTHD(push, NV907D, HEAD_SET_OFFSET(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:222:2-222:2: PUSH_MTHD(push, NV907D, HEAD_SET_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:240:2-240:2: PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_POINT_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:256:2-256:2: PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:259:2-259:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:273:2-273:2: PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:281:2-281:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:333:2-333:2: PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:358:2-358:2: PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:363:2-363:2: PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:388:2-388:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:394:2-394:2: PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:398:2-398:2: PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:46:2-46:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:67:2-67:2: PUSH_MTHD(push, NV907D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:87:2-87:2: PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:120:2-120:2: PUSH_MTHD(push, NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:148:2-148:2: PUSH_MTHD(push, NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:162:2-162:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:167:2-167:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:181:2-181:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:191:2-191:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:205:2-205:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMAS_ISO(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:219:2-219:2: PUSH_MTHD(push, NV907D, HEAD_SET_OFFSET(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:222:2-222:2: PUSH_MTHD(push, NV907D, HEAD_SET_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:240:2-240:2: PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_POINT_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:256:2-256:2: PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:259:2-259:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:273:2-273:2: PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:281:2-281:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:333:2-333:2: PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:358:2-358:2: PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:363:2-363:2: PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:388:2-388:2: PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:394:2-394:2: PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/head907d.c:398:2-398:2: PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:40:2-40:2: PUSH_MTHD(push, NV917D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:73:2-73:2: PUSH_MTHD(push, NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:88:2-88:2: PUSH_MTHD(push, NV917D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:98:2-98:2: PUSH_MTHD(push, NV917D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:40:2-40:2: PUSH_MTHD(push, NV917D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:73:2-73:2: PUSH_MTHD(push, NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:88:2-88:2: PUSH_MTHD(push, NV917D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/head917d.c:98:2-98:2: PUSH_MTHD(push, NV917D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:55:2-55:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:74:2-74:2: PUSH_MTHD(push, NVC37D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:95:2-95:2: PUSH_MTHD(push, NVC37D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:114:2-114:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:118:2-118:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:132:2-132:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:148:2-148:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:149:2-149:2: PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:171:2-171:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:185:2-185:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:220:2-220:2: PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:237:2-237:2: PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:238:2-238:2: PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:240:2-240:2: PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:243:2-243:2: PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:247:2-247:2: PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:264:2-264:2: PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:268:2-268:2: PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:55:2-55:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:74:2-74:2: PUSH_MTHD(push, NVC37D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:95:2-95:2: PUSH_MTHD(push, NVC37D, HEAD_SET_DITHER_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:114:2-114:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:118:2-118:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:132:2-132:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:148:2-148:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:149:2-149:2: PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:171:2-171:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:185:2-185:2: PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:220:2-220:2: PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:237:2-237:2: PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:238:2-238:2: PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace);
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:240:2-240:2: PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:243:2-243:2: PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:247:2-247:2: PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:264:2-264:2: PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_IN(i),
• drivers/gpu/drm/nouveau/dispnv50/headc37d.c:268:2-268:2: PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:55:2-55:2: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:76:2-76:2: PUSH_MTHD(push, NVC57D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:93:2-93:2: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_OLUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:107:2-107:2: PUSH_MTHD(push, NVC57D, HEAD_SET_OLUT_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:199:2-199:2: PUSH_MTHD(push, NVC57D, HEAD_SET_RASTER_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:216:2-216:2: PUSH_NVSQ(push, NVC57D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:217:2-217:2: PUSH_NVSQ(push, NVC57D, 0x2008 + (i * 0x400), m->interlace);
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:219:2-219:2: PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:222:2-222:2: PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:226:2-226:2: PUSH_MTHD(push, NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:55:2-55:2: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:76:2-76:2: PUSH_MTHD(push, NVC57D, HEAD_SET_PROCAMP(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:93:2-93:2: PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_OLUT(i), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:107:2-107:2: PUSH_MTHD(push, NVC57D, HEAD_SET_OLUT_CONTROL(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:199:2-199:2: PUSH_MTHD(push, NVC57D, HEAD_SET_RASTER_SIZE(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:216:2-216:2: PUSH_NVSQ(push, NVC57D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:217:2-217:2: PUSH_NVSQ(push, NVC57D, 0x2008 + (i * 0x400), m->interlace);
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:219:2-219:2: PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:222:2-222:2: PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
• drivers/gpu/drm/nouveau/dispnv50/headc57d.c:226:2-226:2: PUSH_MTHD(push, NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:42:2-42:2: PUSH_MTHD(push, NV507E, SET_POINT_IN,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:64:2-64:2: PUSH_MTHD(push, NV507E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:68:2-68:2: PUSH_MTHD(push, NV507E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:70:2-70:2: PUSH_MTHD(push, NV507E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:73:2-73:2: PUSH_MTHD(push, NV507E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:75:2-75:2: PUSH_MTHD(push, NV507E, SURFACE_SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:42:2-42:2: PUSH_MTHD(push, NV507E, SET_POINT_IN,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:64:2-64:2: PUSH_MTHD(push, NV507E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:68:2-68:2: PUSH_MTHD(push, NV507E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:70:2-70:2: PUSH_MTHD(push, NV507E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:73:2-73:2: PUSH_MTHD(push, NV507E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/ovly507e.c:75:2-75:2: PUSH_MTHD(push, NV507E, SURFACE_SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:41:2-41:2: PUSH_MTHD(push, NV827E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:45:2-45:2: PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:47:2-47:2: PUSH_MTHD(push, NV827E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:50:2-50:2: PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:52:2-52:2: PUSH_MTHD(push, NV827E, SURFACE_SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:41:2-41:2: PUSH_MTHD(push, NV827E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:45:2-45:2: PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:47:2-47:2: PUSH_MTHD(push, NV827E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:50:2-50:2: PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/ovly827e.c:52:2-52:2: PUSH_MTHD(push, NV827E, SURFACE_SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:38:2-38:2: PUSH_MTHD(push, NV907E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:42:2-42:2: PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:44:2-44:2: PUSH_MTHD(push, NV907E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:47:2-47:2: PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:49:2-49:2: PUSH_MTHD(push, NV907E, SURFACE_SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:38:2-38:2: PUSH_MTHD(push, NV907E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:42:2-42:2: PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:44:2-44:2: PUSH_MTHD(push, NV907E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:47:2-47:2: PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/ovly907e.c:49:2-49:2: PUSH_MTHD(push, NV907E, SURFACE_SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/pior507d.c:45:2-45:2: PUSH_MTHD(push, NV507D, PIOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/pior507d.c:45:2-45:2: PUSH_MTHD(push, NV507D, PIOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/sor507d.c:45:2-45:2: PUSH_MTHD(push, NV507D, SOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/sor507d.c:45:2-45:2: PUSH_MTHD(push, NV507D, SOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/sor907d.c:41:2-41:2: PUSH_MTHD(push, NV907D, SOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/sor907d.c:41:2-41:2: PUSH_MTHD(push, NV907D, SOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/sorc37d.c:38:2-38:2: PUSH_MTHD(push, NVC37D, SOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/sorc37d.c:38:2-38:2: PUSH_MTHD(push, NVC37D, SOR_SET_CONTROL(or), ctrl);
• drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c:40:2-40:2: PUSH_MTHD(push, NVC37B, UPDATE, 0x00000001 |
• drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c:55:2-55:2: PUSH_MTHD(push, NVC37B, SET_POINT_OUT(0),
• drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c:40:2-40:2: PUSH_MTHD(push, NVC37B, UPDATE, 0x00000001 |
• drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c:55:2-55:2: PUSH_MTHD(push, NVC37B, SET_POINT_OUT(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:48:2-48:2: PUSH_MTHD(push, NVC37E, SET_CSC_RED2RED, asyw->csc.matrix, 12);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:61:2-61:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_INPUT_LUT, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:74:2-74:2: PUSH_MTHD(push, NVC37E, SET_CONTROL_INPUT_LUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:103:2-103:2: PUSH_MTHD(push, NVC37E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:148:2-148:2: PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:152:2-152:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:165:2-165:2: PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:170:2-170:2: PUSH_MTHD(push, NVC37E, SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:192:2-192:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:193:2-193:2: PUSH_MTHD(push, NVC37E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:195:2-195:2: PUSH_MTHD(push, NVC37E, SET_POINT_IN(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:199:2-199:2: PUSH_MTHD(push, NVC37E, SET_SIZE_IN,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:203:2-203:2: PUSH_MTHD(push, NVC37E, SET_SIZE_OUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:218:2-218:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:231:2-231:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, asyw->ntfy.handle,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:248:2-248:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:261:2-261:2: PUSH_MTHD(push, NVC37E, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:277:2-277:2: PUSH_MTHD(push, NVC37E, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS] << 1 |
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:281:2-281:2: PUSH_MTHD(push, NVC37E, UPDATE, 0x00000001 |
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:48:2-48:2: PUSH_MTHD(push, NVC37E, SET_CSC_RED2RED, asyw->csc.matrix, 12);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:61:2-61:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_INPUT_LUT, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:74:2-74:2: PUSH_MTHD(push, NVC37E, SET_CONTROL_INPUT_LUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:103:2-103:2: PUSH_MTHD(push, NVC37E, SET_COMPOSITION_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:148:2-148:2: PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:152:2-152:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:165:2-165:2: PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:170:2-170:2: PUSH_MTHD(push, NVC37E, SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:192:2-192:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:193:2-193:2: PUSH_MTHD(push, NVC37E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:195:2-195:2: PUSH_MTHD(push, NVC37E, SET_POINT_IN(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:199:2-199:2: PUSH_MTHD(push, NVC37E, SET_SIZE_IN,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:203:2-203:2: PUSH_MTHD(push, NVC37E, SET_SIZE_OUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:218:2-218:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:231:2-231:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, asyw->ntfy.handle,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:248:2-248:2: PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:261:2-261:2: PUSH_MTHD(push, NVC37E, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:277:2-277:2: PUSH_MTHD(push, NVC37E, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS] << 1 |
• drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c:281:2-281:2: PUSH_MTHD(push, NVC37E, UPDATE, 0x00000001 |
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:41:2-41:2: PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:46:2-46:2: PUSH_MTHD(push, NVC57E, SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:64:2-64:2: PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:65:2-65:2: PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:67:2-67:2: PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:71:2-71:2: PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:75:2-75:2: PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:95:2-95:2: PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, identity, ARRAY_SIZE(identity));
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:108:2-108:2: PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, asyw->csc.matrix, 12);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:121:2-121:2: PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ILUT, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:134:2-134:2: PUSH_MTHD(push, NVC57E, SET_ILUT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:41:2-41:2: PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:46:2-46:2: PUSH_MTHD(push, NVC57E, SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:64:2-64:2: PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:65:2-65:2: PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:67:2-67:2: PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:71:2-71:2: PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:75:2-75:2: PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:95:2-95:2: PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, identity, ARRAY_SIZE(identity));
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:108:2-108:2: PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, asyw->csc.matrix, 12);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:121:2-121:2: PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ILUT, 0x00000000);
• drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c:134:2-134:2: PUSH_MTHD(push, NVC57E, SET_ILUT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:38:2-38:2: PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:43:2-43:2: PUSH_MTHD(push, NVC57E, SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:60:2-60:2: PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:61:2-61:2: PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:63:2-63:2: PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:67:2-67:2: PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:71:2-71:2: PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:38:2-38:2: PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:43:2-43:2: PUSH_MTHD(push, NVC57E, SET_SIZE,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:60:2-60:2: PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:61:2-61:2: PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:63:2-63:2: PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:67:2-67:2: PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
• drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c:71:2-71:2: PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:62:2-62:2: PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma,
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:73:3-73:3: PUSH_MTHD(push, NV039, OFFSET_IN, src_offset,
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:86:3-86:3: PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000);
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:106:2-106:2: PUSH_MTHD(push, NV039, SET_OBJECT, handle);
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:107:2-107:2: PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_NOTIFIES, chan->drm->ntfy.handle);
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:62:2-62:2: PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma,
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:73:3-73:3: PUSH_MTHD(push, NV039, OFFSET_IN, src_offset,
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:86:3-86:3: PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000);
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:106:2-106:2: PUSH_MTHD(push, NV039, SET_OBJECT, handle);
• drivers/gpu/drm/nouveau/nouveau_bo0039.c:107:2-107:2: PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_NOTIFIES, chan->drm->ntfy.handle);
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:63:4-63:4: PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:80:4-80:4: PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:85:4-85:4: PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:102:4-102:4: PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:106:3-106:3: PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:112:3-112:3: PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset),
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:126:3-126:3: PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000);
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:146:2-146:2: PUSH_MTHD(push, NV5039, SET_OBJECT, handle);
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:147:2-147:2: PUSH_MTHD(push, NV5039, SET_CONTEXT_DMA_NOTIFY, chan->drm->ntfy.handle,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:63:4-63:4: PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:80:4-80:4: PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:85:4-85:4: PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:102:4-102:4: PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:106:3-106:3: PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:112:3-112:3: PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset),
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:126:3-126:3: PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000);
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:146:2-146:2: PUSH_MTHD(push, NV5039, SET_OBJECT, handle);
• drivers/gpu/drm/nouveau/nouveau_bo5039.c:147:2-147:2: PUSH_MTHD(push, NV5039, SET_CONTEXT_DMA_NOTIFY, chan->drm->ntfy.handle,
• drivers/gpu/drm/nouveau/nouveau_bo74c1.c:47:2-47:2: PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->size,
• drivers/gpu/drm/nouveau/nouveau_bo74c1.c:47:2-47:2: PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->size,
• drivers/gpu/drm/nouveau/nouveau_bo85b5.c:58:3-58:3: PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset),
• drivers/gpu/drm/nouveau/nouveau_bo85b5.c:66:3-66:3: PUSH_NVSQ(push, NV85B5, 0x0300, 0x00000110);
• drivers/gpu/drm/nouveau/nouveau_bo85b5.c:58:3-58:3: PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset),
• drivers/gpu/drm/nouveau/nouveau_bo85b5.c:66:3-66:3: PUSH_NVSQ(push, NV85B5, 0x0300, 0x00000110);
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:56:3-56:3: PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER,
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:61:3-61:3: PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:70:3-70:3: PUSH_MTHD(push, NV9039, LAUNCH_DMA,
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:96:2-96:2: PUSH_MTHD(push, NV9039, SET_OBJECT, handle);
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:56:3-56:3: PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER,
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:61:3-61:3: PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:70:3-70:3: PUSH_MTHD(push, NV9039, LAUNCH_DMA,
• drivers/gpu/drm/nouveau/nouveau_bo9039.c:96:2-96:2: PUSH_MTHD(push, NV9039, SET_OBJECT, handle);
• drivers/gpu/drm/nouveau/nouveau_bo90b5.c:51:3-51:3: PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset),
• drivers/gpu/drm/nouveau/nouveau_bo90b5.c:59:3-59:3: PUSH_NVIM(push, NV90B5, 0x0300, 0x0110);
• drivers/gpu/drm/nouveau/nouveau_bo90b5.c:51:3-51:3: PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset),
• drivers/gpu/drm/nouveau/nouveau_bo90b5.c:59:3-59:3: PUSH_NVIM(push, NV90B5, 0x0300, 0x0110);
• drivers/gpu/drm/nouveau/nouveau_boa0b5.c:49:2-49:2: PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_boa0b5.c:63:2-63:2: PUSH_IMMD(push, NVA0B5, LAUNCH_DMA,
• drivers/gpu/drm/nouveau/nouveau_boa0b5.c:88:2-88:2: PUSH_NVSQ(push, NVA0B5, 0x0000, handle & 0x0000ffff);
• drivers/gpu/drm/nouveau/nouveau_boa0b5.c:49:2-49:2: PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_boa0b5.c:63:2-63:2: PUSH_IMMD(push, NVA0B5, LAUNCH_DMA,
• drivers/gpu/drm/nouveau/nouveau_boa0b5.c:88:2-88:2: PUSH_NVSQ(push, NVA0B5, 0x0000, handle & 0x0000ffff);
• drivers/gpu/drm/nouveau/nouveau_chan.c:473:3-473:3: PUSH_DATA(chan->chan.push, 0x00000000);
• drivers/gpu/drm/nouveau/nouveau_chan.c:487:3-487:3: PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
• drivers/gpu/drm/nouveau/nouveau_chan.c:473:3-473:3: PUSH_DATA(chan->chan.push, 0x00000000);
• drivers/gpu/drm/nouveau/nouveau_chan.c:487:3-487:3: PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
• drivers/gpu/drm/nouveau/nouveau_dmem.c:457:4-457:4: PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:461:4-461:4: PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:474:4-474:4: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:478:4-478:4: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:488:2-488:2: PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:502:2-502:2: PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
• drivers/gpu/drm/nouveau/nouveau_dmem.c:529:3-529:3: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:533:3-533:3: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:542:2-542:2: PUSH_MTHD(push, NVA0B5, SET_REMAP_CONST_A, 0,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:551:2-551:2: PUSH_MTHD(push, NVA0B5, OFFSET_OUT_UPPER,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:556:2-556:2: PUSH_MTHD(push, NVA0B5, LINE_LENGTH_IN, length >> 3);
• drivers/gpu/drm/nouveau/nouveau_dmem.c:558:2-558:2: PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
• drivers/gpu/drm/nouveau/nouveau_dmem.c:457:4-457:4: PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:461:4-461:4: PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:474:4-474:4: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:478:4-478:4: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:488:2-488:2: PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:502:2-502:2: PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
• drivers/gpu/drm/nouveau/nouveau_dmem.c:529:3-529:3: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:533:3-533:3: PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:542:2-542:2: PUSH_MTHD(push, NVA0B5, SET_REMAP_CONST_A, 0,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:551:2-551:2: PUSH_MTHD(push, NVA0B5, OFFSET_OUT_UPPER,
• drivers/gpu/drm/nouveau/nouveau_dmem.c:556:2-556:2: PUSH_MTHD(push, NVA0B5, LINE_LENGTH_IN, length >> 3);
• drivers/gpu/drm/nouveau/nouveau_dmem.c:558:2-558:2: PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
• drivers/gpu/drm/nouveau/nouveau_drm.c:401:6-401:6: PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle);
• drivers/gpu/drm/nouveau/nouveau_drm.c:402:6-402:6: PUSH_NVSQ(push, NV09F, 0x0120, 0,
• drivers/gpu/drm/nouveau/nouveau_drm.c:406:5-406:5: PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
• drivers/gpu/drm/nouveau/nouveau_drm.c:401:6-401:6: PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle);
• drivers/gpu/drm/nouveau/nouveau_drm.c:402:6-402:6: PUSH_NVSQ(push, NV09F, 0x0120, 0,
• drivers/gpu/drm/nouveau/nouveau_drm.c:406:5-406:5: PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
• drivers/gpu/drm/nouveau/nouveau_gem.c:877:4-877:4: PUSH_CALL(chan->chan.push, nvbo->offset + push[i].offset);
• drivers/gpu/drm/nouveau/nouveau_gem.c:878:4-878:4: PUSH_DATA(chan->chan.push, 0);
• drivers/gpu/drm/nouveau/nouveau_gem.c:910:4-910:4: PUSH_JUMP(chan->chan.push, nvbo->offset + push[i].offset);
• drivers/gpu/drm/nouveau/nouveau_gem.c:911:4-911:4: PUSH_DATA(chan->chan.push, 0);
• drivers/gpu/drm/nouveau/nouveau_gem.c:913:5-913:5: PUSH_DATA(chan->chan.push, 0);
• drivers/gpu/drm/nouveau/nouveau_gem.c:877:4-877:4: PUSH_CALL(chan->chan.push, nvbo->offset + push[i].offset);
• drivers/gpu/drm/nouveau/nouveau_gem.c:878:4-878:4: PUSH_DATA(chan->chan.push, 0);
• drivers/gpu/drm/nouveau/nouveau_gem.c:910:4-910:4: PUSH_JUMP(chan->chan.push, nvbo->offset + push[i].offset);
• drivers/gpu/drm/nouveau/nouveau_gem.c:911:4-911:4: PUSH_DATA(chan->chan.push, 0);
• drivers/gpu/drm/nouveau/nouveau_gem.c:913:5-913:5: PUSH_DATA(chan->chan.push, 0);
• drivers/gpu/drm/nouveau/nv04_fence.c:45:3-45:3: PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno);
• drivers/gpu/drm/nouveau/nv04_fence.c:45:3-45:3: PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno);
• drivers/gpu/drm/nouveau/nv10_fence.c:38:3-38:3: PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno);
• drivers/gpu/drm/nouveau/nv10_fence.c:38:3-38:3: PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno);
• drivers/gpu/drm/nouveau/nv17_fence.c:57:3-57:3: PUSH_MTHD(ppush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
• drivers/gpu/drm/nouveau/nv17_fence.c:65:3-65:3: PUSH_MTHD(npush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
• drivers/gpu/drm/nouveau/nv17_fence.c:57:3-57:3: PUSH_MTHD(ppush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
• drivers/gpu/drm/nouveau/nv17_fence.c:65:3-65:3: PUSH_MTHD(npush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
• drivers/gpu/drm/nouveau/nv84_fence.c:41:3-41:3: PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
• drivers/gpu/drm/nouveau/nv84_fence.c:43:3-43:3: PUSH_MTHD(push, NV826F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nv84_fence.c:64:3-64:3: PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
• drivers/gpu/drm/nouveau/nv84_fence.c:66:3-66:3: PUSH_MTHD(push, NV826F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nv84_fence.c:41:3-41:3: PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
• drivers/gpu/drm/nouveau/nv84_fence.c:43:3-43:3: PUSH_MTHD(push, NV826F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nv84_fence.c:64:3-64:3: PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
• drivers/gpu/drm/nouveau/nv84_fence.c:66:3-66:3: PUSH_MTHD(push, NV826F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nvc0_fence.c:40:3-40:3: PUSH_MTHD(push, NV906F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nvc0_fence.c:63:3-63:3: PUSH_MTHD(push, NV906F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nvc0_fence.c:40:3-40:3: PUSH_MTHD(push, NV906F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nvc0_fence.c:63:3-63:3: PUSH_MTHD(push, NV906F, SEMAPHOREA,
• drivers/gpu/drm/nouveau/nvif/conn.c:44:2-44:2: NVIF_DEBUG(&conn->object, "[NEW EVENT:HPD types:%02x]", types);
• drivers/gpu/drm/nouveau/nvif/conn.c:57:2-57:2: NVIF_ERRON(ret, &conn->object, "[HPD_STATUS] support:%d present:%d",
• drivers/gpu/drm/nouveau/nvif/conn.c:79:2-79:2: NVIF_ERRON(ret, &disp->object, "[NEW conn id:%d]", id);
• drivers/gpu/drm/nouveau/nvif/disp.c:63:3-63:3: NVIF_ERRON(cid, &device->object, "[NEW disp%04x] not supported", oclass);
• drivers/gpu/drm/nouveau/nvif/disp.c:71:2-71:2: NVIF_ERRON(ret, &device->object, "[NEW disp%04x]", disps[cid].oclass);
• drivers/gpu/drm/nouveau/nvif/disp.c:75:2-75:2: NVIF_DEBUG(&disp->object, "[NEW] conn_mask:%08x outp_mask:%08x head_mask:%08x",
• drivers/gpu/drm/nouveau/nvif/event.c:33:3-33:3: NVIF_ERRON(ret, &event->object, "[BLOCK]");
• drivers/gpu/drm/nouveau/nvif/event.c:44:3-44:3: NVIF_ERRON(ret, &event->object, "[ALLOW]");
• drivers/gpu/drm/nouveau/nvif/event.c:74:2-74:2: NVIF_ERRON(ret && warn, parent, "[NEW EVENT wait:%d size:%zd]",
• drivers/gpu/drm/nouveau/nvif/head.c:35:2-35:2: NVIF_ERRON(ret, &head->object, "[NEW EVENT:VBLANK]");
• drivers/gpu/drm/nouveau/nvif/head.c:56:2-56:2: NVIF_ERRON(ret, &disp->object, "[NEW head id:%d]", args.id);
• drivers/gpu/drm/nouveau/nvif/outp.c:43:2-43:2: NVIF_ERRON(ret, &outp->object,
• drivers/gpu/drm/nouveau/nvif/outp.c:53:2-53:2: NVIF_ERRON(ret, &outp->object, "[DP_RETRAIN]");
• drivers/gpu/drm/nouveau/nvif/outp.c:67:2-67:2: NVIF_ERRON(ret, &outp->object, "[DP_AUX_PWR state:%d]", args.state);
• drivers/gpu/drm/nouveau/nvif/outp.c:88:2-88:2: NVIF_ERRON(ret, &outp->object, "[HDA_ELD head:%d size:%d]", head, size);
• drivers/gpu/drm/nouveau/nvif/outp.c:100:2-100:2: NVIF_ERRON(ret, &outp->object, "[INFOFRAME type:%d size:%d]", type, size);
• drivers/gpu/drm/nouveau/nvif/outp.c:108:2-108:2: NVIF_ERRON(ret, &outp->object, "[RELEASE]");
• drivers/gpu/drm/nouveau/nvif/outp.c:143:2-143:2: NVIF_ERRON(ret, &outp->object,
• drivers/gpu/drm/nouveau/nvif/outp.c:159:2-159:2: NVIF_ERRON(ret, &outp->object,
• drivers/gpu/drm/nouveau/nvif/outp.c:180:2-180:2: NVIF_ERRON(ret, &outp->object,
• drivers/gpu/drm/nouveau/nvif/outp.c:195:2-195:2: NVIF_ERRON(ret, &outp->object, "[ACQUIRE proto:RGB_CRT] or:%d", args.or);
• drivers/gpu/drm/nouveau/nvif/outp.c:209:2-209:2: NVIF_ERRON(ret, &outp->object, "[LOAD_DETECT data:%08x] load:%02x", args.data, args.load);
• drivers/gpu/drm/nouveau/nvif/outp.c:230:2-230:2: NVIF_ERRON(ret, &disp->object, "[NEW outp id:%d]", id);
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.c:63:9-63:9: ectx = nvkm_list_find(ectx, &cgrp->ectxs, head, ectx->engn == engn);
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.c:127:9-127:9: vctx = nvkm_list_find(vctx, &cgrp->vctxs, head,
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c:103:9-103:9: cctx = nvkm_list_find(cctx, &chan->cctxs, head,
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c:346:3-346:3: nvkm_runl_foreach_engn_cond(engn, runl, stat & BIT(engn->id)) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c:472:2-472:2: nvkm_list_foreach(tdev, &device->top->device, head, tdev->runlist == runl->addr) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c:576:2-576:2: nvkm_list_foreach(tdev, &device->top->device, head, tdev->runlist >= 0) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c:548:10-548:10: engn = nvkm_runl_find_engn(engn, runl, engn->fault == info->engine);
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c:628:3-628:3: nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id)) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c:633:5-633:5: nvkm_runl_foreach_engn_cond(engn2, runl, engn2->func->cxid) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c:653:3-653:3: nvkm_runl_foreach_engn_cond(engn, runl, engn->func->chsw) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c:740:2-740:2: nvkm_runq_foreach_cond(runq, fifo, mask & BIT(runq->id)) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c:646:2-646:2: nvkm_runl_foreach_cond(runl, fifo, mask & BIT(runl->id)) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c:764:2-764:2: nvkm_list_foreach(tdev, &device->top->device, head, tdev->runlist >= 0) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c:771:4-771:4: nvkm_runq_foreach_cond(runq, fifo, gk104_runq_runm(runq) & BIT(runl->id)) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c:462:3-462:3: nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id))
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.c:101:2-101:2: nvkm_runl_foreach_engn_cond(engn, runl, engn->func->cxid) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c:177:3-177:3: nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id)) {
• drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c:164:9-164:9: engn = nvkm_runl_find_engn(engn, cgrp->runl, engn->engine == oclass->engine);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c:193:4-193:4: nvkm_fo64(pt->memory, 0, 0, size >> 3);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c:94:2-94:2: VMM_FO064(pt, vmm, ptei * 8, 0ULL, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c:338:2-338:2: nvkm_fo64(inst, 0x0200, 0x00000000, 2);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c:29:2-29:2: VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(1) /* PRIV. */, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c:32:2-32:2: VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(32) /* VOL. */, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c:57:2-57:2: VMM_FO064(pt, vmm, pdei * 8, BIT_ULL(35) /* VOL_BIG. */, pdes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c:166:2-166:2: VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(3) /* VOL. */, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c:186:2-186:2: VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(5) /* PRIV. */, ptes);
• drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c:94:2-94:2: VMM_FO064(pt, vmm, ptei * 8, 0ULL, ptes);
• fs/afs/flock.c:92:2-92:24: struct file_lock *p, *_p;
• fs/afs/flock.c:113:2-113:24: struct file_lock *p, *_p, *next = NULL;
• kernel/kprobes.c:983:2-983:17: struct kprobe *_p;
• kernel/kprobes.c:1000:2-1000:17: struct kprobe *_p;
• lib/crc64.c:55:2-55:28: const unsigned char *_p = p;
• lib/crc64.c:75:2-75:28: const unsigned char *_p = p;
• net/rxrpc/conn_object.c:383:2-383:34: struct rxrpc_connection *conn, *_p;
• net/rxrpc/conn_object.c:462:2-462:34: struct rxrpc_connection *conn, *_p;
• net/tipc/name_distr.c:238:2-238:22: struct publication *_p;
• net/tipc/name_table.c:336:2-336:22: struct publication *_p;
• security/keys/proc.c:155:2-155:23: struct rb_node *_p = v;
• security/keys/proc.c:277:2-277:18: struct rb_node *_p;
• security/keys/proc.c:305:2-305:23: struct rb_node *_p = v;
• virt/kvm/eventfd.c:814:2-814:21: struct _ioeventfd *_p;