Symbol: PLL

macro public

Defined...

• drivers/clk/mediatek/clk-mt2701.c:913:9-929:2: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
• drivers/clk/mediatek/clk-mt2712-apmixedsys.c:44:9-50:20: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/mediatek/clk-mt6765.c:695:9-702:30: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/mediatek/clk-mt6779.c:1172:9-1181:22: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
• drivers/clk/mediatek/clk-mt6795-apmixedsys.c:26:9-44:2: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/mediatek/clk-mt6797.c:613:9-618:8: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/mediatek/clk-mt7622-apmixedsys.c:41:9-46:19: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/mediatek/clk-mt7629.c:44:9-49:17: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/mediatek/clk-mt7981-apmixed.c:38:9-42:13: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
• drivers/clk/mediatek/clk-mt7986-apmixed.c:36:9-40:13: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
• drivers/clk/mediatek/clk-mt8135-apmixedsys.c:20:9-35:2: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
• drivers/clk/mediatek/clk-mt8167-apmixedsys.c:42:9-47:8: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/mediatek/clk-mt8173-apmixedsys.c:44:9-49:8: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/mediatek/clk-mt8183-apmixedsys.c:81:9-90:22: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
• drivers/clk/mediatek/clk-mt8186-apmixedsys.c:19:9-44:2: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
• drivers/clk/mediatek/clk-mt8188-apmixedsys.c:32:9-58:2: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
• drivers/clk/mediatek/clk-mt8192-apmixedsys.c:35:9-61:2: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
• drivers/clk/mediatek/clk-mt8195-apmixedsys.c:33:9-59:2: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
• drivers/clk/mediatek/clk-mt8195-apusys_pll.c:28:9-50:2: #define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \
• drivers/clk/mediatek/clk-mt8365-apmixedsys.c:45:9-53:16: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/mediatek/clk-mt8516-apmixedsys.c:43:9-48:8: #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
• drivers/clk/pistachio/clk.h:119:9-128:2: #define PLL(_id, _name, _pname, _type, _reg, _rates) \
• drivers/clk/samsung/clk.h:271:9-273:21: #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
• drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.h:104:9-104:15: #define PLL 0x2 /* main chip pll */