Symbol: BASE

macro public

Defined...

• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:51:9-51:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:47:9-47:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:56:9-56:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c:51:9-51:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c:86:9-86:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c:133:9-134:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c:105:9-106:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c:129:9-129:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c:249:9-249:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c:99:9-99:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c:113:9-113:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c:112:9-112:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c:171:9-171:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c:149:9-149:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c:125:9-125:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c:141:9-141:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c:159:9-159:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c:147:9-147:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c:110:9-110:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c:113:9-113:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c:57:9-58:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c:48:9-49:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c:54:9-55:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c:48:9-49:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c:55:9-55:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c:52:9-52:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c:53:9-53:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c:52:9-52:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c:62:9-62:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c:57:9-57:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c:59:9-59:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c:52:9-52:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c:55:9-55:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c:50:9-50:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c:95:9-96:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c:192:9-193:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c:196:9-197:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c:142:9-142:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c:145:9-146:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c:203:9-204:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c:208:9-209:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c:185:9-185:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c:112:9-112:33: #define BASE(seg) BASE_INNER(seg)
• drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c:197:9-198:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c:199:9-200:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c:204:9-205:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c:198:9-199:16: #define BASE(seg) \
• drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h:35:9-35:33: #define BASE(seg) BASE_INNER(seg)
• drivers/hwmon/pc87360.c:75:9-75:14: #define BASE 0x60 /* Register: Base address */
• drivers/media/pci/cobalt/cobalt-omnitek.c:42:9-42:29: #define BASE (cobalt->bar0)
• drivers/media/tuners/xc2028-types.h:14:9-14:20: #define BASE (1<<0)
• include/linux/zutil.h:53:9-53:14: #define BASE 65521L /* largest prime smaller than 65536 */