// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*/
#include <dt-bindings/clock/mt6797-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
/ {
compatible = "mediatek,mt6797";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
};
cpu8: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
reg = <0x200>;
};
cpu9: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
reg = <0x201>;
};
};
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
topckgen: topckgen@10000000 {
compatible = "mediatek,mt6797-topckgen";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infrasys: infracfg_ao@10001000 {
compatible = "mediatek,mt6797-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb",
"iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart0_pins_a: uart0 {
pins0 {
pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
<MT6797_GPIO235__FUNC_URXD0>;
};
};
uart1_pins_a: uart1 {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
i2c0_pins_a: i2c0 {
pins0 {
pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
<MT6797_GPIO38__FUNC_SDA0_0>;
};
};
i2c1_pins_a: i2c1 {
pins1 {
pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
<MT6797_GPIO56__FUNC_SDA1_0>;
};
};
i2c2_pins_a: i2c2 {
pins2 {
pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
<MT6797_GPIO95__FUNC_SDA2_0>;
};
};
i2c3_pins_a: i2c3 {
pins3 {
pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
<MT6797_GPIO74__FUNC_SCL3_0>;
};
};
i2c4_pins_a: i2c4 {
pins4 {
pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
<MT6797_GPIO239__FUNC_SCL4_0>;
};
};
i2c5_pins_a: i2c5 {
pins5 {
pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
<MT6797_GPIO241__FUNC_SCL5_0>;
};
};
i2c6_pins_a: i2c6 {
pins6 {
pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
<MT6797_GPIO151__FUNC_SCL6_0>;
};
};
i2c7_pins_a: i2c7 {
pins7 {
pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
<MT6797_GPIO153__FUNC_SCL7_0>;
};
};
};
scpsys: power-controller@10006000 {
compatible = "mediatek,mt6797-scpsys";
#power-domain-cells = <1>;
reg = <0 0x10006000 0 0x1000>;
clocks = <&topckgen CLK_TOP_MUX_MFG>,
<&topckgen CLK_TOP_MUX_MM>,
<&topckgen CLK_TOP_MUX_VDEC>;
clock-names = "mfg", "mm", "vdec";
infracfg = <&infrasys>;
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
};
apmixedsys: apmixed@1000c000 {
compatible = "mediatek,mt6797-apmixedsys";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6797-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10220620 0 0x20>,
<0 0x10220690 0 0x10>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART0>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART1>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART2>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART3>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <0>;
reg = <0 0x11007000 0 0x1000>,
<0 0x11000100 0 0x80>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C0>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <1>;
reg = <0 0x11008000 0 0x1000>,
<0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C1>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c8: i2c@11009000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <8>;
reg = <0 0x11009000 0 0x1000>,
<0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C2>,
<&infrasys CLK_INFRA_AP_DMA>,
<&infrasys CLK_INFRA_I2C2_ARB>;
clock-names = "main", "dma", "arb";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c@1100d000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <9>;
reg = <0 0x1100d000 0 0x1000>,
<0 0x11000280 0 0x80>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C3>,
<&infrasys CLK_INFRA_AP_DMA>,
<&infrasys CLK_INFRA_I2C3_ARB>;
clock-names = "main", "dma", "arb";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@1100e000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <6>;
reg = <0 0x1100e000 0 0x1000>,
<0 0x11000500 0 0x80>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C_APPM>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@11010000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <7>;
reg = <0 0x11010000 0 0x1000>,
<0 0x11000580 0 0x80>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C_GPUPM>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@11011000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <4>;
reg = <0 0x11011000 0 0x1000>,
<0 0x11000300 0 0x80>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C4>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11013000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <2>;
reg = <0 0x11013000 0 0x1000>,
<0 0x11000400 0 0x80>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C2_IMM>,
<&infrasys CLK_INFRA_AP_DMA>,
<&infrasys CLK_INFRA_I2C2_ARB>;
clock-names = "main", "dma", "arb";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@11014000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <3>;
reg = <0 0x11014000 0 0x1000>,
<0 0x11000480 0 0x80>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C3_IMM>,
<&infrasys CLK_INFRA_AP_DMA>,
<&infrasys CLK_INFRA_I2C3_ARB>;
clock-names = "main", "dma", "arb";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@1101c000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
id = <5>;
reg = <0 0x1101c000 0 0x1000>,
<0 0x11000380 0 0x80>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C5>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt6797-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
imgsys: imgsys_config@15000000 {
compatible = "mediatek,mt6797-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys: vdec_gcon@16000000 {
compatible = "mediatek,mt6797-vdecsys", "syscon";
reg = <0 0x16000000 0 0x10000>;
#clock-cells = <1>;
};
vencsys: venc_gcon@17000000 {
compatible = "mediatek,mt6797-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
gic: interrupt-controller@19000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
reg = <0 0x19000000 0 0x10000>, /* GICD */
<0 0x19200000 0 0x200000>, /* GICR */
<0 0x10240000 0 0x2000>; /* GICC */
};
};