#ifndef GOLDFISH_PIPE_QEMU_H
#define GOLDFISH_PIPE_QEMU_H
enum PipePollFlags {
PIPE_POLL_IN = 1 << 0,
PIPE_POLL_OUT = 1 << 1,
PIPE_POLL_HUP = 1 << 2
};
enum PipeErrors {
PIPE_ERROR_INVAL = -1,
PIPE_ERROR_AGAIN = -2,
PIPE_ERROR_NOMEM = -3,
PIPE_ERROR_IO = -4
};
enum PipeWakeFlags {
PIPE_WAKE_CLOSED = 1 << 0,
PIPE_WAKE_READ = 1 << 1,
PIPE_WAKE_WRITE = 1 << 2,
PIPE_WAKE_UNLOCK_DMA = 1 << 3,
PIPE_WAKE_UNLOCK_DMA_SHARED = 1 << 4,
};
enum PipeCloseReason {
PIPE_CLOSE_GRACEFUL = 0,
PIPE_CLOSE_REBOOT = 1,
PIPE_CLOSE_LOAD_SNAPSHOT = 2,
PIPE_CLOSE_ERROR = 3,
};
enum PipeFlagsBits {
BIT_CLOSED_ON_HOST = 0,
BIT_WAKE_ON_WRITE = 1,
BIT_WAKE_ON_READ = 2,
};
enum PipeRegs {
PIPE_REG_CMD = 0,
PIPE_REG_SIGNAL_BUFFER_HIGH = 4,
PIPE_REG_SIGNAL_BUFFER = 8,
PIPE_REG_SIGNAL_BUFFER_COUNT = 12,
PIPE_REG_OPEN_BUFFER_HIGH = 20,
PIPE_REG_OPEN_BUFFER = 24,
PIPE_REG_VERSION = 36,
PIPE_REG_GET_SIGNALLED = 48,
};
enum PipeCmdCode {
PIPE_CMD_OPEN = 1,
PIPE_CMD_CLOSE,
PIPE_CMD_POLL,
PIPE_CMD_WRITE,
PIPE_CMD_WAKE_ON_WRITE,
PIPE_CMD_READ,
PIPE_CMD_WAKE_ON_READ,
PIPE_CMD_WAKE_ON_DONE_IO,
};
#endif /* GOLDFISH_PIPE_QEMU_H */