# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display DPU on SM6115 maintainers: - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: const: qcom,sm6115-dpu reg: items: - description: MDP register set - description: VBIF register set reg-names: items: - const: mdp - const: vbif clocks: items: - description: Display AXI - description: Display AHB - description: Display core - description: Display lut - description: Display rotator - description: Display vsync clock-names: items: - const: bus - const: iface - const: core - const: lut - const: rot - const: vsync required: - compatible - reg - reg-names - clocks - clock-names unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,sm6115-dispcc.h> #include <dt-bindings/clock/qcom,gcc-sm6115.h> #include <dt-bindings/power/qcom-rpmpd.h> display-controller@5e01000 { compatible = "qcom,sm6115-dpu"; reg = <0x05e01000 0x8f000>, <0x05eb0000 0x2008>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmpd SM6115_VDDCX>; interrupt-parent = <&mdss>; interrupts = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; endpoint { remote-endpoint = <&dsi0_in>; }; }; }; }; ...