# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/qcom,qcs404-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm QCS404 TLMM pin controller maintainers: - Bjorn Andersson <andersson@kernel.org> - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> description: Top Level Mode Multiplexer pin controller in Qualcomm QCS404 SoC. properties: compatible: const: qcom,qcs404-pinctrl reg: maxItems: 3 reg-names: items: - const: south - const: north - const: east interrupts: maxItems: 1 interrupt-controller: true "#interrupt-cells": true gpio-controller: true "#gpio-cells": true gpio-ranges: true wakeup-parent: true gpio-reserved-ranges: minItems: 1 maxItems: 60 gpio-line-names: maxItems: 120 patternProperties: "-state$": oneOf: - $ref: "#/$defs/qcom-qcs404-tlmm-state" - patternProperties: "-pins$": $ref: "#/$defs/qcom-qcs404-tlmm-state" additionalProperties: false $defs: qcom-qcs404-tlmm-state: type: object description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state unevaluatedProperties: false properties: pins: description: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] minItems: 1 maxItems: 36 function: description: Specify the alternative function to be configured for the specified pins. enum: [ gpio, adsp_ext, atest_char, atest_char0, atest_char1, atest_char2, atest_char3, aud_cdc, audio_ts, bimc_dte0, bimc_dte1, blsp_i2c0, blsp_i2c1, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c_scl_a2, blsp_i2c_scl_b2, blsp_i2c_sda_a2, blsp_i2c_sda_b2, blsp_spi0, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi_clk_a1, blsp_spi_clk_b1, blsp_spi_cs_n_a1, blsp_spi_cs_n_b1, blsp_spi_miso_a1, blsp_spi_miso_b1, blsp_spi_mosi_a1, blsp_spi_mosi_b1, blsp_uart0, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart5, blsp_uart_rx_a2, blsp_uart_rx_b2, blsp_uart_tx_a2, blsp_uart_tx_b2, cri_trng, cri_trng0, cri_trng1, dbg_out, dsd_clk_a, dsd_clk_b, ebi2_a, ebi2_lcd, ebi_cdc, ebi_ch0, ext_lpass, ext_mclk0, ext_mclk1_a, ext_mclk1_b, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, hdmi_ddc, hdmi_dtest, hdmi_lbk0, hdmi_lbk1, hdmi_lbk2, hdmi_lbk3, hdmi_lbk4, hdmi_lbk5, hdmi_lbk6, hdmi_lbk7, hdmi_lbk8, hdmi_lbk9, hdmi_pixel, hdmi_rcv, hdmi_tx, i2s_1, i2s_2, i2s_3_data0_a, i2s_3_data0_b, i2s_3_data1_a, i2s_3_data1_b, i2s_3_data2_a, i2s_3_data2_b, i2s_3_data3_a, i2s_3_data3_b, i2s_3_sck_a, i2s_3_sck_b, i2s_3_ws_a, i2s_3_ws_b, i2s_4, ir_in, ldo_en, ldo_update, mclk_in1, mclk_in2, m_voc, nfc_dwl, nfc_irq, pcie_clk, pll_bist, prng_rosc, pwm_led1, pwm_led10, pwm_led11, pwm_led12, pwm_led13, pwm_led14, pwm_led15, pwm_led16, pwm_led17, pwm_led18, pwm_led19, pwm_led2, pwm_led20, pwm_led21, pwm_led22, pwm_led23, pwm_led24, pwm_led3, pwm_led4, pwm_led5, pwm_led6, pwm_led7, pwm_led8, pwm_led9, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rgb_clk, rgb_data0, rgb_data1, rgb_data2, rgb_data3, rgb_data4, rgb_data5, rgb_data6, rgb_data7, rgb_data_b0, rgb_data_b1, rgb_data_b2, rgb_data_b3, rgb_data_b4, rgb_data_b5, rgb_data_b6, rgb_data_b7, rgb_de, rgb_hsync, rgb_mdp, rgb_vsync, rgmi_dll1, rgmi_dll2, rgmii_ck, rgmii_ctl, rgmii_int, rgmii_mdc, rgmii_mdio, rgmii_rx, rgmii_tx, rgmii_wol, sd_write, spdifrx_opt, spi_lcd, spkr_dac0, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_en ] required: - pins allOf: - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# required: - compatible - reg additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, <0x01300000 0x200000>, <0x07b00000 0x200000>; reg-names = "south", "north", "east"; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-ranges = <&tlmm 0 0 120>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; blsp1-i2c1-default-state { pins = "gpio24", "gpio25"; function = "blsp_i2c1"; }; blsp1-i2c2-default-state { sda-pins { pins = "gpio19"; function = "blsp_i2c_sda_a2"; }; scl-pins { pins = "gpio20"; function = "blsp_i2c_scl_a2"; }; }; };