#ifndef ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_
#define ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID 0x41DAB80
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP 0x41DAB84
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x41DAB88
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x41DAB8C
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x41DAB90
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x41DAB94
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_QOS 0x41DAB98
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RSVD 0x41DAB9C
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x41DABA0
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_CORE 0x41DABA4
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_E2E_COORD 0x41DABA8
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x41DABB0
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x41DABB4
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x41DABB8
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x41DABBC
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_COORD 0x41DABC0
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_LOCK 0x41DABC4
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_RSVD 0x41DABC8
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_OVRD 0x41DABCC
#endif /* ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_ */