// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Endless Computers, Inc. * Author: Carlo Caione <carlo@endlessm.com> */ #include "meson-gxl.dtsi" / { compatible = "amlogic,meson-gxm"; cpus { cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; }; cluster1 { core0 { cpu = <&cpu4>; }; core1 { cpu = <&cpu5>; }; core2 { cpu = <&cpu6>; }; core3 { cpu = <&cpu7>; }; }; }; cpu0: cpu@0 { capacity-dmips-mhz = <1024>; }; cpu1: cpu@1 { capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; }; cpu5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; }; cpu6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; }; cpu7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; }; }; gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-125000000 { opp-hz = /bits/ 64 <125000000>; opp-microvolt = <950000>; }; opp-250000000 { opp-hz = /bits/ 64 <250000000>; opp-microvolt = <950000>; }; opp-285714285 { opp-hz = /bits/ 64 <285714285>; opp-microvolt = <950000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-microvolt = <950000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <950000>; }; opp-666666666 { opp-hz = /bits/ 64 <666666666>; opp-microvolt = <950000>; }; }; }; &apb { usb2_phy2: phy@78040 { compatible = "amlogic,meson-gxl-usb2-phy"; #phy-cells = <0>; reg = <0x0 0x78040 0x0 0x20>; clocks = <&clkc CLKID_USB>; clock-names = "phy"; resets = <&reset RESET_USB_OTG>; reset-names = "phy"; status = "okay"; }; mali: gpu@c0000 { compatible = "amlogic,meson-gxm-mali", "arm,mali-t820"; reg = <0x0 0xc0000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "job", "mmu", "gpu"; clocks = <&clkc CLKID_MALI>; resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>; operating-points-v2 = <&gpu_opp_table>; }; }; &clkc_AO { compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc"; }; &cpu_cooling_maps { map0 { cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; &saradc { compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc"; }; &scpi_dvfs { clock-indices = <0 1>; clock-output-names = "vbig", "vlittle"; }; &vpu { compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu"; }; &hdmi_tx { compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; }; &usb { compatible = "amlogic,meson-gxm-usb-ctrl"; phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2"; phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; }; &vdec { compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec"; };