// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Eagle board with R-Car V3M * * Copyright (C) 2016-2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. */ /dts-v1/; #include "r8a77970.dtsi" #include <dt-bindings/gpio/gpio.h> / { model = "Renesas Eagle board based on r8a77970"; compatible = "renesas,eagle", "renesas,r8a77970"; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; serial0 = &scif0; ethernet0 = &avb; }; chosen { bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; d3p3: regulator-fixed { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; hdmi-out { compatible = "hdmi-connector"; type = "a"; port { hdmi_con_out: endpoint { remote-endpoint = <&adv7511_out>; }; }; }; lvds-decoder { compatible = "thine,thc63lvd1024"; vcc-supply = <&d3p3>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; thc63lvd1024_in: endpoint { remote-endpoint = <&lvds0_out>; }; }; port@2 { reg = <2>; thc63lvd1024_out: endpoint { remote-endpoint = <&adv7511_in>; }; }; }; }; memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; x1_clk: x1-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <148500000>; }; }; &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; renesas,no-ether-link; phy-handle = <&phy0>; rx-internal-delay-ps = <1800>; tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { compatible = "ethernet-phy-id0022.1622", "ethernet-phy-ieee802.3-c22"; rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio1>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; &canfd { pinctrl-0 = <&canfd0_pins>; pinctrl-names = "default"; status = "okay"; channel0 { status = "okay"; }; }; &csi40 { status = "okay"; ports { port@0 { csi40_in: endpoint { clock-lanes = <0>; data-lanes = <1 2 3 4>; remote-endpoint = <&max9286_out0>; }; }; }; }; &du { clocks = <&cpg CPG_MOD 724>, <&x1_clk>; clock-names = "du.0", "dclkin.0"; status = "okay"; }; &extal_clk { clock-frequency = <16666666>; }; &extalr_clk { clock-frequency = <32768>; }; &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; status = "okay"; clock-frequency = <400000>; io_expander: gpio@20 { compatible = "onnn,pca9654"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; }; hdmi@39 { compatible = "adi,adv7511w"; reg = <0x39>; interrupt-parent = <&gpio1>; interrupts = <20 IRQ_TYPE_LEVEL_LOW>; adi,input-depth = <8>; adi,input-colorspace = "rgb"; adi,input-clock = "1x"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; adv7511_in: endpoint { remote-endpoint = <&thc63lvd1024_out>; }; }; port@1 { reg = <1>; adv7511_out: endpoint { remote-endpoint = <&hdmi_con_out>; }; }; }; }; }; &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; status = "okay"; clock-frequency = <400000>; gmsl0: gmsl-deserializer@48 { compatible = "maxim,max9286"; reg = <0x48>; maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@1 { reg = <1>; }; port@2 { reg = <2>; }; port@3 { reg = <3>; }; port@4 { reg = <4>; max9286_out0: endpoint { clock-lanes = <0>; data-lanes = <1 2 3 4>; remote-endpoint = <&csi40_in>; }; }; }; i2c-mux { #address-cells = <1>; #size-cells = <0>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; status = "disabled"; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; status = "disabled"; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; status = "disabled"; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; status = "disabled"; }; }; }; }; &lvds0 { status = "okay"; ports { port@1 { lvds0_out: endpoint { remote-endpoint = <&thc63lvd1024_in>; }; }; }; }; &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; avb_pins: avb0 { groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; function = "avb0"; }; canfd0_pins: canfd0 { groups = "canfd0_data_a"; function = "canfd0"; }; i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; }; i2c3_pins: i2c3 { groups = "i2c3_a"; function = "i2c3"; }; qspi0_pins: qspi0 { groups = "qspi0_ctrl", "qspi0_data4"; function = "qspi0"; }; scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; }; scif_clk_pins: scif_clk { groups = "scif_clk_b"; function = "scif_clk"; }; }; &rpc { pinctrl-0 = <&qspi0_pins>; pinctrl-names = "default"; status = "okay"; flash@0 { compatible = "spansion,s25fs512s", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; bootparam@0 { reg = <0x00000000 0x040000>; read-only; }; cr7@40000 { reg = <0x00040000 0x080000>; read-only; }; cert_header_sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; bl2@140000 { reg = <0x00140000 0x040000>; read-only; }; cert_header_sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; bl31@1c0000 { reg = <0x001c0000 0x460000>; read-only; }; uboot@640000 { reg = <0x00640000 0x0c0000>; read-only; }; uboot-env@700000 { reg = <0x00700000 0x040000>; read-only; }; dtb@740000 { reg = <0x00740000 0x080000>; }; kernel@7c0000 { reg = <0x007c0000 0x1400000>; }; user@1bc0000 { reg = <0x01bc0000 0x2440000>; }; }; }; }; &rwdt { timeout-sec = <60>; status = "okay"; }; &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; status = "okay"; }; &scif_clk { clock-frequency = <14745600>; };