// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Source for the TMPV7708
*
* (C) Copyright 2018 - 2020, Toshiba Corporation.
* (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
*
*/
#include <dt-bindings/clock/toshiba,tmpv770x.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
/ {
compatible = "toshiba,tmpv7708";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x00>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x01>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x02>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x03>;
};
cpu4: cpu@100 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x100>;
};
cpu5: cpu@101 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x101>;
};
cpu6: cpu@102 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x102>;
};
cpu7: cpu@103 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x103>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
extclk100mhz: extclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "extclk100mhz";
};
osc2_clk: osc2-clk {
compatible = "fixed-clock";
clock-frequency = <20000000>;
#clock-cells = <0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
gic: interrupt-controller@24001000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
reg = <0 0x24001000 0 0x1000>,
<0 0x24002000 0 0x2000>,
<0 0x24004000 0 0x2000>,
<0 0x24006000 0 0x2000>;
};
pmux: pmux@24190000 {
compatible = "toshiba,tmpv7708-pinctrl";
reg = <0 0x24190000 0 0x10000>;
};
gpio: gpio@28020000 {
compatible = "toshiba,gpio-tmpv7708";
reg = <0 0x28020000 0 0x1000>;
#gpio-cells = <0x2>;
gpio-ranges = <&pmux 0 0 32>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
};
pipllct: clock-controller@24220000 {
compatible = "toshiba,tmpv7708-pipllct";
reg = <0 0x24220000 0 0x820>;
#clock-cells = <1>;
clocks = <&osc2_clk>;
};
pismu: syscon@24200000 {
compatible = "toshiba,tmpv7708-pismu", "syscon";
reg = <0 0x24200000 0 0x2140>;
#clock-cells = <1>;
#reset-cells = <1>;
};
uart0: serial@28200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0x28200000 0 0x1000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
clocks = <&pismu TMPV770X_CLK_PIUART0>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: serial@28201000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0x28201000 0 0x1000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
clocks = <&pismu TMPV770X_CLK_PIUART1>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: serial@28202000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0x28202000 0 0x1000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
clocks = <&pismu TMPV770X_CLK_PIUART2>;
clock-names = "apb_pclk";
status = "disabled";
};
uart3: serial@28203000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0x28203000 0 0x1000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
clocks = <&pismu TMPV770X_CLK_PIUART2>;
clock-names = "apb_pclk";
status = "disabled";
};
i2c0: i2c@28030000 {
compatible = "snps,designware-i2c";
reg = <0 0x28030000 0 0x1000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PII2C0>;
status = "disabled";
};
i2c1: i2c@28031000 {
compatible = "snps,designware-i2c";
reg = <0 0x28031000 0 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PII2C1>;
status = "disabled";
};
i2c2: i2c@28032000 {
compatible = "snps,designware-i2c";
reg = <0 0x28032000 0 0x1000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PII2C2>;
status = "disabled";
};
i2c3: i2c@28033000 {
compatible = "snps,designware-i2c";
reg = <0 0x28033000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PII2C3>;
status = "disabled";
};
i2c4: i2c@28034000 {
compatible = "snps,designware-i2c";
reg = <0 0x28034000 0 0x1000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PII2C4>;
status = "disabled";
};
i2c5: i2c@28035000 {
compatible = "snps,designware-i2c";
reg = <0 0x28035000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PII2C5>;
status = "disabled";
};
i2c6: i2c@28036000 {
compatible = "snps,designware-i2c";
reg = <0 0x28036000 0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PII2C6>;
status = "disabled";
};
i2c7: i2c@28037000 {
compatible = "snps,designware-i2c";
reg = <0 0x28037000 0 0x1000>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PII2C7>;
status = "disabled";
};
i2c8: i2c@28038000 {
compatible = "snps,designware-i2c";
reg = <0 0x28038000 0 0x1000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PII2C8>;
status = "disabled";
};
spi0: spi@28140000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28140000 0 0x1000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PISPI1>;
clock-names = "apb_pclk";
status = "disabled";
};
spi1: spi@28141000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28141000 0 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PISPI1>;
clock-names = "apb_pclk";
status = "disabled";
};
spi2: spi@28142000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28142000 0 0x1000>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PISPI2>;
clock-names = "apb_pclk";
status = "disabled";
};
spi3: spi@28143000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28143000 0 0x1000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PISPI3>;
clock-names = "apb_pclk";
status = "disabled";
};
spi4: spi@28144000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28144000 0 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi4_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PISPI4>;
clock-names = "apb_pclk";
status = "disabled";
};
spi5: spi@28145000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28145000 0 0x1000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi5_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PISPI5>;
clock-names = "apb_pclk";
status = "disabled";
};
spi6: spi@28146000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28146000 0 0x1000>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi6_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pismu TMPV770X_CLK_PISPI6>;
clock-names = "apb_pclk";
status = "disabled";
};
piether: ethernet@28000000 {
compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a";
reg = <0 0x28000000 0 0x10000>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,txpbl = <4>;
snps,rxpbl = <4>;
snps,tso;
clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>;
clock-names = "stmmaceth", "phy_ref_clk";
status = "disabled";
};
wdt: wdt@28330000 {
compatible = "toshiba,visconti-wdt";
reg = <0 0x28330000 0 0x1000>;
clocks = <&pismu TMPV770X_CLK_WDTCLK>;
status = "disabled";
};
pwm: pwm@241c0000 {
compatible = "toshiba,visconti-pwm";
reg = <0 0x241c0000 0 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&pwm_mux>;
#pwm-cells = <2>;
status = "disabled";
};
pcie: pcie@28400000 {
compatible = "toshiba,visconti-pcie";
reg = <0x0 0x28400000 0x0 0x00400000>,
<0x0 0x70000000 0x0 0x10000000>,
<0x0 0x28050000 0x0 0x00010000>,
<0x0 0x24200000 0x0 0x00002000>,
<0x0 0x24162000 0x0 0x00001000>;
reg-names = "dbi", "config", "ulreg", "smu", "mpu";
device_type = "pci";
bus-range = <0x00 0xff>;
num-lanes = <2>;
num-viewport = <8>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi", "intr";
interrupt-map-mask = <0 0 0 7>;
interrupt-map =
<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
max-link-speed = <2>;
clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
clock-names = "ref", "core", "aux";
status = "disabled";
};
};
};
#include "tmpv7708_pins.dtsi"