// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-j7200.dtsi"
/ {
memory@80000000 {
device_type = "memory";
/* 4G RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x00 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
alignment = <0x1000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a4000000 {
reg = <0x00 0xa4000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
};
&wkup_pmx0 {
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
>;
};
};
&wkup_pmx2 {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>;
};
};
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
>;
};
};
&hbmc {
/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
* appropriate node based on board detection
*/
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
<0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x00 0x00 0x4000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "hbmc.tiboot3";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "hbmc.tispl";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "hbmc.u-boot";
reg = <0x300000 0x400000>;
};
partition@700000 {
label = "hbmc.env";
reg = <0x700000 0x40000>;
};
partition@800000 {
label = "hbmc.rootfs";
reg = <0x800000 0x3800000>;
};
};
};
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
exp_som: gpio@21 {
compatible = "ti,tca6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
"CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
"UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
"GPIO_LIN_EN", "CAN_STB";
};
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
};
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "ospi.tispl";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "ospi.u-boot";
reg = <0x300000 0x400000>;
};
partition@700000 {
label = "ospi.env";
reg = <0x700000 0x40000>;
};
partition@740000 {
label = "ospi.env.backup";
reg = <0x740000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};