# SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface maintainers: - Mark Brown <broonie@kernel.org> allOf: - $ref: spi-controller.yaml# - if: properties: compatible: contains: enum: - mscc,ocelot-spi - mscc,jaguar2-spi then: properties: reg: minItems: 2 - if: properties: compatible: contains: enum: - baikal,bt1-sys-ssi then: properties: mux-controls: maxItems: 1 required: - mux-controls else: required: - interrupts - if: properties: compatible: contains: const: amd,pensando-elba-spi then: required: - amd,pensando-elba-syscon else: properties: amd,pensando-elba-syscon: false properties: compatible: oneOf: - description: Generic DW SPI Controller enum: - snps,dw-apb-ssi - snps,dwc-ssi-1.01a - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller items: - enum: - mscc,ocelot-spi - mscc,jaguar2-spi - const: snps,dw-apb-ssi - description: Microchip Sparx5 SoC SPI Controller const: microchip,sparx5-spi - description: Amazon Alpine SPI Controller const: amazon,alpine-dw-apb-ssi - description: Renesas RZ/N1 SPI Controller items: - const: renesas,rzn1-spi - const: snps,dw-apb-ssi - description: Intel Keem Bay SPI Controller const: intel,keembay-ssi - description: Intel Thunder Bay SPI Controller const: intel,thunderbay-ssi - description: Intel Mount Evans Integrated Management Complex SPI Controller const: intel,mountevans-imc-ssi - description: AMD Pensando Elba SoC SPI Controller const: amd,pensando-elba-spi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller const: baikal,bt1-sys-ssi - description: Canaan Kendryte K210 SoS SPI Controller const: canaan,k210-spi - description: Renesas RZ/N1 SPI Controller items: - enum: - renesas,r9a06g032-spi # RZ/N1D - renesas,r9a06g033-spi # RZ/N1S - const: renesas,rzn1-spi # RZ/N1 reg: minItems: 1 items: - description: DW APB SSI controller memory mapped registers - description: SPI MST region map or directly mapped SPI ROM interrupts: maxItems: 1 clocks: minItems: 1 items: - description: SPI Controller reference clock source - description: APB interface clock source clock-names: minItems: 1 items: - const: ssi_clk - const: pclk resets: maxItems: 1 reset-names: const: spi reg-io-width: description: I/O register width (in bytes) implemented by this device default: 4 enum: [ 2, 4 ] num-cs: default: 4 minimum: 1 maximum: 4 dmas: items: - description: TX DMA Channel - description: RX DMA Channel dma-names: items: - const: tx - const: rx rx-sample-delay-ns: default: 0 description: | Default value of the rx-sample-delay-ns property. This value will be used if the property is not explicitly defined for a SPI slave device. SPI Rx sample delay offset, unit is nanoseconds. The delay from the default sample time before the actual sample of the rxd input signal occurs. The "rx_sample_delay" is an optional feature of the designware controller, and the upper limit is also subject to controller configuration. amd,pensando-elba-syscon: $ref: /schemas/types.yaml#/definitions/phandle-array description: Block address to control SPI chip-selects. The Elba SoC system controller provides an interface to override the native DWC SSI CS control. patternProperties: "^.*@[0-9a-f]+$": type: object properties: reg: minimum: 0 maximum: 3 unevaluatedProperties: false required: - compatible - reg - "#address-cells" - "#size-cells" - clocks examples: - | spi@fff00000 { compatible = "snps,dw-apb-ssi"; reg = <0xfff00000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 154 4>; clocks = <&spi_m_clk>; num-cs = <2>; cs-gpios = <&gpio0 13 0>, <&gpio0 14 0>; rx-sample-delay-ns = <3>; flash@1 { compatible = "spi-nand"; reg = <1>; rx-sample-delay-ns = <7>; }; }; - | spi@1f040100 { compatible = "baikal,bt1-sys-ssi"; reg = <0x1f040100 0x900>, <0x1c000000 0x1000000>; #address-cells = <1>; #size-cells = <0>; mux-controls = <&boot_mux>; clocks = <&ccu_sys>; clock-names = "ssi_clk"; }; ...