#ifndef ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_
#define ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_ASID 0x40F9A80
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_MMU_BP 0x40F9A84
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x40F9A88
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_NO_SNOOP 0x40F9A8C
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x40F9A90
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x40F9A94
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_QOS 0x40F9A98
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RSVD 0x40F9A9C
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x40F9AA0
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_CORE 0x40F9AA4
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_E2E_COORD 0x40F9AA8
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x40F9AB0
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x40F9AB4
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x40F9AB8
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x40F9ABC
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_COORD 0x40F9AC0
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_LOCK 0x40F9AC4
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_RSVD 0x40F9AC8
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_OVRD 0x40F9ACC
#endif /* ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_ */