/*
 * Copyright (C) 2022  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef _dcn_3_2_0_OFFSET_HEADER
#define _dcn_3_2_0_OFFSET_HEADER



// addressBlock: dcn_dc_dccg_dccg_dfs_dispdec
// base address: 0x0
#define regDENTIST_DISPCLK_CNTL                                                                         0x0064
#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1


// addressBlock: dcn_dc_dccg_dccg_dispdec
// base address: 0x0
#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regDP_DTO_DBUF_EN                                                                               0x0044
#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1
#define regDSCCLK3_DTO_PARAM                                                                            0x0045
#define regDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1
#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049
#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1
#define regDPSTREAMCLK_CNTL                                                                             0x004a
#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1
#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
#define regDCCG_GLOBAL_FGCG_REP_CNTL                                                                    0x0050
#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX                                                           1
#define regDCCG_DS_DTO_INCR                                                                             0x0053
#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
#define regDCCG_DS_DTO_MODULO                                                                           0x0054
#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
#define regDCCG_DS_CNTL                                                                                 0x0055
#define regDCCG_DS_CNTL_BASE_IDX                                                                        1
#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
#define regDPREFCLK_CNTL                                                                                0x0058
#define regDPREFCLK_CNTL_BASE_IDX                                                                       1
#define regDCE_VERSION                                                                                  0x005e
#define regDCE_VERSION_BASE_IDX                                                                         1
#define regDCCG_GTC_CNTL                                                                                0x0060
#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1
#define regDCCG_GTC_DTO_INCR                                                                            0x0061
#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
#define regDCCG_GTC_DTO_MODULO                                                                          0x0062
#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
#define regDCCG_GTC_CURRENT                                                                             0x0063
#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1
#define regSYMCLK32_SE_CNTL                                                                             0x0065
#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1
#define regSYMCLK32_LE_CNTL                                                                             0x0066
#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1
#define regDTBCLK_P_CNTL                                                                                0x0068
#define regDTBCLK_P_CNTL_BASE_IDX                                                                       1
#define regDCCG_GATE_DISABLE_CNTL5                                                                      0x0069
#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX                                                             1
#define regDSCCLK0_DTO_PARAM                                                                            0x006c
#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
#define regDSCCLK1_DTO_PARAM                                                                            0x006d
#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
#define regDSCCLK2_DTO_PARAM                                                                            0x006e
#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
#define regOTG_PIXEL_RATE_DIV                                                                           0x006f
#define regOTG_PIXEL_RATE_DIV_BASE_IDX                                                                  1
#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070
#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074
#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
#define regDCCG_CAC_STATUS                                                                              0x0077
#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1
#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b
#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
#define regDCCG_DISP_CNTL_REG                                                                           0x007f
#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080
#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
#define regDP_DTO0_PHASE                                                                                0x0081
#define regDP_DTO0_PHASE_BASE_IDX                                                                       1
#define regDP_DTO0_MODULO                                                                               0x0082
#define regDP_DTO0_MODULO_BASE_IDX                                                                      1
#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084
#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
#define regDP_DTO1_PHASE                                                                                0x0085
#define regDP_DTO1_PHASE_BASE_IDX                                                                       1
#define regDP_DTO1_MODULO                                                                               0x0086
#define regDP_DTO1_MODULO_BASE_IDX                                                                      1
#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088
#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
#define regDP_DTO2_PHASE                                                                                0x0089
#define regDP_DTO2_PHASE_BASE_IDX                                                                       1
#define regDP_DTO2_MODULO                                                                               0x008a
#define regDP_DTO2_MODULO_BASE_IDX                                                                      1
#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c
#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
#define regDP_DTO3_PHASE                                                                                0x008d
#define regDP_DTO3_PHASE_BASE_IDX                                                                       1
#define regDP_DTO3_MODULO                                                                               0x008e
#define regDP_DTO3_MODULO_BASE_IDX                                                                      1
#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
#define regDPPCLK0_DTO_PARAM                                                                            0x0099
#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
#define regDPPCLK1_DTO_PARAM                                                                            0x009a
#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
#define regDPPCLK2_DTO_PARAM                                                                            0x009b
#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
#define regDPPCLK3_DTO_PARAM                                                                            0x009c
#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
#define regDCCG_CAC_STATUS2                                                                             0x009f
#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1
#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
#define regDCCG_SOFT_RESET                                                                              0x00a6
#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1
#define regDSCCLK_DTO_CTRL                                                                              0x00a7
#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
#define regDPPCLK_DTO_CTRL                                                                              0x00b6
#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba
#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
#define regDCCG_TEST_CLK_SEL                                                                            0x00be
#define regDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1
#define regDTBCLK_DTO0_PHASE                                                                            0x0018
#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2
#define regDTBCLK_DTO1_PHASE                                                                            0x0019
#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2
#define regDTBCLK_DTO2_PHASE                                                                            0x001a
#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2
#define regDTBCLK_DTO3_PHASE                                                                            0x001b
#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2
#define regDTBCLK_DTO0_MODULO                                                                           0x001f
#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2
#define regDTBCLK_DTO1_MODULO                                                                           0x0020
#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2
#define regDTBCLK_DTO2_MODULO                                                                           0x0021
#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2
#define regDTBCLK_DTO3_MODULO                                                                           0x0022
#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2
#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a
#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2
#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056
#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
#define regHDMISTREAMCLK_CNTL                                                                           0x0059
#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2
#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a
#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2
#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b
#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2
#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061
#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2
#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062
#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2
#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063
#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2
#define regDMCUBCLK_CNTL                                                                                0x0067
#define regDMCUBCLK_CNTL_BASE_IDX                                                                       2


// addressBlock: dcn_dc_dmu_rbbmif_dispdec
// base address: 0x0
#define regRBBMIF_TIMEOUT                                                                               0x017f
#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2
#define regRBBMIF_STATUS                                                                                0x0180
#define regRBBMIF_STATUS_BASE_IDX                                                                       2
#define regRBBMIF_STATUS_2                                                                              0x0181
#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2
#define regRBBMIF_INT_STATUS                                                                            0x0182
#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2
#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183
#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
#define regRBBMIF_STATUS_FLAG                                                                           0x0185
#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2


// addressBlock: dcn_dc_dmu_ihc_dispdec
// base address: 0x0
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
#define regDC_GPU_TIMER_READ                                                                            0x0128
#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2
#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129
#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
#define regDISP_INTERRUPT_STATUS                                                                        0x012a
#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
#define regDCCG_INTERRUPT_DEST                                                                          0x0148
#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regDMU_INTERRUPT_DEST                                                                           0x0149
#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regDMU_INTERRUPT_DEST2                                                                          0x014a
#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
#define regDCPG_INTERRUPT_DEST                                                                          0x014b
#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regDCPG_INTERRUPT_DEST2                                                                         0x014c
#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
#define regWB_INTERRUPT_DEST                                                                            0x014e
#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2
#define regDCHUB_INTERRUPT_DEST                                                                         0x014f
#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151
#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
#define regMPC_INTERRUPT_DEST                                                                           0x0153
#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regOPP_INTERRUPT_DEST                                                                           0x0154
#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regOPTC_INTERRUPT_DEST                                                                          0x0155
#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG0_INTERRUPT_DEST                                                                          0x0156
#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG1_INTERRUPT_DEST                                                                          0x0157
#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG2_INTERRUPT_DEST                                                                          0x0158
#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG3_INTERRUPT_DEST                                                                          0x0159
#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG4_INTERRUPT_DEST                                                                          0x015a
#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regOTG5_INTERRUPT_DEST                                                                          0x015b
#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regDIG_INTERRUPT_DEST                                                                           0x015c
#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
#define regDIO_INTERRUPT_DEST                                                                           0x015f
#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regDCIO_INTERRUPT_DEST                                                                          0x0160
#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
#define regHPD_INTERRUPT_DEST                                                                           0x0161
#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regAZ_INTERRUPT_DEST                                                                            0x0162
#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
#define regAUX_INTERRUPT_DEST                                                                           0x0163
#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regDSC_INTERRUPT_DEST                                                                           0x0164
#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
#define regHPO_INTERRUPT_DEST                                                                           0x0165
#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2


// addressBlock: dcn_dc_dmu_dmu_misc_dispdec
// base address: 0x0
#define regCC_DC_PIPE_DIS                                                                               0x00ca
#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2
#define regDMU_CLK_CNTL                                                                                 0x00cb
#define regDMU_CLK_CNTL_BASE_IDX                                                                        2
#define regDMCUB_SMU_INTERRUPT_CNTL                                                                     0x00cd
#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX                                                            2
#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce
#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2


// addressBlock: dcn_dc_dmu_dc_pg_dispdec
// base address: 0x0
#define regDOMAIN0_PG_CONFIG                                                                            0x0080
#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
#define regDOMAIN0_PG_STATUS                                                                            0x0081
#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
#define regDOMAIN1_PG_CONFIG                                                                            0x0082
#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
#define regDOMAIN1_PG_STATUS                                                                            0x0083
#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
#define regDOMAIN2_PG_CONFIG                                                                            0x0084
#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
#define regDOMAIN2_PG_STATUS                                                                            0x0085
#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
#define regDOMAIN3_PG_CONFIG                                                                            0x0086
#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
#define regDOMAIN3_PG_STATUS                                                                            0x0087
#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
#define regDOMAIN16_PG_CONFIG                                                                           0x0089
#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN16_PG_STATUS                                                                           0x008a
#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN17_PG_CONFIG                                                                           0x008b
#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN17_PG_STATUS                                                                           0x008c
#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN18_PG_CONFIG                                                                           0x008d
#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN18_PG_STATUS                                                                           0x008e
#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
#define regDOMAIN19_PG_CONFIG                                                                           0x008f
#define regDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2
#define regDOMAIN19_PG_STATUS                                                                           0x0090
#define regDOMAIN19_PG_STATUS_BASE_IDX                                                                  2
#define regDCPG_INTERRUPT_STATUS                                                                        0x0091
#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
#define regDCPG_INTERRUPT_STATUS_2                                                                      0x0092
#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x0093
#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x0094
#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
#define regDC_IP_REQUEST_CNTL                                                                           0x0095
#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2


// addressBlock: dcn_dc_dmu_dmcub_dispdec
// base address: 0x0
#define regDMCUB_REGION0_OFFSET                                                                         0x018e
#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION1_OFFSET                                                                         0x0190
#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION2_OFFSET                                                                         0x0192
#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION4_OFFSET                                                                         0x0196
#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION5_OFFSET                                                                         0x0198
#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION6_OFFSET                                                                         0x019a
#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION7_OFFSET                                                                         0x019c
#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6
#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7
#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8
#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
#define regDMCUB_SEC_CNTL                                                                               0x01ce
#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2
#define regDMCUB_MEM_CNTL                                                                               0x01cf
#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2
#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_INBOX0_SIZE                                                                            0x01d1
#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
#define regDMCUB_INBOX0_WPTR                                                                            0x01d2
#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
#define regDMCUB_INBOX0_RPTR                                                                            0x01d3
#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
#define regDMCUB_INBOX1_SIZE                                                                            0x01d5
#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
#define regDMCUB_INBOX1_WPTR                                                                            0x01d6
#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
#define regDMCUB_INBOX1_RPTR                                                                            0x01d7
#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9
#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da
#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db
#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd
#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de
#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df
#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0
#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1
#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
#define regDMCUB_TIMER_WINDOW                                                                           0x01e2
#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
#define regDMCUB_SCRATCH0                                                                               0x01e3
#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH1                                                                               0x01e4
#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH2                                                                               0x01e5
#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH3                                                                               0x01e6
#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH4                                                                               0x01e7
#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH5                                                                               0x01e8
#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH6                                                                               0x01e9
#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH7                                                                               0x01ea
#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH8                                                                               0x01eb
#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH9                                                                               0x01ec
#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2
#define regDMCUB_SCRATCH10                                                                              0x01ed
#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH11                                                                              0x01ee
#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH12                                                                              0x01ef
#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH13                                                                              0x01f0
#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH14                                                                              0x01f1
#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH15                                                                              0x01f2
#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH16                                                                              0x01f3
#define regDMCUB_SCRATCH16_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH17                                                                              0x01f4
#define regDMCUB_SCRATCH17_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH18                                                                              0x01f5
#define regDMCUB_SCRATCH18_BASE_IDX                                                                     2
#define regDMCUB_CNTL                                                                                   0x01f6
#define regDMCUB_CNTL_BASE_IDX                                                                          2
#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7
#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8
#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9
#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc
#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
#define regDMCUB_TIMER_CURRENT                                                                          0x01fd
#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
#define regDMCUB_PROC_ID                                                                                0x01ff
#define regDMCUB_PROC_ID_BASE_IDX                                                                       2
#define regDMCUB_CNTL2                                                                                  0x0200
#define regDMCUB_CNTL2_BASE_IDX                                                                         2
#define regDMCUB_GPINT_DATAIN2                                                                          0x0215
#define regDMCUB_GPINT_DATAIN2_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN3                                                                          0x0216
#define regDMCUB_GPINT_DATAIN3_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN4                                                                          0x0217
#define regDMCUB_GPINT_DATAIN4_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN5                                                                          0x0218
#define regDMCUB_GPINT_DATAIN5_BASE_IDX                                                                 2
#define regDMCUB_GPINT_DATAIN6                                                                          0x0219
#define regDMCUB_GPINT_DATAIN6_BASE_IDX                                                                 2
#define regDMCUB_REGION3_TMR_AXI_SPACE                                                                  0x021a
#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX                                                         2
#define regDMCUB_SCRATCH19                                                                              0x022e
#define regDMCUB_SCRATCH19_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH20                                                                              0x022f
#define regDMCUB_SCRATCH20_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH21                                                                              0x0230
#define regDMCUB_SCRATCH21_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH22                                                                              0x0231
#define regDMCUB_SCRATCH22_BASE_IDX                                                                     2
#define regDMCUB_SCRATCH23                                                                              0x0232
#define regDMCUB_SCRATCH23_BASE_IDX                                                                     2


// addressBlock: dcn_dc_wb0_dispdec_dwb_top_dispdec
// base address: 0x0
#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228
#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
#define regDWB_MEM_PWR_CTRL                                                                             0x3229
#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
#define regFC_MODE_CTRL                                                                                 0x322a
#define regFC_MODE_CTRL_BASE_IDX                                                                        2
#define regFC_FLOW_CTRL                                                                                 0x322b
#define regFC_FLOW_CTRL_BASE_IDX                                                                        2
#define regFC_WINDOW_START                                                                              0x322c
#define regFC_WINDOW_START_BASE_IDX                                                                     2
#define regFC_WINDOW_SIZE                                                                               0x322d
#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2
#define regFC_SOURCE_SIZE                                                                               0x322e
#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2
#define regDWB_UPDATE_CTRL                                                                              0x322f
#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2
#define regDWB_CRC_CTRL                                                                                 0x3230
#define regDWB_CRC_CTRL_BASE_IDX                                                                        2
#define regDWB_CRC_MASK_R_G                                                                             0x3231
#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
#define regDWB_CRC_MASK_B_A                                                                             0x3232
#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
#define regDWB_CRC_VAL_R_G                                                                              0x3233
#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
#define regDWB_CRC_VAL_B_A                                                                              0x3234
#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
#define regDWB_OUT_CTRL                                                                                 0x3235
#define regDWB_OUT_CTRL_BASE_IDX                                                                        2
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
#define regDWB_HOST_READ_CONTROL                                                                        0x3238
#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
#define regDWB_OVERFLOW_STATUS                                                                          0x3239
#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
#define regDWB_OVERFLOW_COUNTER                                                                         0x323a
#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
#define regDWB_SOFT_RESET                                                                               0x323b
#define regDWB_SOFT_RESET_BASE_IDX                                                                      2


// addressBlock: dcn_dc_wb0_dispdec_dwbcp_dispdec
// base address: 0x0
#define regDWB_HDR_MULT_COEF                                                                            0x3294
#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295
#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
#define regDWB_OGAM_CONTROL                                                                             0x32a3
#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2
#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4
#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
#define regDWB_OGAM_LUT_DATA                                                                            0x32a5
#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6
#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2


// addressBlock: dcn_dc_mmhubbub_vga_dispdec
// base address: 0x0
#define regVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
#define regVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
#define regVGA_RENDER_CONTROL                                                                           0x0000
#define regVGA_RENDER_CONTROL_BASE_IDX                                                                  1
#define regVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
#define regVGA_MODE_CONTROL                                                                             0x0002
#define regVGA_MODE_CONTROL_BASE_IDX                                                                    1
#define regVGA_SURFACE_PITCH_SELECT                                                                     0x0003
#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
#define regVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
#define regVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
#define regVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
#define regVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
#define regVGA_HDP_CONTROL                                                                              0x000a
#define regVGA_HDP_CONTROL_BASE_IDX                                                                     1
#define regVGA_CACHE_CONTROL                                                                            0x000b
#define regVGA_CACHE_CONTROL_BASE_IDX                                                                   1
#define regD1VGA_CONTROL                                                                                0x000c
#define regD1VGA_CONTROL_BASE_IDX                                                                       1
#define regD2VGA_CONTROL                                                                                0x000e
#define regD2VGA_CONTROL_BASE_IDX                                                                       1
#define regVGA_STATUS                                                                                   0x0010
#define regVGA_STATUS_BASE_IDX                                                                          1
#define regVGA_INTERRUPT_CONTROL                                                                        0x0011
#define regVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
#define regVGA_STATUS_CLEAR                                                                             0x0012
#define regVGA_STATUS_CLEAR_BASE_IDX                                                                    1
#define regVGA_INTERRUPT_STATUS                                                                         0x0013
#define regVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
#define regVGA_MAIN_CONTROL                                                                             0x0014
#define regVGA_MAIN_CONTROL_BASE_IDX                                                                    1
#define regVGA_TEST_CONTROL                                                                             0x0015
#define regVGA_TEST_CONTROL_BASE_IDX                                                                    1
#define regVGA_QOS_CTRL                                                                                 0x0018
#define regVGA_QOS_CTRL_BASE_IDX                                                                        1
#define regCRTC8_IDX                                                                                    0x002d
#define regCRTC8_IDX_BASE_IDX                                                                           1
#define regCRTC8_DATA                                                                                   0x002d
#define regCRTC8_DATA_BASE_IDX                                                                          1
#define regGENFC_WT                                                                                     0x002e
#define regGENFC_WT_BASE_IDX                                                                            1
#define regGENS1                                                                                        0x002e
#define regGENS1_BASE_IDX                                                                               1
#define regATTRDW                                                                                       0x0030
#define regATTRDW_BASE_IDX                                                                              1
#define regATTRX                                                                                        0x0030
#define regATTRX_BASE_IDX                                                                               1
#define regATTRDR                                                                                       0x0030
#define regATTRDR_BASE_IDX                                                                              1
#define regGENMO_WT                                                                                     0x0030
#define regGENMO_WT_BASE_IDX                                                                            1
#define regGENS0                                                                                        0x0030
#define regGENS0_BASE_IDX                                                                               1
#define regGENENB                                                                                       0x0030
#define regGENENB_BASE_IDX                                                                              1
#define regSEQ8_IDX                                                                                     0x0031
#define regSEQ8_IDX_BASE_IDX                                                                            1
#define regSEQ8_DATA                                                                                    0x0031
#define regSEQ8_DATA_BASE_IDX                                                                           1
#define regDAC_MASK                                                                                     0x0031
#define regDAC_MASK_BASE_IDX                                                                            1
#define regDAC_R_INDEX                                                                                  0x0031
#define regDAC_R_INDEX_BASE_IDX                                                                         1
#define regDAC_W_INDEX                                                                                  0x0032
#define regDAC_W_INDEX_BASE_IDX                                                                         1
#define regDAC_DATA                                                                                     0x0032
#define regDAC_DATA_BASE_IDX                                                                            1
#define regGENFC_RD                                                                                     0x0032
#define regGENFC_RD_BASE_IDX                                                                            1
#define regGENMO_RD                                                                                     0x0033
#define regGENMO_RD_BASE_IDX                                                                            1
#define regGRPH8_IDX                                                                                    0x0033
#define regGRPH8_IDX_BASE_IDX                                                                           1
#define regGRPH8_DATA                                                                                   0x0033
#define regGRPH8_DATA_BASE_IDX                                                                          1
#define regCRTC8_IDX_1                                                                                  0x0035
#define regCRTC8_IDX_1_BASE_IDX                                                                         1
#define regCRTC8_DATA_1                                                                                 0x0035
#define regCRTC8_DATA_1_BASE_IDX                                                                        1
#define regGENFC_WT_1                                                                                   0x0036
#define regGENFC_WT_1_BASE_IDX                                                                          1
#define regGENS1_1                                                                                      0x0036
#define regGENS1_1_BASE_IDX                                                                             1
#define regD3VGA_CONTROL                                                                                0x0038
#define regD3VGA_CONTROL_BASE_IDX                                                                       1
#define regD4VGA_CONTROL                                                                                0x0039
#define regD4VGA_CONTROL_BASE_IDX                                                                       1
#define regD5VGA_CONTROL                                                                                0x003a
#define regD5VGA_CONTROL_BASE_IDX                                                                       1
#define regD6VGA_CONTROL                                                                                0x003b
#define regD6VGA_CONTROL_BASE_IDX                                                                       1
#define regVGA_SOURCE_SELECT                                                                            0x003c
#define regVGA_SOURCE_SELECT_BASE_IDX                                                                   1


// addressBlock: dcn_dc_mmhubbub_vgaif_dispdec
// base address: 0x0
#define regMCIF_CONTROL                                                                                 0x034a
#define regMCIF_CONTROL_BASE_IDX                                                                        2
#define regMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
#define regMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
#define regMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
#define regMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2


// addressBlock: dcn_dc_mmhubbub_mcif_wb0_dispdec
// base address: 0x0
#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274
#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
#define regMCIF_WB_BUF_PITCH                                                                            0x0275
#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276
#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277
#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278
#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279
#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a
#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b
#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c
#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d
#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f
#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
#define regMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280
#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2
#define regMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281
#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2
#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297
#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
#define regMCIF_WB_SECURITY_LEVEL                                                                       0x0298
#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX                                                              2
#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI                                                           0x02a7
#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX                                                  2
#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8
#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
#define regMCIF_WB_MIN_TTO                                                                              0x02a9
#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2


// addressBlock: dcn_dc_mmhubbub_mmhubbub_dispdec
// base address: 0x0
#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
#define regMCIF_WB_WATERMARK                                                                            0x02ab
#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2
#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
#define regMMHUBBUB_MIN_TTO                                                                             0x02b1
#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
#define regMMHUBBUB_CTRL                                                                                0x0333
#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2
#define regWBIF_SMU_WM_CONTROL                                                                          0x0334
#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
#define regWBIF0_MISC_CTRL                                                                              0x0335
#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2
#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336
#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337
#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
#define regVGA_SRC_SPLIT_CNTL                                                                           0x033e
#define regVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033f
#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x0340
#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0341
#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
#define regMMHUBBUB_SOFT_RESET                                                                          0x0342
#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
#define regDMU_IF_ERR_STATUS                                                                            0x0346
#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0347
#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0349
#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2


// addressBlock: dcn_dc_hda_azf0controller_dispdec
// base address: 0x0
#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
#define regAZALIA_AUDIO_DTO                                                                             0x03c3
#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5
#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
#define regAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3
#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4
#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5
#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6
#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
#define regAZALIA_CRC0_RESULT                                                                           0x03e7
#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8
#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9
#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea
#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb
#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
#define regAZALIA_CRC1_RESULT                                                                           0x03ec
#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee
#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef
#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2


// addressBlock: dcn_dc_hda_azf0root_dispdec
// base address: 0x0
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2


// addressBlock: dcn_dc_hda_az_misc_dispdec
// base address: 0x0
#define regAZ_CLOCK_CNTL                                                                                0x0372
#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2


// addressBlock: dcn_dc_hda_azf0stream0_dispdec
// base address: 0x0
#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream1_dispdec
// base address: 0x8
#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream2_dispdec
// base address: 0x10
#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream3_dispdec
// base address: 0x18
#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream4_dispdec
// base address: 0x20
#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream5_dispdec
// base address: 0x28
#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream6_dispdec
// base address: 0x30
#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream7_dispdec
// base address: 0x38
#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream8_dispdec
// base address: 0x320
#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream9_dispdec
// base address: 0x328
#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2


// addressBlock: dcn_dc_hda_azf0stream10_dispdec
// base address: 0x330
#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dcn_dc_hda_azf0stream11_dispdec
// base address: 0x338
#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dcn_dc_hda_azf0stream12_dispdec
// base address: 0x340
#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dcn_dc_hda_azf0stream13_dispdec
// base address: 0x348
#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dcn_dc_hda_azf0stream14_dispdec
// base address: 0x350
#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dcn_dc_hda_azf0stream15_dispdec
// base address: 0x358
#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2


// addressBlock: dcn_dc_hda_azf0endpoint0_dispdec
// base address: 0x0
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dcn_dc_hda_azf0endpoint1_dispdec
// base address: 0x18
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dcn_dc_hda_azf0endpoint2_dispdec
// base address: 0x30
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dcn_dc_hda_azf0endpoint3_dispdec
// base address: 0x48
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dcn_dc_hda_azf0endpoint4_dispdec
// base address: 0x60
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dcn_dc_hda_azf0endpoint5_dispdec
// base address: 0x78
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dcn_dc_hda_azf0endpoint6_dispdec
// base address: 0x90
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dcn_dc_hda_azf0endpoint7_dispdec
// base address: 0xa8
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2


// addressBlock: dcn_dc_hda_azf0inputendpoint0_dispdec
// base address: 0x0
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dcn_dc_hda_azf0inputendpoint1_dispdec
// base address: 0x10
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dcn_dc_hda_azf0inputendpoint2_dispdec
// base address: 0x20
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dcn_dc_hda_azf0inputendpoint3_dispdec
// base address: 0x30
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dcn_dc_hda_azf0inputendpoint4_dispdec
// base address: 0x40
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dcn_dc_hda_azf0inputendpoint5_dispdec
// base address: 0x50
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dcn_dc_hda_azf0inputendpoint6_dispdec
// base address: 0x60
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dcn_dc_hda_azf0inputendpoint7_dispdec
// base address: 0x70
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2


// addressBlock: dcn_dc_dchubbubl_hubbub_dispdec
// base address: 0x0
#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9
#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa
#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb
#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc
#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL                                                             0x04fd
#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX                                                    2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fe
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A                                                      0x04ff
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX                                             2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x0500
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x0501
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0502
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0503
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0504
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0505
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0506
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0507
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B                                                      0x0508
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX                                             2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x0509
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x050a
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050b
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050c
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050d
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x050e
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x050f
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0510
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C                                                      0x0511
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX                                             2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0512
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0513
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0514
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0515
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0516
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0517
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0518
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0519
#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D                                                      0x051a
#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX                                             2
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x051b
#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051c
#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051d
#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051e
#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051f
#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0520
#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0521
#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x0522
#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
#define regDCHUBBUB_ARB_MALL_CNTL                                                                       0x0523
#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX                                                              2
#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x0524
#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x0525
#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0526
#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0527
#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0528
#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0529
#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x052a
#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x052b
#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x052c
#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x052d
#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
#define regVTG0_CONTROL                                                                                 0x052e
#define regVTG0_CONTROL_BASE_IDX                                                                        2
#define regVTG1_CONTROL                                                                                 0x052f
#define regVTG1_CONTROL_BASE_IDX                                                                        2
#define regVTG2_CONTROL                                                                                 0x0530
#define regVTG2_CONTROL_BASE_IDX                                                                        2
#define regVTG3_CONTROL                                                                                 0x0531
#define regVTG3_CONTROL_BASE_IDX                                                                        2
#define regDCHUBBUB_SOFT_RESET                                                                          0x0532
#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
#define regDCHUBBUB_CLOCK_CNTL                                                                          0x0533
#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
#define regDCFCLK_CNTL                                                                                  0x0534
#define regDCFCLK_CNTL_BASE_IDX                                                                         2
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0535
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0536
#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0537
#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
#define regDCHUBBUB_CTRL_STATUS                                                                         0x0538
#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053e
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053f
#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x0540
#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
#define regFMON_CTRL                                                                                    0x0541
#define regFMON_CTRL_BASE_IDX                                                                           2


// addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec
// base address: 0x0
#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f
#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470
#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471
#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
#define regVM_REQUEST_PHYSICAL                                                                          0x0472
#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473
#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474
#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475
#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476
#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
#define regDCN_VM_FB_OFFSET                                                                             0x0477
#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
#define regDCN_VM_AGP_BOT                                                                               0x0478
#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2
#define regDCN_VM_AGP_TOP                                                                               0x0479
#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2
#define regDCN_VM_AGP_BASE                                                                              0x047a
#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2
#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b
#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c
#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d
#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x047e
#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2
#define regDCHUBBUB_SDPIF_PIPE_NOALLOC                                                                  0x047f
#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX                                                         2
#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x0480
#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2
#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL                                                          0x0481
#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX                                                 2
#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL                                                          0x0482
#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX                                                 2
#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL                                                            0x0483
#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX                                                   2
#define regSDPIF_REQUEST_RATE_LIMIT                                                                     0x0484
#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX                                                            2
#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0485
#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0486
#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2


// addressBlock: dcn_dc_dchubbubl_hubbub_ret_path_dispdec
// base address: 0x0
#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04af
#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04b0
#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
#define regDCHUBBUB_CRC_CTRL                                                                            0x04b1
#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04b2
#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04b3
#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04b4
#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04b5
#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04b6
#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2
#define regDCHUBBUB_DCC_STAT0                                                                           0x04b7
#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2
#define regDCHUBBUB_DCC_STAT1                                                                           0x04b8
#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2
#define regDCHUBBUB_DCC_STAT2                                                                           0x04b9
#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2
#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04ba
#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2
#define regDCHUBBUB_DET0_CTRL                                                                           0x04bb
#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2
#define regDCHUBBUB_DET1_CTRL                                                                           0x04bc
#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2
#define regDCHUBBUB_DET2_CTRL                                                                           0x04bd
#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2
#define regDCHUBBUB_DET3_CTRL                                                                           0x04be
#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2
#define regDCHUBBUB_DEBUG_CTRL_0                                                                        0x04c5
#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                                               2
#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0
#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2
#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1
#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2
#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04c2
#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2
#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04c3
#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
#define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4
#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2


// addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec
// base address: 0x0
#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559
#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560
#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567
#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e
#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575
#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c
#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583
#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a
#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591
#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598
#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f
#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
#define regDCN_VM_FAULT_CNTL                                                                            0x05cb
#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
#define regDCN_VM_FAULT_STATUS                                                                          0x05cc
#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2


// addressBlock: dcn_dc_dcbubp0_dispdec_hubp_dispdec
// base address: 0x0
#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3
#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
#define regHUBP0_DCHUBP_MALL_CONFIG                                                                     0x05f6
#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
#define regHUBP0_DCHUBP_MALL_SUB_VP                                                                     0x05f7
#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f8
#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f9
#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fd
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fe
#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
#define regHUBP0_HUBP_MALL_STATUS                                                                       0x05ff
#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX                                                              2


// addressBlock: dcn_dc_dcbubp0_dispdec_hubpreq_dispdec
// base address: 0x0
#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x061f
#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0620
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0621
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0622
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0623
#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0624
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0625
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0626
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0627
#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0628
#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x0629
#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062a
#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062b
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062c
#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062d
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062e
#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x062f
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0630
#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0631
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0632
#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0633
#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0634
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0635
#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0642
#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0643
#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0644
#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0645
#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0646
#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0647
#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0648
#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x0649
#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064a
#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064b
#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064c
#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064d
#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064e
#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x064f
#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0650
#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0651
#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0652
#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0653
#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0654
#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0655
#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0656
#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0657
#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0658
#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x0659
#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065a
#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065b
#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065c
#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065d
#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065e
#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x065f
#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0662
#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0663
#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0664
#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0665
#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0666
#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0667
#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
#define regHUBPREQ0_UCLK_PSTATE_FORCE                                                                   0x0668
#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
#define regHUBPREQ0_HUBPREQ_STATUS_REG0                                                                 0x0669
#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
#define regHUBPREQ0_HUBPREQ_STATUS_REG1                                                                 0x066a
#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
#define regHUBPREQ0_HUBPREQ_STATUS_REG2                                                                 0x066b
#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2


// addressBlock: dcn_dc_dcbubp0_dispdec_hubpret_dispdec
// base address: 0x0
#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2


// addressBlock: dcn_dc_dcbubp0_dispdec_cursor0_dispdec
// base address: 0x0
#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b
#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c
#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684
#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686
#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2



// addressBlock: dcn_dc_dcbubp1_dispdec_hubp_dispdec
// base address: 0x370
#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf
#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
#define regHUBP1_DCHUBP_MALL_CONFIG                                                                     0x06d2
#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
#define regHUBP1_DCHUBP_MALL_SUB_VP                                                                     0x06d3
#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d4
#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d5
#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d9
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06da
#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
#define regHUBP1_HUBP_MALL_STATUS                                                                       0x06db
#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX                                                              2


// addressBlock: dcn_dc_dcbubp1_dispdec_hubpreq_dispdec
// base address: 0x370
#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fb
#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fc
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fd
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06fe
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x06ff
#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0700
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0701
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0702
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0703
#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0704
#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0705
#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0706
#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0707
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0708
#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x0709
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070a
#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070b
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070c
#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070d
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070e
#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x070f
#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0710
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0711
#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071e
#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x071f
#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0720
#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0721
#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0722
#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0723
#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0724
#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0725
#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0726
#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0727
#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0728
#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x0729
#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072a
#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072b
#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072c
#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072d
#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072e
#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x072f
#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0730
#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0731
#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0732
#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0733
#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0734
#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0735
#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0736
#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0737
#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0738
#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x0739
#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073a
#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073b
#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073e
#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x073f
#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0740
#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0741
#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0742
#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0743
#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
#define regHUBPREQ1_UCLK_PSTATE_FORCE                                                                   0x0744
#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
#define regHUBPREQ1_HUBPREQ_STATUS_REG0                                                                 0x0745
#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
#define regHUBPREQ1_HUBPREQ_STATUS_REG1                                                                 0x0746
#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
#define regHUBPREQ1_HUBPREQ_STATUS_REG2                                                                 0x0747
#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2


// addressBlock: dcn_dc_dcbubp1_dispdec_hubpret_dispdec
// base address: 0x370
#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2


// addressBlock: dcn_dc_dcbubp1_dispdec_cursor0_dispdec
// base address: 0x370
#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757
#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758
#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760
#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762
#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2


// addressBlock: dcn_dc_dcbubp2_dispdec_hubp_dispdec
// base address: 0x6e0
#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab
#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
#define regHUBP2_DCHUBP_MALL_CONFIG                                                                     0x07ae
#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
#define regHUBP2_DCHUBP_MALL_SUB_VP                                                                     0x07af
#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07b0
#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07b1
#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b5
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b6
#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
#define regHUBP2_HUBP_MALL_STATUS                                                                       0x07b7
#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX                                                              2


// addressBlock: dcn_dc_dcbubp2_dispdec_hubpreq_dispdec
// base address: 0x6e0
#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d7
#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d8
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07d9
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07da
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07db
#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dc
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07dd
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07de
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07df
#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e0
#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e1
#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e2
#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e3
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e4
#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e5
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e6
#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e7
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e8
#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07e9
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ea
#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07eb
#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ec
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ed
#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fa
#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fb
#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fc
#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fd
#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07fe
#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x07ff
#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0800
#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0801
#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0802
#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0803
#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0804
#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0805
#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0806
#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0807
#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0808
#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x0809
#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080a
#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080b
#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080c
#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080d
#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080e
#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x080f
#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0810
#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0811
#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0812
#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0813
#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0814
#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0815
#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0816
#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0817
#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081a
#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081b
#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081c
#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081d
#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081e
#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x081f
#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
#define regHUBPREQ2_UCLK_PSTATE_FORCE                                                                   0x0820
#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
#define regHUBPREQ2_HUBPREQ_STATUS_REG0                                                                 0x0821
#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
#define regHUBPREQ2_HUBPREQ_STATUS_REG1                                                                 0x0822
#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
#define regHUBPREQ2_HUBPREQ_STATUS_REG2                                                                 0x0823
#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2


// addressBlock: dcn_dc_dcbubp2_dispdec_hubpret_dispdec
// base address: 0x6e0
#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2


// addressBlock: dcn_dc_dcbubp2_dispdec_cursor0_dispdec
// base address: 0x6e0
#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833
#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834
#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c
#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e
#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2


// addressBlock: dcn_dc_dcbubp3_dispdec_hubp_dispdec
// base address: 0xa50
#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
#define regHUBP3_DCHUBP_CNTL                                                                            0x0887
#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888
#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
#define regHUBP3_DCHUBP_MALL_CONFIG                                                                     0x088a
#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
#define regHUBP3_DCHUBP_MALL_SUB_VP                                                                     0x088b
#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088c
#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088d
#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0891
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0892
#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
#define regHUBP3_HUBP_MALL_STATUS                                                                       0x0893
#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX                                                              2


// addressBlock: dcn_dc_dcbubp3_dispdec_hubpreq_dispdec
// base address: 0xa50
#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b3
#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b4
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b5
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b6
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b7
#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b8
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08b9
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08ba
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bb
#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bc
#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08bd
#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08be
#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08bf
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c0
#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c1
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c2
#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c3
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c4
#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c5
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c6
#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c7
#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c8
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08c9
#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d6
#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d7
#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d8
#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08d9
#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08da
#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08db
#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dc
#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08dd
#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08de
#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08df
#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e0
#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e1
#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e2
#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e3
#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e4
#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e5
#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e6
#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e7
#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e8
#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08e9
#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ea
#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08eb
#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ec
#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ed
#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ee
#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08ef
#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f0
#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f1
#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f2
#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f3
#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f6
#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f7
#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f8
#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08f9
#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fa
#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fb
#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
#define regHUBPREQ3_UCLK_PSTATE_FORCE                                                                   0x08fc
#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
#define regHUBPREQ3_HUBPREQ_STATUS_REG0                                                                 0x08fd
#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
#define regHUBPREQ3_HUBPREQ_STATUS_REG1                                                                 0x08fe
#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
#define regHUBPREQ3_HUBPREQ_STATUS_REG2                                                                 0x08ff
#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2


// addressBlock: dcn_dc_dcbubp3_dispdec_hubpret_dispdec
// base address: 0xa50
#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2


// addressBlock: dcn_dc_dcbubp3_dispdec_cursor0_dispdec
// base address: 0xa50
#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f
#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910
#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918
#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a
#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2


// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cfg_dispdec
// base address: 0x0
#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2


// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cur_dispdec
// base address: 0x0
#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2


// addressBlock: dcn_dc_dpp0_dispdec_dscl_dispdec
// base address: 0x0
#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
#define regDSCL0_SCL_MODE                                                                               0x0cfb
#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2
#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd
#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b
#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f
#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
#define regDSCL0_OTG_V_BLANK                                                                            0x0d10
#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
#define regDSCL0_RECOUT_START                                                                           0x0d11
#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2
#define regDSCL0_RECOUT_SIZE                                                                            0x0d12
#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
#define regDSCL0_MPC_SIZE                                                                               0x0d13
#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2
#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14
#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
#define regDSCL0_LB_V_COUNTER                                                                           0x0d16
#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
#define regDSCL0_OBUF_CONTROL                                                                           0x0d19
#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2


// addressBlock: dcn_dc_dpp0_dispdec_cm_dispdec
// base address: 0x0
#define regCM0_CM_CONTROL                                                                               0x0d20
#define regCM0_CM_CONTROL_BASE_IDX                                                                      2
#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b
#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
#define regCM0_CM_HDR_MULT_COEF                                                                         0x0d87
#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0d88
#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0d89
#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
#define regCM0_CM_DEALPHA                                                                               0x0d8b
#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2
#define regCM0_CM_COEF_FORMAT                                                                           0x0d8c
#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2


// addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec
// base address: 0x0
#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2


// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cfg_dispdec
// base address: 0x5ac
#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2


// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cur_dispdec
// base address: 0x5ac
#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2


// addressBlock: dcn_dc_dpp1_dispdec_dscl_dispdec
// base address: 0x5ac
#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
#define regDSCL1_SCL_MODE                                                                               0x0e66
#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2
#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
#define regDSCL1_DSCL_CONTROL                                                                           0x0e68
#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
#define regDSCL1_DSCL_UPDATE                                                                            0x0e76
#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77
#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a
#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b
#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
#define regDSCL1_RECOUT_START                                                                           0x0e7c
#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2
#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d
#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
#define regDSCL1_MPC_SIZE                                                                               0x0e7e
#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2
#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
#define regDSCL1_LB_V_COUNTER                                                                           0x0e81
#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
#define regDSCL1_OBUF_CONTROL                                                                           0x0e84
#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2


// addressBlock: dcn_dc_dpp1_dispdec_cm_dispdec
// base address: 0x5ac
#define regCM1_CM_CONTROL                                                                               0x0e8b
#define regCM1_CM_CONTROL_BASE_IDX                                                                      2
#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6
#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
#define regCM1_CM_HDR_MULT_COEF                                                                         0x0ef2
#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0ef3
#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0ef4
#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
#define regCM1_CM_DEALPHA                                                                               0x0ef6
#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2
#define regCM1_CM_COEF_FORMAT                                                                           0x0ef7
#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2


// addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec
// base address: 0x5ac
#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30
#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2


// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cfg_dispdec
// base address: 0xb58
#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2


// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cur_dispdec
// base address: 0xb58
#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2


// addressBlock: dcn_dc_dpp2_dispdec_dscl_dispdec
// base address: 0xb58
#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
#define regDSCL2_SCL_MODE                                                                               0x0fd1
#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2
#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3
#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1
#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5
#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6
#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
#define regDSCL2_RECOUT_START                                                                           0x0fe7
#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2
#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8
#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
#define regDSCL2_MPC_SIZE                                                                               0x0fe9
#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2
#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea
#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
#define regDSCL2_LB_V_COUNTER                                                                           0x0fec
#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
#define regDSCL2_OBUF_CONTROL                                                                           0x0fef
#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2


// addressBlock: dcn_dc_dpp2_dispdec_cm_dispdec
// base address: 0xb58
#define regCM2_CM_CONTROL                                                                               0x0ff6
#define regCM2_CM_CONTROL_BASE_IDX                                                                      2
#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
#define regCM2_CM_BIAS_CR_R                                                                             0x1011
#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013
#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
#define regCM2_CM_HDR_MULT_COEF                                                                         0x105d
#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
#define regCM2_CM_MEM_PWR_CTRL                                                                          0x105e
#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regCM2_CM_MEM_PWR_STATUS                                                                        0x105f
#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
#define regCM2_CM_DEALPHA                                                                               0x1061
#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2
#define regCM2_CM_COEF_FORMAT                                                                           0x1062
#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2


// addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec
// base address: 0xb58
#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2


// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cfg_dispdec
// base address: 0x1104
#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e
#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f
#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2


// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cur_dispdec
// base address: 0x1104
#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2


// addressBlock: dcn_dc_dpp3_dispdec_dscl_dispdec
// base address: 0x1104
#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
#define regDSCL3_SCL_MODE                                                                               0x113c
#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2
#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d
#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
#define regDSCL3_DSCL_CONTROL                                                                           0x113e
#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b
#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
#define regDSCL3_DSCL_UPDATE                                                                            0x114c
#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d
#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
#define regDSCL3_OTG_H_BLANK                                                                            0x1150
#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
#define regDSCL3_OTG_V_BLANK                                                                            0x1151
#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
#define regDSCL3_RECOUT_START                                                                           0x1152
#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2
#define regDSCL3_RECOUT_SIZE                                                                            0x1153
#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
#define regDSCL3_MPC_SIZE                                                                               0x1154
#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2
#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155
#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156
#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
#define regDSCL3_LB_V_COUNTER                                                                           0x1157
#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
#define regDSCL3_OBUF_CONTROL                                                                           0x115a
#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2


// addressBlock: dcn_dc_dpp3_dispdec_cm_dispdec
// base address: 0x1104
#define regCM3_CM_CONTROL                                                                               0x1161
#define regCM3_CM_CONTROL_BASE_IDX                                                                      2
#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162
#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163
#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164
#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165
#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166
#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167
#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168
#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
#define regCM3_CM_BIAS_CR_R                                                                             0x117c
#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e
#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
#define regCM3_CM_HDR_MULT_COEF                                                                         0x11c8
#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
#define regCM3_CM_MEM_PWR_CTRL                                                                          0x11c9
#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
#define regCM3_CM_MEM_PWR_STATUS                                                                        0x11ca
#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
#define regCM3_CM_DEALPHA                                                                               0x11cc
#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2
#define regCM3_CM_COEF_FORMAT                                                                           0x11cd
#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2


// addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec
// base address: 0x1104
#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106
#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2


// addressBlock: dcn_dc_mpc_mpcc0_dispdec
// base address: 0x0
#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000
#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001
#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
#define regMPCC0_MPCC_OPP_ID                                                                            0x0002
#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
#define regMPCC0_MPCC_CONTROL                                                                           0x0003
#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004
#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006
#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0009
#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
#define regMPCC0_MPCC_BG_R_CR                                                                           0x000a
#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
#define regMPCC0_MPCC_BG_G_Y                                                                            0x000b
#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
#define regMPCC0_MPCC_BG_B_CB                                                                           0x000c
#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000d
#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
#define regMPCC0_MPCC_STATUS                                                                            0x000e
#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3


// addressBlock: dcn_dc_mpc_mpcc1_dispdec
// base address: 0x54
#define regMPCC1_MPCC_TOP_SEL                                                                           0x0015
#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
#define regMPCC1_MPCC_BOT_SEL                                                                           0x0016
#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
#define regMPCC1_MPCC_OPP_ID                                                                            0x0017
#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
#define regMPCC1_MPCC_CONTROL                                                                           0x0018
#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0019
#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x001a
#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
#define regMPCC1_MPCC_TOP_GAIN                                                                          0x001b
#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x001c
#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x001d
#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x001e
#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
#define regMPCC1_MPCC_BG_R_CR                                                                           0x001f
#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
#define regMPCC1_MPCC_BG_G_Y                                                                            0x0020
#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
#define regMPCC1_MPCC_BG_B_CB                                                                           0x0021
#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x0022
#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
#define regMPCC1_MPCC_STATUS                                                                            0x0023
#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3


// addressBlock: dcn_dc_mpc_mpcc2_dispdec
// base address: 0xa8
#define regMPCC2_MPCC_TOP_SEL                                                                           0x002a
#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
#define regMPCC2_MPCC_BOT_SEL                                                                           0x002b
#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
#define regMPCC2_MPCC_OPP_ID                                                                            0x002c
#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
#define regMPCC2_MPCC_CONTROL                                                                           0x002d
#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
#define regMPCC2_MPCC_SM_CONTROL                                                                        0x002e
#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x002f
#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0030
#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0031
#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0032
#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0033
#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
#define regMPCC2_MPCC_BG_R_CR                                                                           0x0034
#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
#define regMPCC2_MPCC_BG_G_Y                                                                            0x0035
#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
#define regMPCC2_MPCC_BG_B_CB                                                                           0x0036
#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x0037
#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
#define regMPCC2_MPCC_STATUS                                                                            0x0038
#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3


// addressBlock: dcn_dc_mpc_mpcc3_dispdec
// base address: 0xfc
#define regMPCC3_MPCC_TOP_SEL                                                                           0x003f
#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
#define regMPCC3_MPCC_BOT_SEL                                                                           0x0040
#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
#define regMPCC3_MPCC_OPP_ID                                                                            0x0041
#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
#define regMPCC3_MPCC_CONTROL                                                                           0x0042
#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0043
#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0044
#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0045
#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0046
#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0047
#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0048
#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
#define regMPCC3_MPCC_BG_R_CR                                                                           0x0049
#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
#define regMPCC3_MPCC_BG_G_Y                                                                            0x004a
#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
#define regMPCC3_MPCC_BG_B_CB                                                                           0x004b
#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x004c
#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
#define regMPCC3_MPCC_STATUS                                                                            0x004d
#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3


// addressBlock: dcn_dc_mpc_mpc_cfg_dispdec
// base address: 0x0
#define regMPC_CLOCK_CONTROL                                                                            0x0398
#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
#define regMPC_SOFT_RESET                                                                               0x0399
#define regMPC_SOFT_RESET_BASE_IDX                                                                      3
#define regMPC_CRC_CTRL                                                                                 0x039a
#define regMPC_CRC_CTRL_BASE_IDX                                                                        3
#define regMPC_CRC_SEL_CONTROL                                                                          0x039b
#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
#define regMPC_CRC_RESULT_AR                                                                            0x039c
#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
#define regMPC_CRC_RESULT_GB                                                                            0x039d
#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
#define regMPC_CRC_RESULT_C                                                                             0x039e
#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3
#define regMPC_BYPASS_BG_AR                                                                             0x03a2
#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
#define regMPC_BYPASS_BG_GB                                                                             0x03a3
#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
#define regMPC_HOST_READ_CONTROL                                                                        0x03a4
#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
#define regMPC_DPP_PENDING_STATUS                                                                       0x03a5
#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
#define regMPC_PENDING_STATUS_MISC                                                                      0x03a6
#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x03a7
#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x03a8
#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
#define regADR_VUPDATE_LOCK_SET0                                                                        0x03a9
#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
#define regCFG_VUPDATE_LOCK_SET0                                                                        0x03aa
#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
#define regCUR_VUPDATE_LOCK_SET0                                                                        0x03ab
#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x03ac
#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x03ad
#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
#define regADR_VUPDATE_LOCK_SET1                                                                        0x03ae
#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
#define regCFG_VUPDATE_LOCK_SET1                                                                        0x03af
#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
#define regCUR_VUPDATE_LOCK_SET1                                                                        0x03b0
#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x03b1
#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x03b2
#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
#define regADR_VUPDATE_LOCK_SET2                                                                        0x03b3
#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
#define regCFG_VUPDATE_LOCK_SET2                                                                        0x03b4
#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
#define regCUR_VUPDATE_LOCK_SET2                                                                        0x03b5
#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x03b6
#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x03b7
#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
#define regADR_VUPDATE_LOCK_SET3                                                                        0x03b8
#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
#define regCFG_VUPDATE_LOCK_SET3                                                                        0x03b9
#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
#define regCUR_VUPDATE_LOCK_SET3                                                                        0x03ba
#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
#define regMPC_DWB0_MUX                                                                                 0x03c6
#define regMPC_DWB0_MUX_BASE_IDX                                                                        3


// addressBlock: dcn_dc_mpc_mpcc_ogam0_dispdec
// base address: 0x0
#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x00a8
#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x00a9
#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x00aa
#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x00ab
#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x00ac
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x00ad
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x00ae
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x00af
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x00b0
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x00b1
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x00b2
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x00b3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x00b4
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x00b5
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x00b6
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x00b7
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x00b8
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x00b9
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x00ba
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x00bb
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x00bc
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x00bd
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x00be
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x00bf
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x00c0
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x00c1
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x00c2
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x00c3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x00c4
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x00c5
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x00c6
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x00c7
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x00c8
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x00c9
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00ca
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00cb
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x00cc
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x00cd
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x00ce
#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x00cf
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x00d0
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x00d1
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x00d2
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x00d3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x00d4
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x00d5
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x00d6
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x00d7
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x00d8
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x00d9
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x00da
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x00db
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x00dc
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x00dd
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x00de
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x00df
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x00e0
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x00e1
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x00e2
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x00e3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x00e4
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x00e5
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x00e6
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x00e7
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x00e8
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x00e9
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x00ea
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x00eb
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x00ec
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x00ed
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x00ee
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x00ef
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x00f0
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x00f1
#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x00f2
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x00f3
#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x00f4
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x00f5
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x00f6
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x00f7
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x00f8
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x00f9
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x00fa
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x00fb
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x00fc
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x00fd
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x00fe
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x00ff
#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3


// addressBlock: dcn_dc_mpc_mpcc_ogam1_dispdec
// base address: 0x178
#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0106
#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0107
#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0108
#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0109
#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x010a
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x010b
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x010c
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x010d
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x010e
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x010f
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0110
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0111
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0112
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0113
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0114
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0115
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0116
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0117
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0118
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0119
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x011a
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x011b
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x011c
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x011d
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x011e
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x011f
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0120
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0121
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0122
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0123
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0124
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0125
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0126
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0127
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0128
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0129
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x012a
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x012b
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x012c
#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x012d
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x012e
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x012f
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0130
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0131
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0132
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0133
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0134
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0135
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0136
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0137
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0138
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0139
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x013a
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x013b
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x013c
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x013d
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x013e
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x013f
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0140
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0141
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0142
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0143
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0144
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0145
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0146
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0147
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0148
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0149
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x014a
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x014b
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x014c
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x014d
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x014e
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x014f
#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0150
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x0151
#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0152
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0153
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0154
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0155
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0156
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0157
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0158
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0159
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x015a
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x015b
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x015c
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x015d
#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3


// addressBlock: dcn_dc_mpc_mpcc_ogam2_dispdec
// base address: 0x2f0
#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0164
#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0165
#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0166
#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0167
#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0168
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0169
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x016a
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x016b
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x016c
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x016d
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x016e
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x016f
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0170
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0171
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0172
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0173
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0174
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0175
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0176
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0177
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0178
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0179
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x017a
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x017b
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x017c
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x017d
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x017e
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x017f
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0180
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0181
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0182
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0183
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0184
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0185
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0186
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0187
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0188
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0189
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x018a
#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x018b
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x018c
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x018d
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x018e
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x018f
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0190
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0191
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0192
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0193
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0194
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0195
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0196
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0197
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0198
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0199
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x019a
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x019b
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x019c
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x019d
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x019e
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x019f
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01a0
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01a1
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01a2
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01a3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01a4
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01a5
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01a6
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01a7
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01a8
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01a9
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01aa
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01ab
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01ac
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01ad
#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ae
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x01af
#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01b0
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01b1
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01b2
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01b3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01b4
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01b5
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01b6
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01b7
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01b8
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01b9
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01ba
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01bb
#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3


// addressBlock: dcn_dc_mpc_mpcc_ogam3_dispdec
// base address: 0x468
#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x01c2
#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x01c3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x01c4
#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x01c5
#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x01c6
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x01c7
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x01c8
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x01c9
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x01ca
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x01cb
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x01cc
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x01cd
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x01ce
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x01cf
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x01d0
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x01d1
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x01d2
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x01d3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x01d4
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x01d5
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x01d6
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x01d7
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x01d8
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x01d9
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x01da
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x01db
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x01dc
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x01dd
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x01de
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x01df
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x01e0
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x01e1
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01e2
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01e3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01e4
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01e5
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01e6
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01e7
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01e8
#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01e9
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01ea
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01eb
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01ec
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ed
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ee
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ef
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01f0
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01f1
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01f2
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01f3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01f4
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01f5
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01f6
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01f7
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01f8
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01f9
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01fa
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01fb
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01fc
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01fd
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01fe
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01ff
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0200
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0201
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0202
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0203
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0204
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0205
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0206
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0207
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0208
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0209
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x020a
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x020b
#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX