/* SPDX-License-Identifier: GPL-2.0-only */
/****************************************************************************
 * Driver for Solarflare network controllers and boards
 * Copyright 2009-2018 Solarflare Communications Inc.
 * Copyright 2019-2020 Xilinx Inc.
 */


#ifndef MCDI_PCOL_H
#define MCDI_PCOL_H

/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
/* Power-on reset state */
#define MC_FW_STATE_POR (1)
/* If this is set in MC_RESET_STATE_REG then it should be
 * possible to jump into IMEM without loading code from flash. */
#define MC_FW_WARM_BOOT_OK (2)
/* The MC main image has started to boot. */
#define MC_FW_STATE_BOOTING (4)
/* The Scheduler has started. */
#define MC_FW_STATE_SCHED (8)
/* If this is set in MC_RESET_STATE_REG then it should be
 * possible to jump into IMEM without loading code from flash.
 * Unlike a warm boot, assume DMEM has been reloaded, so that
 * the MC persistent data must be reinitialised. */
#define MC_FW_TEPID_BOOT_OK (16)
/* We have entered the main firmware via recovery mode.  This
 * means that MC persistent data must be reinitialised, but that
 * we shouldn't touch PCIe config. */
#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)
/* BIST state has been initialized */
#define MC_FW_BIST_INIT_OK (128)

/* Siena MC shared memmory offsets */
/* The 'doorbell' addresses are hard-wired to alert the MC when written */
#define	MC_SMEM_P0_DOORBELL_OFST	0x000
#define	MC_SMEM_P1_DOORBELL_OFST	0x004
/* The rest of these are firmware-defined */
#define	MC_SMEM_P0_PDU_OFST		0x008
#define	MC_SMEM_P1_PDU_OFST		0x108
#define	MC_SMEM_PDU_LEN			0x100
#define	MC_SMEM_P0_PTP_TIME_OFST	0x7f0
#define	MC_SMEM_P0_STATUS_OFST		0x7f8
#define	MC_SMEM_P1_STATUS_OFST		0x7fc

/* Values to be written to the per-port status dword in shared
 * memory on reboot and assert */
#define MC_STATUS_DWORD_REBOOT (0xb007b007)
#define MC_STATUS_DWORD_ASSERT (0xdeaddead)

/* Check whether an mcfw version (in host order) belongs to a bootloader */
#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)

/* The current version of the MCDI protocol.
 *
 * Note that the ROM burnt into the card only talks V0, so at the very
 * least every driver must support version 0 and MCDI_PCOL_VERSION
 */
#define MCDI_PCOL_VERSION 2

/* Unused commands: 0x23, 0x27, 0x30, 0x31 */

/* MCDI version 1
 *
 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
 * structure, filled in by the client.
 *
 *       0       7  8     16    20     22  23  24    31
 *      | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
 *               |                      |   |
 *               |                      |   \--- Response
 *               |                      \------- Error
 *               \------------------------------ Resync (always set)
 *
 * The client writes it's request into MC shared memory, and rings the
 * doorbell. Each request is completed by either by the MC writing
 * back into shared memory, or by writing out an event.
 *
 * All MCDI commands support completion by shared memory response. Each
 * request may also contain additional data (accounted for by HEADER.LEN),
 * and some response's may also contain additional data (again, accounted
 * for by HEADER.LEN).
 *
 * Some MCDI commands support completion by event, in which any associated
 * response data is included in the event.
 *
 * The protocol requires one response to be delivered for every request, a
 * request should not be sent unless the response for the previous request
 * has been received (either by polling shared memory, or by receiving
 * an event).
 */

/** Request/Response structure */
#define MCDI_HEADER_OFST 0
#define MCDI_HEADER_CODE_LBN 0
#define MCDI_HEADER_CODE_WIDTH 7
#define MCDI_HEADER_RESYNC_LBN 7
#define MCDI_HEADER_RESYNC_WIDTH 1
#define MCDI_HEADER_DATALEN_LBN 8
#define MCDI_HEADER_DATALEN_WIDTH 8
#define MCDI_HEADER_SEQ_LBN 16
#define MCDI_HEADER_SEQ_WIDTH 4
#define MCDI_HEADER_RSVD_LBN 20
#define MCDI_HEADER_RSVD_WIDTH 1
#define MCDI_HEADER_NOT_EPOCH_LBN 21
#define MCDI_HEADER_NOT_EPOCH_WIDTH 1
#define MCDI_HEADER_ERROR_LBN 22
#define MCDI_HEADER_ERROR_WIDTH 1
#define MCDI_HEADER_RESPONSE_LBN 23
#define MCDI_HEADER_RESPONSE_WIDTH 1
#define MCDI_HEADER_XFLAGS_LBN 24
#define MCDI_HEADER_XFLAGS_WIDTH 8
/* Request response using event */
#define MCDI_HEADER_XFLAGS_EVREQ 0x01
/* Request (and signal) early doorbell return */
#define MCDI_HEADER_XFLAGS_DBRET 0x02

/* Maximum number of payload bytes */
#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
#define MCDI_CTL_SDU_LEN_MAX_V2 0x400

#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2


/* The MC can generate events for two reasons:
 *   - To advance a shared memory request if XFLAGS_EVREQ was set
 *   - As a notification (link state, i2c event), controlled
 *     via MC_CMD_LOG_CTRL
 *
 * Both events share a common structure:
 *
 *  0      32     33      36    44     52     60
 * | Data | Cont | Level | Src | Code | Rsvd |
 *           |
 *           \ There is another event pending in this notification
 *
 * If Code==CMDDONE, then the fields are further interpreted as:
 *
 *   - LEVEL==INFO    Command succeeded
 *   - LEVEL==ERR     Command failed
 *
 *    0     8         16      24     32
 *   | Seq | Datalen | Errno | Rsvd |
 *
 *   These fields are taken directly out of the standard MCDI header, i.e.,
 *   LEVEL==ERR, Datalen == 0 => Reboot
 *
 * Events can be squirted out of the UART (using LOG_CTRL) without a
 * MCDI header.  An event can be distinguished from a MCDI response by
 * examining the first byte which is 0xc0.  This corresponds to the
 * non-existent MCDI command MC_CMD_DEBUG_LOG.
 *
 *      0         7        8
 *     | command | Resync |     = 0xc0
 *
 * Since the event is written in big-endian byte order, this works
 * providing bits 56-63 of the event are 0xc0.
 *
 *      56     60  63
 *     | Rsvd | Code |    = 0xc0
 *
 * Which means for convenience the event code is 0xc for all MC
 * generated events.
 */
#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc


#define MC_CMD_ERR_CODE_OFST 0
#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4

/* We define 8 "escape" commands to allow
   for command number space extension */

#define MC_CMD_CMD_SPACE_ESCAPE_0	      0x78
#define MC_CMD_CMD_SPACE_ESCAPE_1	      0x79
#define MC_CMD_CMD_SPACE_ESCAPE_2	      0x7A
#define MC_CMD_CMD_SPACE_ESCAPE_3	      0x7B
#define MC_CMD_CMD_SPACE_ESCAPE_4	      0x7C
#define MC_CMD_CMD_SPACE_ESCAPE_5	      0x7D
#define MC_CMD_CMD_SPACE_ESCAPE_6	      0x7E
#define MC_CMD_CMD_SPACE_ESCAPE_7	      0x7F

/* Vectors in the boot ROM */
/* Point to the copycode entry point. */
#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
/* Points to the recovery mode entry point. Misnamed but kept for compatibility. */
#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
/* Points to the recovery mode entry point. Same as above, but the right name. */
#define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
#define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
#define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)

/* Points to noflash mode entry point. */
#define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)

/* The command set exported by the boot ROM (MCDI v0) */
#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS {		\
	(1 << MC_CMD_READ32)	|			\
	(1 << MC_CMD_WRITE32)	|			\
	(1 << MC_CMD_COPYCODE)	|			\
	(1 << MC_CMD_GET_VERSION),			\
	0, 0, 0 }

#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x)		\
	(MC_CMD_SENSOR_ENTRY_OFST + (_x))

#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n)		\
	(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +		\
	 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST +		\
	 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)

#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n)		\
	(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +		\
	 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST +	\
	 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)

#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n)		\
	(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +		\
	 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST +		\
	 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)

/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
 * stack ID (which must be in the range 1-255) along with an EVB port ID.
 */
#define EVB_STACK_ID(n)  (((n) & 0xff) << 16)


/* Version 2 adds an optional argument to error returns: the errno value
 * may be followed by the (0-based) number of the first argument that
 * could not be processed.
 */
#define MC_CMD_ERR_ARG_OFST 4

/* MC_CMD_ERR enum: Public MCDI error codes. Error codes that correspond to
 * POSIX errnos should use the same numeric values that linux does. Error codes
 * specific to Solarflare firmware should use values in the range 0x1000 -
 * 0x10ff. The range 0x2000 - 0x20ff is reserved for private error codes (see
 * MC_CMD_ERR_PRIV below).
 */
/* enum: Operation not permitted. */
#define          MC_CMD_ERR_EPERM 0x1
/* enum: Non-existent command target */
#define          MC_CMD_ERR_ENOENT 0x2
/* enum: assert() has killed the MC */
#define          MC_CMD_ERR_EINTR 0x4
/* enum: I/O failure */
#define          MC_CMD_ERR_EIO 0x5
/* enum: Already exists */
#define          MC_CMD_ERR_EEXIST 0x6
/* enum: Try again */
#define          MC_CMD_ERR_EAGAIN 0xb
/* enum: Out of memory */
#define          MC_CMD_ERR_ENOMEM 0xc
/* enum: Caller does not hold required locks */
#define          MC_CMD_ERR_EACCES 0xd
/* enum: Resource is currently unavailable (e.g. lock contention) */
#define          MC_CMD_ERR_EBUSY 0x10
/* enum: No such device */
#define          MC_CMD_ERR_ENODEV 0x13
/* enum: Invalid argument to target */
#define          MC_CMD_ERR_EINVAL 0x16
/* enum: No space */
#define          MC_CMD_ERR_ENOSPC 0x1c
/* enum: Read-only */
#define          MC_CMD_ERR_EROFS 0x1e
/* enum: Broken pipe */
#define          MC_CMD_ERR_EPIPE 0x20
/* enum: Out of range */
#define          MC_CMD_ERR_ERANGE 0x22
/* enum: Non-recursive resource is already acquired */
#define          MC_CMD_ERR_EDEADLK 0x23
/* enum: Operation not implemented */
#define          MC_CMD_ERR_ENOSYS 0x26
/* enum: Operation timed out */
#define          MC_CMD_ERR_ETIME 0x3e
/* enum: Link has been severed */
#define          MC_CMD_ERR_ENOLINK 0x43
/* enum: Protocol error */
#define          MC_CMD_ERR_EPROTO 0x47
/* enum: Bad message */
#define          MC_CMD_ERR_EBADMSG 0x4a
/* enum: Operation not supported */
#define          MC_CMD_ERR_ENOTSUP 0x5f
/* enum: Address not available */
#define          MC_CMD_ERR_EADDRNOTAVAIL 0x63
/* enum: Not connected */
#define          MC_CMD_ERR_ENOTCONN 0x6b
/* enum: Operation already in progress */
#define          MC_CMD_ERR_EALREADY 0x72
/* enum: Stale handle. The handle references a resource that no longer exists.
 */
#define          MC_CMD_ERR_ESTALE 0x74
/* enum: Resource allocation failed. */
#define          MC_CMD_ERR_ALLOC_FAIL 0x1000
/* enum: V-adaptor not found. */
#define          MC_CMD_ERR_NO_VADAPTOR 0x1001
/* enum: EVB port not found. */
#define          MC_CMD_ERR_NO_EVB_PORT 0x1002
/* enum: V-switch not found. */
#define          MC_CMD_ERR_NO_VSWITCH 0x1003
/* enum: Too many VLAN tags. */
#define          MC_CMD_ERR_VLAN_LIMIT 0x1004
/* enum: Bad PCI function number. */
#define          MC_CMD_ERR_BAD_PCI_FUNC 0x1005
/* enum: Invalid VLAN mode. */
#define          MC_CMD_ERR_BAD_VLAN_MODE 0x1006
/* enum: Invalid v-switch type. */
#define          MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
/* enum: Invalid v-port type. */
#define          MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
/* enum: MAC address exists. */
#define          MC_CMD_ERR_MAC_EXIST 0x1009
/* enum: Slave core not present */
#define          MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
/* enum: The datapath is disabled. */
#define          MC_CMD_ERR_DATAPATH_DISABLED 0x100b
/* enum: The requesting client is not a function */
#define          MC_CMD_ERR_CLIENT_NOT_FN 0x100c
/* enum: The requested operation might require the command to be passed between
 * MCs, and thetransport doesn't support that. Should only ever been seen over
 * the UART.
 */
#define          MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
/* enum: VLAN tag(s) exists */
#define          MC_CMD_ERR_VLAN_EXIST 0x100e
/* enum: No MAC address assigned to an EVB port */
#define          MC_CMD_ERR_NO_MAC_ADDR 0x100f
/* enum: Notifies the driver that the request has been relayed to an admin
 * function for authorization. The driver should wait for a PROXY_RESPONSE
 * event and then resend its request. This error code is followed by a 32-bit
 * handle that helps matching it with the respective PROXY_RESPONSE event.
 */
#define          MC_CMD_ERR_PROXY_PENDING 0x1010
/* enum: The request cannot be passed for authorization because another request
 * from the same function is currently being authorized. The drvier should try
 * again later.
 */
#define          MC_CMD_ERR_PROXY_INPROGRESS 0x1011
/* enum: Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
 * that has enabled proxying or BLOCK_INDEX points to a function that doesn't
 * await an authorization.
 */
#define          MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
/* enum: This code is currently only used internally in FW. Its meaning is that
 * an operation failed due to lack of SR-IOV privilege. Normally it is
 * translated to EPERM by send_cmd_err(), but it may also be used to trigger
 * some special mechanism for handling such case, e.g. to relay the failed
 * request to a designated admin function for authorization.
 */
#define          MC_CMD_ERR_NO_PRIVILEGE 0x1013
/* enum: Workaround 26807 could not be turned on/off because some functions
 * have already installed filters. See the comment at
 * MC_CMD_WORKAROUND_BUG26807. May also returned for other operations such as
 * sub-variant switching.
 */
#define          MC_CMD_ERR_FILTERS_PRESENT 0x1014
/* enum: The clock whose frequency you've attempted to set set doesn't exist on
 * this NIC
 */
#define          MC_CMD_ERR_NO_CLOCK 0x1015
/* enum: Returned by MC_CMD_TESTASSERT if the action that should have caused an
 * assertion failed to do so.
 */
#define          MC_CMD_ERR_UNREACHABLE 0x1016
/* enum: This command needs to be processed in the background but there were no
 * resources to do so. Send it again after a command has completed.
 */
#define          MC_CMD_ERR_QUEUE_FULL 0x1017
/* enum: The operation could not be completed because the PCIe link has gone
 * away. This error code is never expected to be returned over the TLP
 * transport.
 */
#define          MC_CMD_ERR_NO_PCIE 0x1018
/* enum: The operation could not be completed because the datapath has gone
 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
 * datapath absence may be temporary
 */
#define          MC_CMD_ERR_NO_DATAPATH 0x1019
/* enum: The operation could not complete because some VIs are allocated */
#define          MC_CMD_ERR_VIS_PRESENT 0x101a
/* enum: The operation could not complete because some PIO buffers are
 * allocated
 */
#define          MC_CMD_ERR_PIOBUFS_PRESENT 0x101b

/* MC_CMD_RESOURCE_SPECIFIER enum */
/* enum: Any */
#define          MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
#define          MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */

/* MC_CMD_FPGA_FLASH_INDEX enum */
#define          MC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */
#define          MC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */

/* MC_CMD_EXTERNAL_MAE_LINK_MODE enum */
/* enum: Legacy mode as described in XN-200039-TC. */
#define          MC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0
/* enum: Switchdev mode as described in XN-200039-TC. */
#define          MC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1
/* enum: Bootstrap mode as described in XN-200039-TC. */
#define          MC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2
/* enum: Link-mode change is in-progress as described in XN-200039-TC. */
#define          MC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf

/* PCIE_INTERFACE enum: From EF100 onwards, SFC products can have multiple PCIe
 * interfaces. There is a need to refer to interfaces explicitly from drivers
 * (for example, a management driver on one interface administering a function
 * on another interface). This enumeration provides stable identifiers to all
 * interfaces present on a product. Product documentation will specify which
 * interfaces exist and their associated identifier. In general, drivers,
 * should not assign special meanings to specific values. Instead, behaviour
 * should be determined by NIC configuration, which will identify interfaces
 * where appropriate.
 */
/* enum: Primary host interfaces. Typically (i.e. for all known SFC products)
 * the interface exposed on the edge connector (or form factor equivalent).
 */
#define          PCIE_INTERFACE_HOST_PRIMARY 0x0
/* enum: Riverhead and keystone products have a second PCIe interface to which
 * an on-NIC ARM module is expected to be connected.
 */
#define          PCIE_INTERFACE_NIC_EMBEDDED 0x1
/* enum: For MCDI commands issued over a PCIe interface, this value is
 * translated into the interface over which the command was issued. Not
 * meaningful for other MCDI transports.
 */
#define          PCIE_INTERFACE_CALLER 0xffffffff

/* MC_CLIENT_ID_SPECIFIER enum */
/* enum: Equivalent to the caller's client ID */
#define          MC_CMD_CLIENT_ID_SELF 0xffffffff

/* MAE_FIELD_SUPPORT_STATUS enum */
/* enum: The NIC does not support this field. The driver must ensure that any
 * mask associated with this field in a match rule is zeroed. The NIC may
 * either reject requests with an invalid mask for such a field, or may assume
 * that the mask is zero. (This category only exists to describe behaviour for
 * fields that a newer driver might know about but that older firmware does
 * not. It is recommended that firmware report MAE_FIELD_FIELD_MATCH_NEVER for
 * all match fields defined at the time of its compilation. If a driver see a
 * field support status value that it does not recognise, it must treat that
 * field as thought the field was reported as MAE_FIELD_SUPPORTED_MATCH_NEVER,
 * and must never set a non-zero mask value for this field.
 */
#define          MAE_FIELD_UNSUPPORTED 0x0
/* enum: The NIC supports this field, but cannot use it in a match rule. The
 * driver must ensure that any mask for such a field in a match rule is zeroed.
 * The NIC will reject requests with an invalid mask for such a field.
 */
#define          MAE_FIELD_SUPPORTED_MATCH_NEVER 0x1
/* enum: The NIC supports this field, and must use it in all match rules. The
 * driver must ensure that any mask for such a field is all ones. The NIC will
 * reject requests with an invalid mask for such a field.
 */
#define          MAE_FIELD_SUPPORTED_MATCH_ALWAYS 0x2
/* enum: The NIC supports this field, and may optionally use it in match rules.
 * The driver must ensure that any mask for such a field is either all zeroes
 * or all ones. The NIC will reject requests with an invalid mask for such a
 * field.
 */
#define          MAE_FIELD_SUPPORTED_MATCH_OPTIONAL 0x3
/* enum: The NIC supports this field, and may optionally use it in match rules.
 * The driver must ensure that any mask for such a field is either all zeroes
 * or a consecutive set of ones following by all zeroes (starting from MSB).
 * The NIC will reject requests with an invalid mask for such a field.
 */
#define          MAE_FIELD_SUPPORTED_MATCH_PREFIX 0x4
/* enum: The NIC supports this field, and may optionally use it in match rules.
 * The driver may provide an arbitrary mask for such a field.
 */
#define          MAE_FIELD_SUPPORTED_MATCH_MASK 0x5

/* MAE_CT_VNI_MODE enum: Controls the layout of the VNI input to the conntrack
 * lookup. (Values are not arbitrary - constrained by table access ABI.)
 */
/* enum: The VNI input to the conntrack lookup will be zero. */
#define          MAE_CT_VNI_MODE_ZERO 0x0
/* enum: The VNI input to the conntrack lookup will be the VNI (VXLAN/Geneve)
 * or VSID (NVGRE) field from the packet.
 */
#define          MAE_CT_VNI_MODE_VNI 0x1
/* enum: The VNI input to the conntrack lookup will be the VLAN ID from the
 * outermost VLAN tag (in bottom 12 bits; top 12 bits zero).
 */
#define          MAE_CT_VNI_MODE_1VLAN 0x2
/* enum: The VNI input to the conntrack lookup will be the VLAN IDs from both
 * VLAN tags (outermost in bottom 12 bits, innermost in top 12 bits).
 */
#define          MAE_CT_VNI_MODE_2VLAN 0x3

/* MAE_FIELD enum: NB: this enum shares namespace with the support status enum.
 */
/* enum: Source mport upon entering the MAE. */
#define          MAE_FIELD_INGRESS_PORT 0x0
#define          MAE_FIELD_MARK 0x1 /* enum */
/* enum: Table ID used in action rule. Initially zero, can be changed in action
 * rule response.
 */
#define          MAE_FIELD_RECIRC_ID 0x2
#define          MAE_FIELD_IS_IP_FRAG 0x3 /* enum */
#define          MAE_FIELD_DO_CT 0x4 /* enum */
#define          MAE_FIELD_CT_HIT 0x5 /* enum */
/* enum: Undefined unless CT_HIT=1. */
#define          MAE_FIELD_CT_MARK 0x6
/* enum: Undefined unless DO_CT=1. */
#define          MAE_FIELD_CT_DOMAIN 0x7
/* enum: Undefined unless CT_HIT=1. */
#define          MAE_FIELD_CT_PRIVATE_FLAGS 0x8
/* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
#define          MAE_FIELD_IS_FROM_NETWORK 0x9
/* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
#define          MAE_FIELD_HAS_OVLAN 0xa
/* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
#define          MAE_FIELD_HAS_IVLAN 0xb
/* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
 * when encap
 */
#define          MAE_FIELD_ENC_HAS_OVLAN 0xc
/* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
 * when encap
 */
#define          MAE_FIELD_ENC_HAS_IVLAN 0xd
/* enum: Packet is IP fragment */
#define          MAE_FIELD_ENC_IP_FRAG 0xe
#define          MAE_FIELD_ETHER_TYPE 0x21 /* enum */
#define          MAE_FIELD_VLAN0_TCI 0x22 /* enum */
#define          MAE_FIELD_VLAN0_PROTO 0x23 /* enum */
#define          MAE_FIELD_VLAN1_TCI 0x24 /* enum */
#define          MAE_FIELD_VLAN1_PROTO 0x25 /* enum */
/* enum: Inner when encap */
#define          MAE_FIELD_ETH_SADDR 0x28
/* enum: Inner when encap */
#define          MAE_FIELD_ETH_DADDR 0x29
/* enum: Inner when encap. NB: IPv4 and IPv6 fields are mutually exclusive. */
#define          MAE_FIELD_SRC_IP4 0x2a
/* enum: Inner when encap */
#define          MAE_FIELD_SRC_IP6 0x2b
/* enum: Inner when encap */
#define          MAE_FIELD_DST_IP4 0x2c
/* enum: Inner when encap */
#define          MAE_FIELD_DST_IP6 0x2d
/* enum: Inner when encap */
#define          MAE_FIELD_IP_PROTO 0x2e
/* enum: Inner when encap */
#define          MAE_FIELD_IP_TOS 0x2f
/* enum: Inner when encap */
#define          MAE_FIELD_IP_TTL 0x30
/* enum: Inner when encap TODO: how this is defined? The raw flags +
 * frag_offset from the packet, or some derived value more amenable to ternary
 * matching? TODO: there was a proposal for driver-allocation fields. The
 * driver would provide some instruction for how to extract given field values,
 * and would be given a field id in return. It could then use that field id in
 * its matches. This feels like it would be extremely hard to implement in
 * hardware, but I mention it for completeness.
 */
#define          MAE_FIELD_IP_FLAGS 0x31
/* enum: Ports (UDP, TCP) Inner when encap */
#define          MAE_FIELD_L4_SPORT 0x32
/* enum: Ports (UDP, TCP) Inner when encap */
#define          MAE_FIELD_L4_DPORT 0x33
/* enum: Inner when encap */
#define          MAE_FIELD_TCP_FLAGS 0x34
/* enum: TCP packet with any of SYN, FIN or RST flag set */
#define          MAE_FIELD_TCP_SYN_FIN_RST 0x35
/* enum: Packet is IP fragment with fragment offset 0 */
#define          MAE_FIELD_IP_FIRST_FRAG 0x36
/* enum: The type of encapsulated used for this packet. Value as per
 * ENCAP_TYPE_*.
 */
#define          MAE_FIELD_ENCAP_TYPE 0x3f
/* enum: The ID of the outer rule that marked this packet as encapsulated.
 * Useful for implicitly matching on outer fields.
 */
#define          MAE_FIELD_OUTER_RULE_ID 0x40
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_ETHER_TYPE 0x41
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_VLAN0_TCI 0x42
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_VLAN0_PROTO 0x43
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_VLAN1_TCI 0x44
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_VLAN1_PROTO 0x45
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_ETH_SADDR 0x48
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_ETH_DADDR 0x49
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_SRC_IP4 0x4a
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_SRC_IP6 0x4b
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_DST_IP4 0x4c
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_DST_IP6 0x4d
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_IP_PROTO 0x4e
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_IP_TOS 0x4f
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_IP_TTL 0x50
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_IP_FLAGS 0x51
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_L4_SPORT 0x52
/* enum: Outer; only present when encap */
#define          MAE_FIELD_ENC_L4_DPORT 0x53
/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Bottom 24 bits of Key
 * (when L2GRE) Outer; only present when encap
 */
#define          MAE_FIELD_ENC_VNET_ID 0x54

/* MAE_MCDI_ENCAP_TYPE enum: Encapsulation type. Defines how the payload will
 * be parsed to an inner frame. Other values are reserved. Unknown values
 * should be treated same as NONE. (Values are not arbitrary - constrained by
 * table access ABI.)
 */
#define          MAE_MCDI_ENCAP_TYPE_NONE 0x0 /* enum */
/* enum: Don't assume enum aligns with support bitmask... */
#define          MAE_MCDI_ENCAP_TYPE_VXLAN 0x1
#define          MAE_MCDI_ENCAP_TYPE_NVGRE 0x2 /* enum */
#define          MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */
#define          MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */

/* MAE_MPORT_END enum: Selects which end of the logical link identified by an
 * MPORT_SELECTOR is targeted by an operation.
 */
/* enum: Selects the port on the MAE virtual switch */
#define          MAE_MPORT_END_MAE 0x1
/* enum: Selects the virtual NIC plugged into the MAE switch */
#define          MAE_MPORT_END_VNIC 0x2

/* MAE_COUNTER_TYPE enum: The datapath maintains several sets of counters, each
 * being associated with a different table. Note that the same counter ID may
 * be allocated by different counter blocks, so e.g. AR counter 42 is different
 * from CT counter 42. Generation counts are also type-specific. This value is
 * also present in the header of streaming counter packets, in the IDENTIFIER
 * field (see packetiser packet format definitions).
 */
/* enum: Action Rule counters - can be referenced in AR response. */
#define          MAE_COUNTER_TYPE_AR 0x0
/* enum: Conntrack counters - can be referenced in CT response. */
#define          MAE_COUNTER_TYPE_CT 0x1
/* enum: Outer Rule counters - can be referenced in OR response. */
#define          MAE_COUNTER_TYPE_OR 0x2

/* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been
 * structured with bits [31:24] reserved (0), [23:16] indicating which major
 * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),
 * [15:8] a unique ID within the block, and [7:0] reserved for future
 * variations of the same table. (All of the tables currently defined within
 * the streaming engines are listed here, but this does not imply that they are
 * all supported - MC_CMD_TABLE_LIST returns the list of actually supported
 * tables.)
 */
/* enum: Outer_Rule_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_OUTER_RULE_TABLE 0x10000
/* enum: Outer_Rule_No_CT_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_OUTER_RULE_NO_CT_TABLE 0x10100
/* enum: Mgmt_Filter_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_MGMT_FILTER_TABLE 0x10200
/* enum: Conntrack_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_CONNTRACK_TABLE 0x10300
/* enum: Action_Rule_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_ACTION_RULE_TABLE 0x10400
/* enum: Mgroup_Default_Action_Set_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_MGROUP_DEFAULT_ACTION_SET_TABLE 0x10500
/* enum: Encap_Hdr_Part1_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_ENCAP_HDR_PART1_TABLE 0x10600
/* enum: Encap_Hdr_Part2_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_ENCAP_HDR_PART2_TABLE 0x10700
/* enum: Replace_Src_MAC_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_REPLACE_SRC_MAC_TABLE 0x10800
/* enum: Replace_Dst_MAC_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_REPLACE_DST_MAC_TABLE 0x10900
/* enum: Dst_Mport_VC_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_DST_MPORT_VC_TABLE 0x10a00
/* enum: LACP_LAG_Config_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_LACP_LAG_CONFIG_TABLE 0x10b00
/* enum: LACP_Balance_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_LACP_BALANCE_TABLE 0x10c00
/* enum: Dst_Mport_Host_Chan_Table in the MAE - refer to SF-123102-TC. */
#define          TABLE_ID_DST_MPORT_HOST_CHAN_TABLE 0x10d00
/* enum: VNIC_Rx_Encap_Table in VNIC Rx - refer to SF-123102-TC. */
#define          TABLE_ID_VNIC_RX_ENCAP_TABLE 0x20000
/* enum: Steering_Table in VNIC Rx - refer to SF-123102-TC. */
#define          TABLE_ID_STEERING_TABLE 0x20100
/* enum: RSS_Context_Table in VNIC Rx - refer to SF-123102-TC. */
#define          TABLE_ID_RSS_CONTEXT_TABLE 0x20200
/* enum: Indirection_Table in VNIC Rx - refer to SF-123102-TC. */
#define          TABLE_ID_INDIRECTION_TABLE 0x20300

/* TABLE_COMPRESSED_VLAN enum: Compressed VLAN TPID as used by some field
 * types; can be calculated by (((ether_type_msb >> 2) & 0x4) ^ 0x4) |
 * (ether_type_msb & 0x3);
 */
#define          TABLE_COMPRESSED_VLAN_TPID_8100 0x5 /* enum */
#define          TABLE_COMPRESSED_VLAN_TPID_88A8 0x4 /* enum */
#define          TABLE_COMPRESSED_VLAN_TPID_9100 0x1 /* enum */
#define          TABLE_COMPRESSED_VLAN_TPID_9200 0x2 /* enum */
#define          TABLE_COMPRESSED_VLAN_TPID_9300 0x3 /* enum */

/* TABLE_NAT_DIR enum: NAT direction. */
#define          TABLE_NAT_DIR_SOURCE 0x0 /* enum */
#define          TABLE_NAT_DIR_DEST 0x1 /* enum */

/* TABLE_RSS_KEY_MODE enum: Defines how the value for Toeplitz hashing for RSS
 * is constructed as a concatenation (indicated here by "++") of packet header
 * fields.
 */
/* enum: IP src addr ++ IP dst addr */
#define          TABLE_RSS_KEY_MODE_SA_DA 0x0
/* enum: IP src addr ++ IP dst addr ++ TCP/UDP src port ++ TCP/UDP dst port */
#define          TABLE_RSS_KEY_MODE_SA_DA_SP_DP 0x1
/* enum: IP src addr */
#define          TABLE_RSS_KEY_MODE_SA 0x2
/* enum: IP dst addr */
#define          TABLE_RSS_KEY_MODE_DA 0x3
/* enum: IP src addr ++ TCP/UDP src port */
#define          TABLE_RSS_KEY_MODE_SA_SP 0x4
/* enum: IP dest addr ++ TCP dest port */
#define          TABLE_RSS_KEY_MODE_DA_DP 0x5
/* enum: Nothing (produces input of 0, resulting in output hash of 0) */
#define          TABLE_RSS_KEY_MODE_NONE 0x7

/* TABLE_RSS_SPREAD_MODE enum: RSS spreading mode. */
/* enum: RSS uses Indirection_Table lookup. */
#define          TABLE_RSS_SPREAD_MODE_INDIRECTION 0x0
/* enum: RSS uses even spreading calculation. */
#define          TABLE_RSS_SPREAD_MODE_EVEN 0x1

/* TABLE_FIELD_ID enum: Unique IDs for fields. Related concepts have been
 * loosely grouped together into blocks with gaps for expansion, but the values
 * are arbitrary. Field IDs are not specific to particular tables, and in some
 * cases this sharing means that they are not used with the exact names of the
 * corresponding table definitions in SF-123102-TC; however, the mapping should
 * still be clear. The intent is that a list of fields, with their associated
 * bit widths and semantics version code, unambiguously defines the semantics
 * of the fields in a key or response. (Again, this list includes all of the
 * fields currently defined within the streaming engines, but only a subset may
 * actually be used by the supported list of tables.)
 */
/* enum: May appear multiple times within a key or response, and indicates that
 * the field is unused and should be set to 0 (or masked out if permitted by
 * the MASK_VALUE for this field).
 */
#define          TABLE_FIELD_ID_UNUSED 0x0
/* enum: Source m-port (a full m-port label). */
#define          TABLE_FIELD_ID_SRC_MPORT 0x1
/* enum: Destination m-port (a full m-port label). */
#define          TABLE_FIELD_ID_DST_MPORT 0x2
/* enum: Source m-group ID. */
#define          TABLE_FIELD_ID_SRC_MGROUP_ID 0x3
/* enum: Physical network port ID (or m-port ID; same thing, for physical
 * network ports).
 */
#define          TABLE_FIELD_ID_NETWORK_PORT_ID 0x4
/* enum: True if packet arrived via network port, false if it arrived via host.
 */
#define          TABLE_FIELD_ID_IS_FROM_NETWORK 0x5
/* enum: Full virtual channel from capsule header. */
#define          TABLE_FIELD_ID_CH_VC 0x6
/* enum: Low bits of virtual channel from capsule header. */
#define          TABLE_FIELD_ID_CH_VC_LOW 0x7
/* enum: User mark value in metadata and packet prefix. */
#define          TABLE_FIELD_ID_USER_MARK 0x8
/* enum: User flag value in metadata and packet prefix. */
#define          TABLE_FIELD_ID_USER_FLAG 0x9
/* enum: Counter ID associated with a response. All-bits-1 is a null value to
 * suppress counting.
 */
#define          TABLE_FIELD_ID_COUNTER_ID 0xa
/* enum: Discriminator which may be set by plugins in some lookup keys; this
 * allows plugins to make a reinterpretation of packet fields in these keys
 * without clashing with the normal interpretation.
 */
#define          TABLE_FIELD_ID_DISCRIM 0xb
/* enum: Destination MAC address. The mapping from bytes in a frame to the
 * 48-bit value for this field is in network order, i.e. a MAC address of
 * AA:BB:CC:DD:EE:FF becomes a 48-bit value of 0xAABBCCDDEEFF.
 */
#define          TABLE_FIELD_ID_DST_MAC 0x14
/* enum: Source MAC address (see notes for DST_MAC). */
#define          TABLE_FIELD_ID_SRC_MAC 0x15
/* enum: Outer VLAN tag TPID, compressed to an enumeration. */
#define          TABLE_FIELD_ID_OVLAN_TPID_COMPRESSED 0x16
/* enum: Full outer VLAN tag TCI (16 bits). */
#define          TABLE_FIELD_ID_OVLAN 0x17
/* enum: Outer VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
#define          TABLE_FIELD_ID_OVLAN_VID 0x18
/* enum: Inner VLAN tag TPID, compressed to an enumeration. */
#define          TABLE_FIELD_ID_IVLAN_TPID_COMPRESSED 0x19
/* enum: Full inner VLAN tag TCI (16 bits). */
#define          TABLE_FIELD_ID_IVLAN 0x1a
/* enum: Inner VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
#define          TABLE_FIELD_ID_IVLAN_VID 0x1b
/* enum: Ethertype. */
#define          TABLE_FIELD_ID_ETHER_TYPE 0x1c
/* enum: Source IP address, either IPv4 or IPv6. The mapping from bytes in a
 * frame to the 128-bit value for this field is in network order, with IPv4
 * addresses assumed to have 12 bytes of trailing zeroes. i.e. the IPv6 address
 * [2345::6789:ABCD] is 0x2345000000000000000000006789ABCD; the IPv4 address
 * 192.168.1.2 is 0xC0A80102000000000000000000000000.
 */
#define          TABLE_FIELD_ID_SRC_IP 0x1d
/* enum: Destination IP address (see notes for SRC_IP). */
#define          TABLE_FIELD_ID_DST_IP 0x1e
/* enum: IPv4 Type-of-Service or IPv6 Traffic Class field. */
#define          TABLE_FIELD_ID_IP_TOS 0x1f
/* enum: IP Protocol. */
#define          TABLE_FIELD_ID_IP_PROTO 0x20
/* enum: Layer 4 source port. */
#define          TABLE_FIELD_ID_SRC_PORT 0x21
/* enum: Layer 4 destination port. */
#define          TABLE_FIELD_ID_DST_PORT 0x22
/* enum: TCP flags. */
#define          TABLE_FIELD_ID_TCP_FLAGS 0x23
/* enum: Virtual Network Identifier (VXLAN) or Virtual Session ID (NVGRE). */
#define          TABLE_FIELD_ID_VNI 0x24
/* enum: True if packet has any tunnel encapsulation header. */
#define          TABLE_FIELD_ID_HAS_ENCAP 0x32
/* enum: True if encap header has an outer VLAN tag. */
#define          TABLE_FIELD_ID_HAS_ENC_OVLAN 0x33
/* enum: True if encap header has an inner VLAN tag. */
#define          TABLE_FIELD_ID_HAS_ENC_IVLAN 0x34
/* enum: True if encap header is some sort of IP. */
#define          TABLE_FIELD_ID_HAS_ENC_IP 0x35
/* enum: True if encap header is specifically IPv4. */
#define          TABLE_FIELD_ID_HAS_ENC_IP4 0x36
/* enum: True if encap header is UDP. */
#define          TABLE_FIELD_ID_HAS_ENC_UDP 0x37
/* enum: True if only/inner frame has an outer VLAN tag. */
#define          TABLE_FIELD_ID_HAS_OVLAN 0x38
/* enum: True if only/inner frame has an inner VLAN tag. */
#define          TABLE_FIELD_ID_HAS_IVLAN 0x39
/* enum: True if only/inner frame is some sort of IP. */
#define          TABLE_FIELD_ID_HAS_IP 0x3a
/* enum: True if only/inner frame has a recognised L4 IP protocol (TCP or UDP).
 */
#define          TABLE_FIELD_ID_HAS_L4 0x3b
/* enum: True if only/inner frame is an IP fragment. */
#define          TABLE_FIELD_ID_IP_FRAG 0x3c
/* enum: True if only/inner frame is the first IP fragment (fragment offset 0).
 */
#define          TABLE_FIELD_ID_IP_FIRST_FRAG 0x3d
/* enum: True if only/inner frame has an IP Time-To-Live of <= 1. (Note: the
 * implementation calls this "ip_ttl_is_one" but does in fact match packets
 * with TTL=0 - which we shouldn't be seeing! - as well.)
 */
#define          TABLE_FIELD_ID_IP_TTL_LE_ONE 0x3e
/* enum: True if only/inner frame has any of TCP SYN, FIN or RST flags set. */
#define          TABLE_FIELD_ID_TCP_INTERESTING_FLAGS 0x3f
/* enum: Plugin channel selection. */
#define          TABLE_FIELD_ID_RDP_PL_CHAN 0x50
/* enum: Enable update of CH_ROUTE_RDP_C_PL route bit. */
#define          TABLE_FIELD_ID_RDP_C_PL_EN 0x51
/* enum: New value of CH_ROUTE_RDP_C_PL route bit. */
#define          TABLE_FIELD_ID_RDP_C_PL 0x52
/* enum: Enable update of CH_ROUTE_RDP_D_PL route bit. */
#define          TABLE_FIELD_ID_RDP_D_PL_EN 0x53
/* enum: New value of CH_ROUTE_RDP_D_PL route bit. */
#define          TABLE_FIELD_ID_RDP_D_PL 0x54
/* enum: Enable update of CH_ROUTE_RDP_OUT_HOST_CHAN route bit. */
#define          TABLE_FIELD_ID_RDP_OUT_HOST_CHAN_EN 0x55
/* enum: New value of CH_ROUTE_RDP_OUT_HOST_CHAN route bit. */
#define          TABLE_FIELD_ID_RDP_OUT_HOST_CHAN 0x56
/* enum: Recirculation ID for lookup sequences with two action rule lookups. */
#define          TABLE_FIELD_ID_RECIRC_ID 0x64
/* enum: Domain ID passed to conntrack and action rule lookups. */
#define          TABLE_FIELD_ID_DOMAIN 0x65
/* enum: Construction mode for encap_tunnel_id - see MAE_CT_VNI_MODE enum. */
#define          TABLE_FIELD_ID_CT_VNI_MODE 0x66
/* enum: True to inhibit conntrack lookup if TCP SYN, FIN or RST flag is set.
 */
#define          TABLE_FIELD_ID_CT_TCP_FLAGS_INHIBIT 0x67
/* enum: True to do conntrack lookups for IPv4 TCP packets. */
#define          TABLE_FIELD_ID_DO_CT_IP4_TCP 0x68
/* enum: True to do conntrack lookups for IPv4 UDP packets. */
#define          TABLE_FIELD_ID_DO_CT_IP4_UDP 0x69
/* enum: True to do conntrack lookups for IPv6 TCP packets. */
#define          TABLE_FIELD_ID_DO_CT_IP6_TCP 0x6a
/* enum: True to do conntrack lookups for IPv6 UDP packets. */
#define          TABLE_FIELD_ID_DO_CT_IP6_UDP 0x6b
/* enum: Outer rule identifier. */
#define          TABLE_FIELD_ID_OUTER_RULE_ID 0x6c
/* enum: Encapsulation type - see MAE_MCDI_ENCAP_TYPE enum. */
#define          TABLE_FIELD_ID_ENCAP_TYPE 0x6d
/* enum: Encap tunnel ID for conntrack lookups from VNI, VLAN tag(s), or 0,
 * depending on CT_VNI_MODE.
 */
#define          TABLE_FIELD_ID_ENCAP_TUNNEL_ID 0x78
/* enum: A conntrack entry identifier, passed to plugins. */
#define          TABLE_FIELD_ID_CT_ENTRY_ID 0x79
/* enum: Either source or destination NAT replacement port. */
#define          TABLE_FIELD_ID_NAT_PORT 0x7a
/* enum: Either source or destination NAT replacement IPv4 address. Note that
 * this is specifically an IPv4 address (IPv6 is not supported for NAT), with
 * byte mapped to a 32-bit value in network order, i.e. the IPv4 address
 * 192.168.1.2 is the value 0xC0A80102.
 */
#define          TABLE_FIELD_ID_NAT_IP 0x7b
/* enum: NAT direction: 0=>source, 1=>destination. */
#define          TABLE_FIELD_ID_NAT_DIR 0x7c
/* enum: Conntrack mark value, passed to action rule lookup. Note that this is
 * not related to the "user mark" in the metadata / packet prefix.
 */
#define          TABLE_FIELD_ID_CT_MARK 0x7d
/* enum: Private flags for conntrack, passed to action rule lookup. */
#define          TABLE_FIELD_ID_CT_PRIV_FLAGS 0x7e
/* enum: True if the conntrack lookup resulted in a hit. */
#define          TABLE_FIELD_ID_CT_HIT 0x7f
/* enum: True to suppress delivery when source and destination m-ports match.
 */
#define          TABLE_FIELD_ID_SUPPRESS_SELF_DELIVERY 0x8c
/* enum: True to perform tunnel decapsulation. */
#define          TABLE_FIELD_ID_DO_DECAP 0x8d
/* enum: True to copy outer frame DSCP to inner on decap. */
#define          TABLE_FIELD_ID_DECAP_DSCP_COPY 0x8e
/* enum: True to map outer frame ECN to inner on decap, by RFC 6040 rules. */
#define          TABLE_FIELD_ID_DECAP_ECN_RFC6040 0x8f
/* enum: True to replace DSCP field. */
#define          TABLE_FIELD_ID_DO_REPLACE_DSCP 0x90
/* enum: True to replace ECN field. */
#define          TABLE_FIELD_ID_DO_REPLACE_ECN 0x91
/* enum: True to decrement IP Time-To-Live. */
#define          TABLE_FIELD_ID_DO_DECR_IP_TTL 0x92
/* enum: True to replace source MAC address. */
#define          TABLE_FIELD_ID_DO_SRC_MAC 0x93
/* enum: True to replace destination MAC address. */
#define          TABLE_FIELD_ID_DO_DST_MAC 0x94
/* enum: Number of VLAN tags to pop. Valid values are 0, 1, or 2. */
#define          TABLE_FIELD_ID_DO_VLAN_POP 0x95
/* enum: Number of VLANs tags to push. Valid values are 0, 1, or 2. */
#define          TABLE_FIELD_ID_DO_VLAN_PUSH 0x96
/* enum: True to count this packet. */
#define          TABLE_FIELD_ID_DO_COUNT 0x97
/* enum: True to perform tunnel encapsulation. */
#define          TABLE_FIELD_ID_DO_ENCAP 0x98
/* enum: True to copy inner frame DSCP to outer on encap. */
#define          TABLE_FIELD_ID_ENCAP_DSCP_COPY 0x99
/* enum: True to copy inner frame ECN to outer on encap. */
#define          TABLE_FIELD_ID_ENCAP_ECN_COPY 0x9a
/* enum: True to deliver the packet (otherwise it is dropped). */
#define          TABLE_FIELD_ID_DO_DELIVER 0x9b
/* enum: True to set the user flag in the metadata. */
#define          TABLE_FIELD_ID_DO_FLAG 0x9c
/* enum: True to update the user mark in the metadata. */
#define          TABLE_FIELD_ID_DO_MARK 0x9d
/* enum: True to override the capsule virtual channel for network deliveries.
 */
#define          TABLE_FIELD_ID_DO_SET_NET_CHAN 0x9e
/* enum: True to override the reported source m-port for host deliveries. */
#define          TABLE_FIELD_ID_DO_SET_SRC_MPORT 0x9f
/* enum: Encap header ID for DO_ENCAP, indexing Encap_Hdr_Part1/2_Table. */
#define          TABLE_FIELD_ID_ENCAP_HDR_ID 0xaa
/* enum: New DSCP value for DO_REPLACE_DSCP. */
#define          TABLE_FIELD_ID_DSCP_VALUE 0xab
/* enum: If DO_REPLACE_ECN is set, the new value for the ECN field. If
 * DO_REPLACE_ECN is not set, ECN_CONTROL[0] and ECN_CONTROL[1] are set to
 * request remapping of ECT0 and ECT1 ECN codepoints respectively to CE.
 */
#define          TABLE_FIELD_ID_ECN_CONTROL 0xac
/* enum: Source MAC ID for DO_SRC_MAC, indexing Replace_Src_MAC_Table. */
#define          TABLE_FIELD_ID_SRC_MAC_ID 0xad
/* enum: Destination MAC ID for DO_DST_MAC, indexing Replace_Dst_MAC_Table. */
#define          TABLE_FIELD_ID_DST_MAC_ID 0xae
/* enum: Parameter for either DO_SET_NET_CHAN (only bottom 6 bits used in this
 * case) or DO_SET_SRC_MPORT.
 */
#define          TABLE_FIELD_ID_REPORTED_SRC_MPORT_OR_NET_CHAN 0xaf
/* enum: 64-byte chunk of added encapsulation header. */
#define          TABLE_FIELD_ID_CHUNK64 0xb4
/* enum: 32-byte chunk of added encapsulation header. */
#define          TABLE_FIELD_ID_CHUNK32 0xb5
/* enum: 16-byte chunk of added encapsulation header. */
#define          TABLE_FIELD_ID_CHUNK16 0xb6
/* enum: 8-byte chunk of added encapsulation header. */
#define          TABLE_FIELD_ID_CHUNK8 0xb7
/* enum: 4-byte chunk of added encapsulation header. */
#define          TABLE_FIELD_ID_CHUNK4 0xb8
/* enum: 2-byte chunk of added encapsulation header. */
#define          TABLE_FIELD_ID_CHUNK2 0xb9
/* enum: Added encapsulation header length in words. */
#define          TABLE_FIELD_ID_HDR_LEN_W 0xba
/* enum: Static value for layer 2/3 LACP hash of the encapsulation header. */
#define          TABLE_FIELD_ID_ENC_LACP_HASH_L23 0xbb
/* enum: Static value for layer 4 LACP hash of the encapsulation header. */
#define          TABLE_FIELD_ID_ENC_LACP_HASH_L4 0xbc
/* enum: True to use the static ENC_LACP_HASH values for the encap header
 * instead of the calculated values for the inner frame when delivering a newly
 * encapsulated packet to a LAG m-port.
 */
#define          TABLE_FIELD_ID_USE_ENC_LACP_HASHES 0xbd
/* enum: True to trigger conntrack from first action rule lookup (AR=>CT=>AR
 * sequence).
 */
#define          TABLE_FIELD_ID_DO_CT 0xc8
/* enum: True to perform NAT using parameters from conntrack lookup response.
 */
#define          TABLE_FIELD_ID_DO_NAT 0xc9
/* enum: True to trigger recirculated action rule lookup (AR=>AR sequence). */
#define          TABLE_FIELD_ID_DO_RECIRC 0xca
/* enum: Next action set payload ID for replay. The null value is all-1-bits.
 */
#define          TABLE_FIELD_ID_NEXT_ACTION_SET_PAYLOAD 0xcb
/* enum: Next action set row ID for replay. The null value is all-1-bits. */
#define          TABLE_FIELD_ID_NEXT_ACTION_SET_ROW 0xcc
/* enum: Action set payload ID for additional delivery to management CPU. The
 * null value is all-1-bits.
 */
#define          TABLE_FIELD_ID_MC_ACTION_SET_PAYLOAD 0xcd
/* enum: Action set row ID for additional delivery to management CPU. The null
 * value is all-1-bits.
 */
#define          TABLE_FIELD_ID_MC_ACTION_SET_ROW 0xce
/* enum: True to include layer 4 in LACP hash on delivery to a LAG m-port. */
#define          TABLE_FIELD_ID_LACP_INC_L4 0xdc
/* enum: True to request that LACP is performed by a plugin. */
#define          TABLE_FIELD_ID_LACP_PLUGIN 0xdd
/* enum: LACP_Balance_Table base address divided by 64. */
#define          TABLE_FIELD_ID_BAL_TBL_BASE_DIV64 0xde
/* enum: Length of balance table region: 0=>64, 1=>128, 2=>256. */
#define          TABLE_FIELD_ID_BAL_TBL_LEN_ID 0xdf
/* enum: UDP port to match for UDP-based encapsulations; required to be 0 for
 * other encapsulation types.
 */
#define          TABLE_FIELD_ID_UDP_PORT 0xe6
/* enum: True to perform RSS based on outer fields rather than inner fields. */
#define          TABLE_FIELD_ID_RSS_ON_OUTER 0xe7
/* enum: True to perform steering table lookup on outer fields rather than
 * inner fields.
 */
#define          TABLE_FIELD_ID_STEER_ON_OUTER 0xe8
/* enum: Destination queue ID for host delivery. */
#define          TABLE_FIELD_ID_DST_QID 0xf0
/* enum: True to drop this packet. */
#define          TABLE_FIELD_ID_DROP 0xf1
/* enum: True to strip outer VLAN tag from this packet. */
#define          TABLE_FIELD_ID_VLAN_STRIP 0xf2
/* enum: True to override the user mark field with the supplied USER_MARK, or
 * false to bitwise-OR the USER_MARK into it.
 */
#define          TABLE_FIELD_ID_MARK_OVERRIDE 0xf3
/* enum: True to override the user flag field with the supplied USER_FLAG, or
 * false to bitwise-OR the USER_FLAG into it.
 */
#define          TABLE_FIELD_ID_FLAG_OVERRIDE 0xf4
/* enum: RSS context ID, indexing the RSS_Context_Table. */
#define          TABLE_FIELD_ID_RSS_CTX_ID 0xfa
/* enum: True to enable RSS. */
#define          TABLE_FIELD_ID_RSS_EN 0xfb
/* enum: Toeplitz hash key. */
#define          TABLE_FIELD_ID_KEY 0xfc
/* enum: Key mode for IPv4 TCP packets - see TABLE_RSS_KEY_MODE enum. */
#define          TABLE_FIELD_ID_TCP_V4_KEY_MODE 0xfd
/* enum: Key mode for IPv6 TCP packets - see TABLE_RSS_KEY_MODE enum. */
#define          TABLE_FIELD_ID_TCP_V6_KEY_MODE 0xfe
/* enum: Key mode for IPv4 UDP packets - see TABLE_RSS_KEY_MODE enum. */
#define          TABLE_FIELD_ID_UDP_V4_KEY_MODE 0xff
/* enum: Key mode for IPv6 UDP packets - see TABLE_RSS_KEY_MODE enum. */
#define          TABLE_FIELD_ID_UDP_V6_KEY_MODE 0x100
/* enum: Key mode for other IPv4 packets - see TABLE_RSS_KEY_MODE enum. */
#define          TABLE_FIELD_ID_OTHER_V4_KEY_MODE 0x101
/* enum: Key mode for other IPv6 packets - see TABLE_RSS_KEY_MODE enum. */
#define          TABLE_FIELD_ID_OTHER_V6_KEY_MODE 0x102
/* enum: Spreading mode - 0=>indirection; 1=>even. */
#define          TABLE_FIELD_ID_SPREAD_MODE 0x103
/* enum: For indirection spreading mode, the base address of a region within
 * the Indirection_Table. For even spreading mode, the number of queues to
 * spread across (only values 1-255 are valid for this mode).
 */
#define          TABLE_FIELD_ID_INDIR_TBL_BASE 0x104
/* enum: For indirection spreading mode, identifies the length of a region
 * within the Indirection_Table, where length = 32 << len_id. Must be set to 0
 * for even spreading mode.
 */
#define          TABLE_FIELD_ID_INDIR_TBL_LEN_ID 0x105
/* enum: An offset to be applied to the base destination queue ID. */
#define          TABLE_FIELD_ID_INDIR_OFFSET 0x106

/* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF100
 * platforms
 */
#define    MCDI_EVENT_LEN 8
#define       MCDI_EVENT_CONT_LBN 32
#define       MCDI_EVENT_CONT_WIDTH 1
#define       MCDI_EVENT_LEVEL_LBN 33
#define       MCDI_EVENT_LEVEL_WIDTH 3
/* enum: Info. */
#define          MCDI_EVENT_LEVEL_INFO 0x0
/* enum: Warning. */
#define          MCDI_EVENT_LEVEL_WARN 0x1
/* enum: Error. */
#define          MCDI_EVENT_LEVEL_ERR 0x2
/* enum: Fatal. */
#define          MCDI_EVENT_LEVEL_FATAL 0x3
#define       MCDI_EVENT_DATA_OFST 0
#define       MCDI_EVENT_DATA_LEN 4
#define        MCDI_EVENT_CMDDONE_SEQ_OFST 0
#define        MCDI_EVENT_CMDDONE_SEQ_LBN 0
#define        MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
#define        MCDI_EVENT_CMDDONE_DATALEN_OFST 0
#define        MCDI_EVENT_CMDDONE_DATALEN_LBN 8
#define        MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
#define        MCDI_EVENT_CMDDONE_ERRNO_OFST 0
#define        MCDI_EVENT_CMDDONE_ERRNO_LBN 16
#define        MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
#define        MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0
#define        MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
#define        MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
#define        MCDI_EVENT_LINKCHANGE_SPEED_OFST 0
#define        MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
#define        MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
/* enum: Link is down or link speed could not be determined */
#define          MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
/* enum: 100Mbs */
#define          MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
/* enum: 1Gbs */
#define          MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
/* enum: 10Gbs */
#define          MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
/* enum: 40Gbs */
#define          MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
/* enum: 25Gbs */
#define          MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
/* enum: 50Gbs */
#define          MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
/* enum: 100Gbs */
#define          MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
#define        MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0
#define        MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
#define        MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
#define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
#define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
#define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
#define        MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
#define        MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
#define        MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
#define        MCDI_EVENT_SENSOREVT_STATE_OFST 0
#define        MCDI_EVENT_SENSOREVT_STATE_LBN 8
#define        MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
#define        MCDI_EVENT_SENSOREVT_VALUE_OFST 0
#define        MCDI_EVENT_SENSOREVT_VALUE_LBN 16
#define        MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
#define        MCDI_EVENT_FWALERT_DATA_OFST 0
#define        MCDI_EVENT_FWALERT_DATA_LBN 8
#define        MCDI_EVENT_FWALERT_DATA_WIDTH 24
#define        MCDI_EVENT_FWALERT_REASON_OFST 0
#define        MCDI_EVENT_FWALERT_REASON_LBN 0
#define        MCDI_EVENT_FWALERT_REASON_WIDTH 8
/* enum: SRAM Access. */
#define          MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
#define        MCDI_EVENT_FLR_VF_OFST 0
#define        MCDI_EVENT_FLR_VF_LBN 0
#define        MCDI_EVENT_FLR_VF_WIDTH 8
#define        MCDI_EVENT_TX_ERR_TXQ_OFST 0
#define        MCDI_EVENT_TX_ERR_TXQ_LBN 0
#define        MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
#define        MCDI_EVENT_TX_ERR_TYPE_OFST 0
#define        MCDI_EVENT_TX_ERR_TYPE_LBN 12
#define        MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
/* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */
#define          MCDI_EVENT_TX_ERR_DL_FAIL 0x1
/* enum: Descriptor ring empty and no EOP seen for packet. Specific to
 * EF10-family NICs
 */
#define          MCDI_EVENT_TX_ERR_NO_EOP 0x2
/* enum: Overlength packet. Specific to EF10-family NICs. */
#define          MCDI_EVENT_TX_ERR_2BIG 0x3
/* enum: Malformed option descriptor. Specific to EF10-family NICs. */
#define          MCDI_EVENT_TX_BAD_OPTDESC 0x5
/* enum: Option descriptor part way through a packet. Specific to EF10-family
 * NICs.
 */
#define          MCDI_EVENT_TX_OPT_IN_PKT 0x8
/* enum: DMA or PIO data access error. Specific to EF10-family NICs */
#define          MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
#define        MCDI_EVENT_TX_ERR_INFO_OFST 0
#define        MCDI_EVENT_TX_ERR_INFO_LBN 16
#define        MCDI_EVENT_TX_ERR_INFO_WIDTH 16
#define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0
#define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
#define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
#define        MCDI_EVENT_TX_FLUSH_TXQ_OFST 0
#define        MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
#define        MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
#define        MCDI_EVENT_PTP_ERR_TYPE_OFST 0
#define        MCDI_EVENT_PTP_ERR_TYPE_LBN 0
#define        MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
/* enum: PLL lost lock */
#define          MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
/* enum: Filter overflow (PDMA) */
#define          MCDI_EVENT_PTP_ERR_FILTER 0x2
/* enum: FIFO overflow (FPGA) */
#define          MCDI_EVENT_PTP_ERR_FIFO 0x3
/* enum: Merge queue overflow */
#define          MCDI_EVENT_PTP_ERR_QUEUE 0x4
#define        MCDI_EVENT_AOE_ERR_TYPE_OFST 0
#define        MCDI_EVENT_AOE_ERR_TYPE_LBN 0
#define        MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
/* enum: AOE failed to load - no valid image? */
#define          MCDI_EVENT_AOE_NO_LOAD 0x1
/* enum: AOE FC reported an exception */
#define          MCDI_EVENT_AOE_FC_ASSERT 0x2
/* enum: AOE FC watchdogged */
#define          MCDI_EVENT_AOE_FC_WATCHDOG 0x3
/* enum: AOE FC failed to start */
#define          MCDI_EVENT_AOE_FC_NO_START 0x4
/* enum: Generic AOE fault - likely to have been reported via other means too
 * but intended for use by aoex driver.
 */
#define          MCDI_EVENT_AOE_FAULT 0x5
/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
#define          MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
/* enum: AOE loaded successfully */
#define          MCDI_EVENT_AOE_LOAD 0x7
/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
#define          MCDI_EVENT_AOE_DMA 0x8
/* enum: AOE byteblaster connected/disconnected (Connection status in
 * AOE_ERR_DATA)
 */
#define          MCDI_EVENT_AOE_BYTEBLASTER 0x9
/* enum: DDR ECC status update */
#define          MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
/* enum: PTP status update */
#define          MCDI_EVENT_AOE_PTP_STATUS 0xb
/* enum: FPGA header incorrect */
#define          MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
/* enum: FPGA Powered Off due to error in powering up FPGA */
#define          MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
/* enum: AOE FPGA load failed due to MC to MUM communication failure */
#define          MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
/* enum: Notify that invalid flash type detected */
#define          MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
/* enum: Notify that the attempt to run FPGA Controller firmware timedout */
#define          MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
/* enum: Failure to probe one or more FPGA boot flash chips */
#define          MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
/* enum: FPGA boot-flash contains an invalid image header */
#define          MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
/* enum: Failed to program clocks required by the FPGA */
#define          MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
/* enum: Notify that FPGA Controller is alive to serve MCDI requests */
#define          MCDI_EVENT_AOE_FC_RUNNING 0x14
#define        MCDI_EVENT_AOE_ERR_DATA_OFST 0
#define        MCDI_EVENT_AOE_ERR_DATA_LBN 8
#define        MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
#define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0
#define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8
#define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8
/* enum: FC Assert happened, but the register information is not available */
#define          MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
/* enum: The register information for FC Assert is ready for readinng by driver
 */
#define          MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0
#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8
#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8
/* enum: Reading from NV failed */
#define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
/* enum: Invalid Magic Number if FPGA header */
#define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
/* enum: Invalid Silicon type detected in header */
#define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
/* enum: Unsupported VRatio */
#define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
/* enum: Unsupported DDR Type */
#define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
/* enum: DDR Voltage out of supported range */
#define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
/* enum: Unsupported DDR speed */
#define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
/* enum: Unsupported DDR size */
#define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
/* enum: Unsupported DDR rank */
#define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
#define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0
#define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8
#define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8
/* enum: Primary boot flash */
#define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
/* enum: Secondary boot flash */
#define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0
#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8
#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8
#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0
#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8
#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8
#define        MCDI_EVENT_RX_ERR_RXQ_OFST 0
#define        MCDI_EVENT_RX_ERR_RXQ_LBN 0
#define        MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
#define        MCDI_EVENT_RX_ERR_TYPE_OFST 0
#define        MCDI_EVENT_RX_ERR_TYPE_LBN 12
#define        MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
#define        MCDI_EVENT_RX_ERR_INFO_OFST 0
#define        MCDI_EVENT_RX_ERR_INFO_LBN 16
#define        MCDI_EVENT_RX_ERR_INFO_WIDTH 16
#define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0
#define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
#define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
#define        MCDI_EVENT_RX_FLUSH_RXQ_OFST 0
#define        MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
#define        MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
#define        MCDI_EVENT_MC_REBOOT_COUNT_OFST 0
#define        MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
#define        MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
#define        MCDI_EVENT_MUM_ERR_TYPE_OFST 0
#define        MCDI_EVENT_MUM_ERR_TYPE_LBN 0
#define        MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
/* enum: MUM failed to load - no valid image? */
#define          MCDI_EVENT_MUM_NO_LOAD 0x1
/* enum: MUM f/w reported an exception */
#define          MCDI_EVENT_MUM_ASSERT 0x2
/* enum: MUM not kicking watchdog */
#define          MCDI_EVENT_MUM_WATCHDOG 0x3
#define        MCDI_EVENT_MUM_ERR_DATA_OFST 0
#define        MCDI_EVENT_MUM_ERR_DATA_LBN 8
#define        MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
#define        MCDI_EVENT_DBRET_SEQ_OFST 0
#define        MCDI_EVENT_DBRET_SEQ_LBN 0
#define        MCDI_EVENT_DBRET_SEQ_WIDTH 8
#define        MCDI_EVENT_SUC_ERR_TYPE_OFST 0
#define        MCDI_EVENT_SUC_ERR_TYPE_LBN 0
#define        MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8
/* enum: Corrupted or bad SUC application. */
#define          MCDI_EVENT_SUC_BAD_APP 0x1
/* enum: SUC application reported an assert. */
#define          MCDI_EVENT_SUC_ASSERT 0x2
/* enum: SUC application reported an exception. */
#define          MCDI_EVENT_SUC_EXCEPTION 0x3
/* enum: SUC watchdog timer expired. */
#define          MCDI_EVENT_SUC_WATCHDOG 0x4
#define        MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0
#define        MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8
#define        MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24
#define        MCDI_EVENT_SUC_ERR_DATA_OFST 0
#define        MCDI_EVENT_SUC_ERR_DATA_LBN 8
#define        MCDI_EVENT_SUC_ERR_DATA_WIDTH 24
#define        MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0
#define        MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0
#define        MCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 24
#define        MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0
#define        MCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 24
#define        MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
/*             Enum values, see field(s): */
/*                MCDI_EVENT/LINKCHANGE_SPEED */
#define        MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0
#define        MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 28
#define        MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1
#define        MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0
#define        MCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 29
#define        MCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 3
/*             Enum values, see field(s): */
/*                MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
#define        MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0
#define        MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0
#define        MCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 30
#define        MCDI_EVENT_MODULECHANGE_SEQ_OFST 0
#define        MCDI_EVENT_MODULECHANGE_SEQ_LBN 30
#define        MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2
#define       MCDI_EVENT_DATA_LBN 0
#define       MCDI_EVENT_DATA_WIDTH 32
/* Alias for PTP_DATA. */
#define       MCDI_EVENT_SRC_LBN 36
#define       MCDI_EVENT_SRC_WIDTH 8
/* Data associated with PTP events which doesn't fit into the main DATA field
 */
#define       MCDI_EVENT_PTP_DATA_LBN 36
#define       MCDI_EVENT_PTP_DATA_WIDTH 8
/* EF100 specific. Defined by QDMA. The phase bit, changes each time round the
 * event ring
 */
#define       MCDI_EVENT_EV_EVQ_PHASE_LBN 59
#define       MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1
#define       MCDI_EVENT_EV_CODE_LBN 60
#define       MCDI_EVENT_EV_CODE_WIDTH 4
#define       MCDI_EVENT_CODE_LBN 44
#define       MCDI_EVENT_CODE_WIDTH 8
/* enum: Event generated by host software */
#define          MCDI_EVENT_SW_EVENT 0x0
/* enum: Bad assert. */
#define          MCDI_EVENT_CODE_BADSSERT 0x1
/* enum: PM Notice. */
#define          MCDI_EVENT_CODE_PMNOTICE 0x2
/* enum: Command done. */
#define          MCDI_EVENT_CODE_CMDDONE 0x3
/* enum: Link change. */
#define          MCDI_EVENT_CODE_LINKCHANGE 0x4
/* enum: Sensor Event. */
#define          MCDI_EVENT_CODE_SENSOREVT 0x5
/* enum: Schedule error. */
#define          MCDI_EVENT_CODE_SCHEDERR 0x6
/* enum: Reboot. */
#define          MCDI_EVENT_CODE_REBOOT 0x7
/* enum: Mac stats DMA. */
#define          MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
/* enum: Firmware alert. */
#define          MCDI_EVENT_CODE_FWALERT 0x9
/* enum: Function level reset. */
#define          MCDI_EVENT_CODE_FLR 0xa
/* enum: Transmit error */
#define          MCDI_EVENT_CODE_TX_ERR 0xb
/* enum: Tx flush has completed */
#define          MCDI_EVENT_CODE_TX_FLUSH 0xc
/* enum: PTP packet received timestamp */
#define          MCDI_EVENT_CODE_PTP_RX 0xd
/* enum: PTP NIC failure */
#define          MCDI_EVENT_CODE_PTP_FAULT 0xe
/* enum: PTP PPS event */
#define          MCDI_EVENT_CODE_PTP_PPS 0xf
/* enum: Rx flush has completed */
#define          MCDI_EVENT_CODE_RX_FLUSH 0x10
/* enum: Receive error */
#define          MCDI_EVENT_CODE_RX_ERR 0x11
/* enum: AOE fault */
#define          MCDI_EVENT_CODE_AOE 0x12
/* enum: Network port calibration failed (VCAL). */
#define          MCDI_EVENT_CODE_VCAL_FAIL 0x13
/* enum: HW PPS event */
#define          MCDI_EVENT_CODE_HW_PPS 0x14
/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
 * a different format)
 */
#define          MCDI_EVENT_CODE_MC_REBOOT 0x15
/* enum: the MC has detected a parity error */
#define          MCDI_EVENT_CODE_PAR_ERR 0x16
/* enum: the MC has detected a correctable error */
#define          MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
/* enum: the MC has detected an uncorrectable error */
#define          MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
/* enum: The MC has entered offline BIST mode */
#define          MCDI_EVENT_CODE_MC_BIST 0x19
/* enum: PTP tick event providing current NIC time */
#define          MCDI_EVENT_CODE_PTP_TIME 0x1a
/* enum: MUM fault */
#define          MCDI_EVENT_CODE_MUM 0x1b
/* enum: notify the designated PF of a new authorization request */
#define          MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
/* enum: notify a function that awaits an authorization that its request has
 * been processed and it may now resend the command
 */
#define          MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
/* enum: MCDI command accepted. New commands can be issued but this command is
 * not done yet.
 */
#define          MCDI_EVENT_CODE_DBRET 0x1e
/* enum: The MC has detected a fault on the SUC */
#define          MCDI_EVENT_CODE_SUC 0x1f
/* enum: Link change. This event is sent instead of LINKCHANGE if
 * WANT_V2_LINKCHANGES was set on driver attach.
 */
#define          MCDI_EVENT_CODE_LINKCHANGE_V2 0x20
/* enum: This event is sent if WANT_V2_LINKCHANGES was set on driver attach
 * when the local device capabilities changes. This will usually correspond to
 * a module change.
 */
#define          MCDI_EVENT_CODE_MODULECHANGE 0x21
/* enum: Notification that the sensors have been added and/or removed from the
 * sensor table. This event includes the new sensor table generation count, if
 * this does not match the driver's local copy it is expected to call
 * DYNAMIC_SENSORS_LIST to refresh it.
 */
#define          MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
/* enum: Notification that a sensor has changed state as a result of a reading
 * crossing a threshold. This is sent as two events, the first event contains
 * the handle and the sensor's state (in the SRC field), and the second
 * contains the value.
 */
#define          MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
/* enum: Notification that a descriptor proxy function configuration has been
 * pushed to "live" status (visible to host). SRC field contains the handle of
 * the affected descriptor proxy function. DATA field contains the generation
 * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET /
 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
 */
#define          MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24
/* enum: Notification that a descriptor proxy function has been reset. SRC
 * field contains the handle of the affected descriptor proxy function. See
 * SF-122927-TC for details.
 */
#define          MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25
/* enum: Notification that a driver attached to a descriptor proxy function.
 * SRC field contains the handle of the affected descriptor proxy function. For
 * Virtio proxy functions this message consists of two MCDI events, where the
 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy
 * functions event length and meaning of DATA field is not yet defined. See
 * SF-122927-TC for details.
 */
#define          MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26
/* enum: Notification that the mport journal has changed since it was last read
 * and updates can be read using the MC_CMD_MAE_MPORT_READ_JOURNAL command. The
 * firmware may moderate the events so that an event is not sent for every
 * change to the journal.
 */
#define          MCDI_EVENT_CODE_MPORT_JOURNAL_CHANGE 0x27
/* enum: Artificial event generated by host and posted via MC for test
 * purposes.
 */
#define          MCDI_EVENT_CODE_TESTGEN 0xfa
#define       MCDI_EVENT_CMDDONE_DATA_OFST 0
#define       MCDI_EVENT_CMDDONE_DATA_LEN 4
#define       MCDI_EVENT_CMDDONE_DATA_LBN 0
#define       MCDI_EVENT_CMDDONE_DATA_WIDTH 32
#define       MCDI_EVENT_LINKCHANGE_DATA_OFST 0
#define       MCDI_EVENT_LINKCHANGE_DATA_LEN 4
#define       MCDI_EVENT_LINKCHANGE_DATA_LBN 0
#define       MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
#define       MCDI_EVENT_SENSOREVT_DATA_OFST 0
#define       MCDI_EVENT_SENSOREVT_DATA_LEN 4
#define       MCDI_EVENT_SENSOREVT_DATA_LBN 0
#define       MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
#define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
#define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
#define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
#define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
#define       MCDI_EVENT_TX_ERR_DATA_OFST 0
#define       MCDI_EVENT_TX_ERR_DATA_LEN 4
#define       MCDI_EVENT_TX_ERR_DATA_LBN 0
#define       MCDI_EVENT_TX_ERR_DATA_WIDTH 32
/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
 * timestamp
 */
#define       MCDI_EVENT_PTP_SECONDS_OFST 0
#define       MCDI_EVENT_PTP_SECONDS_LEN 4
#define       MCDI_EVENT_PTP_SECONDS_LBN 0
#define       MCDI_EVENT_PTP_SECONDS_WIDTH 32
/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
 * timestamp
 */
#define       MCDI_EVENT_PTP_MAJOR_OFST 0
#define       MCDI_EVENT_PTP_MAJOR_LEN 4
#define       MCDI_EVENT_PTP_MAJOR_LBN 0
#define       MCDI_EVENT_PTP_MAJOR_WIDTH 32
/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
 * of timestamp
 */
#define       MCDI_EVENT_PTP_NANOSECONDS_OFST 0
#define       MCDI_EVENT_PTP_NANOSECONDS_LEN 4
#define       MCDI_EVENT_PTP_NANOSECONDS_LBN 0
#define       MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
 * timestamp
 */
#define       MCDI_EVENT_PTP_MINOR_OFST 0
#define       MCDI_EVENT_PTP_MINOR_LEN 4
#define       MCDI_EVENT_PTP_MINOR_LBN 0
#define       MCDI_EVENT_PTP_MINOR_WIDTH 32
/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
 */
#define       MCDI_EVENT_PTP_UUID_OFST 0
#define       MCDI_EVENT_PTP_UUID_LEN 4
#define       MCDI_EVENT_PTP_UUID_LBN 0
#define       MCDI_EVENT_PTP_UUID_WIDTH 32
#define       MCDI_EVENT_RX_ERR_DATA_OFST 0
#define       MCDI_EVENT_RX_ERR_DATA_LEN 4
#define       MCDI_EVENT_RX_ERR_DATA_LBN 0
#define       MCDI_EVENT_RX_ERR_DATA_WIDTH 32
#define       MCDI_EVENT_PAR_ERR_DATA_OFST 0
#define       MCDI_EVENT_PAR_ERR_DATA_LEN 4
#define       MCDI_EVENT_PAR_ERR_DATA_LBN 0
#define       MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
#define       MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
#define       MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
#define       MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
#define       MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
#define       MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
#define       MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
#define       MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
#define       MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
/* For CODE_PTP_TIME events, the major value of the PTP clock */
#define       MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
#define       MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
#define       MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
#define       MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
#define       MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
#define       MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
/* For CODE_PTP_TIME events, most significant bits of the minor value of the
 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.
 */
#define       MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36
#define       MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8
/* For CODE_PTP_TIME events where report sync status is enabled, indicates
 * whether the NIC clock has ever been set
 */
#define       MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
#define       MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
/* For CODE_PTP_TIME events where report sync status is enabled, indicates
 * whether the NIC and System clocks are in sync
 */
#define       MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
#define       MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
 * the minor value of the PTP clock
 */
#define       MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
#define       MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
/* For CODE_PTP_TIME events, most significant bits of the minor value of the
 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.
 */
#define       MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38
#define       MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6
#define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
#define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
#define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
#define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
#define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
#define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
#define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
#define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
/* Zero means that the request has been completed or authorized, and the driver
 * should resend it. A non-zero value means that the authorization has been
 * denied, and gives the reason. Typically it will be EPERM.
 */
#define       MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
#define       MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
#define       MCDI_EVENT_DBRET_DATA_OFST 0
#define       MCDI_EVENT_DBRET_DATA_LEN 4
#define       MCDI_EVENT_DBRET_DATA_LBN 0
#define       MCDI_EVENT_DBRET_DATA_WIDTH 32
#define       MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0
#define       MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
#define       MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0
#define       MCDI_EVENT_LINKCHANGE_V2_DATA_WIDTH 32
#define       MCDI_EVENT_MODULECHANGE_DATA_OFST 0
#define       MCDI_EVENT_MODULECHANGE_DATA_LEN 4
#define       MCDI_EVENT_MODULECHANGE_DATA_LBN 0
#define       MCDI_EVENT_MODULECHANGE_DATA_WIDTH 32
/* The new generation count after a sensor has been added or deleted. */
#define       MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
#define       MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
#define       MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
#define       MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 32
/* The handle of a dynamic sensor. */
#define       MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
#define       MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
#define       MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
#define       MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 32
/* The current values of a sensor. */
#define       MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
#define       MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
#define       MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
#define       MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 32
/* The current state of a sensor. */
#define       MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36
#define       MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8
#define       MCDI_EVENT_DESC_PROXY_DATA_OFST 0
#define       MCDI_EVENT_DESC_PROXY_DATA_LEN 4
#define       MCDI_EVENT_DESC_PROXY_DATA_LBN 0
#define       MCDI_EVENT_DESC_PROXY_DATA_WIDTH 32
/* Generation count of applied configuration set */
#define       MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0
#define       MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
#define       MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0
#define       MCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 32
/* Virtio features negotiated with the host driver. First event (CONT=1)
 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
 */
#define       MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0
#define       MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
#define       MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0
#define       MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32

/* FCDI_EVENT structuredef */
#define    FCDI_EVENT_LEN 8
#define       FCDI_EVENT_CONT_LBN 32
#define       FCDI_EVENT_CONT_WIDTH 1
#define       FCDI_EVENT_LEVEL_LBN 33
#define       FCDI_EVENT_LEVEL_WIDTH 3
/* enum: Info. */
#define          FCDI_EVENT_LEVEL_INFO 0x0
/* enum: Warning. */
#define          FCDI_EVENT_LEVEL_WARN 0x1
/* enum: Error. */
#define          FCDI_EVENT_LEVEL_ERR 0x2
/* enum: Fatal. */
#define          FCDI_EVENT_LEVEL_FATAL 0x3
#define       FCDI_EVENT_DATA_OFST 0
#define       FCDI_EVENT_DATA_LEN 4
#define        FCDI_EVENT_LINK_STATE_STATUS_OFST 0
#define        FCDI_EVENT_LINK_STATE_STATUS_LBN 0
#define        FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
#define          FCDI_EVENT_LINK_DOWN 0x0 /* enum */
#define          FCDI_EVENT_LINK_UP 0x1 /* enum */
#define       FCDI_EVENT_DATA_LBN 0
#define       FCDI_EVENT_DATA_WIDTH 32
#define       FCDI_EVENT_SRC_LBN 36
#define       FCDI_EVENT_SRC_WIDTH 8
#define       FCDI_EVENT_EV_CODE_LBN 60
#define       FCDI_EVENT_EV_CODE_WIDTH 4
#define       FCDI_EVENT_CODE_LBN 44
#define       FCDI_EVENT_CODE_WIDTH 8
/* enum: The FC was rebooted. */
#define          FCDI_EVENT_CODE_REBOOT 0x1
/* enum: Bad assert. */
#define          FCDI_EVENT_CODE_ASSERT 0x2
/* enum: DDR3 test result. */
#define          FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
/* enum: Link status. */
#define          FCDI_EVENT_CODE_LINK_STATE 0x4
/* enum: A timed read is ready to be serviced. */
#define          FCDI_EVENT_CODE_TIMED_READ 0x5
/* enum: One or more PPS IN events */
#define          FCDI_EVENT_CODE_PPS_IN 0x6
/* enum: Tick event from PTP clock */
#define          FCDI_EVENT_CODE_PTP_TICK 0x7
/* enum: ECC error counters */
#define          FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
/* enum: Current status of PTP */
#define          FCDI_EVENT_CODE_PTP_STATUS 0x9
/* enum: Port id config to map MC-FC port idx */
#define          FCDI_EVENT_CODE_PORT_CONFIG 0xa
/* enum: Boot result or error code */
#define          FCDI_EVENT_CODE_BOOT_RESULT 0xb
#define       FCDI_EVENT_REBOOT_SRC_LBN 36
#define       FCDI_EVENT_REBOOT_SRC_WIDTH 8
#define          FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
#define          FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
#define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
#define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
#define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
#define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
#define       FCDI_EVENT_ASSERT_TYPE_LBN 36
#define       FCDI_EVENT_ASSERT_TYPE_WIDTH 8
#define       FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
#define       FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
#define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
#define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
#define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
#define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
#define       FCDI_EVENT_LINK_STATE_DATA_OFST 0
#define       FCDI_EVENT_LINK_STATE_DATA_LEN 4
#define       FCDI_EVENT_LINK_STATE_DATA_LBN 0
#define       FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
#define       FCDI_EVENT_PTP_STATE_OFST 0
#define       FCDI_EVENT_PTP_STATE_LEN 4
#define          FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
#define          FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
#define          FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
#define       FCDI_EVENT_PTP_STATE_LBN 0
#define       FCDI_EVENT_PTP_STATE_WIDTH 32
#define       FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36
#define       FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8
#define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
#define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
#define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
#define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
/* Index of MC port being referred to */
#define       FCDI_EVENT_PORT_CONFIG_SRC_LBN 36
#define       FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8
/* FC Port index that matches the MC port index in SRC */
#define       FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
#define       FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
#define       FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
#define       FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32
#define       FCDI_EVENT_BOOT_RESULT_OFST 0
#define       FCDI_EVENT_BOOT_RESULT_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */
#define       FCDI_EVENT_BOOT_RESULT_LBN 0
#define       FCDI_EVENT_BOOT_RESULT_WIDTH 32

/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events
 * to the MC. Note that this structure | is overlayed over a normal FCDI event
 * such that bits 32-63 containing | event code, level, source etc remain the
 * same. In this case the data | field of the header is defined to be the
 * number of timestamps
 */
#define    FCDI_EXTENDED_EVENT_PPS_LENMIN 16
#define    FCDI_EXTENDED_EVENT_PPS_LENMAX 248
#define    FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 1016
#define    FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
#define    FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)
/* Number of timestamps following */
#define       FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
#define       FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
#define       FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
#define       FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
/* Seconds field of a timestamp record */
#define       FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
#define       FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
#define       FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
#define       FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
/* Nanoseconds field of a timestamp record */
#define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
#define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
#define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
#define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
/* Timestamp records comprising the event */
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 4
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LBN 64
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_WIDTH 32
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 4
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LBN 96
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_WIDTH 32
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64

/* MUM_EVENT structuredef */
#define    MUM_EVENT_LEN 8
#define       MUM_EVENT_CONT_LBN 32
#define       MUM_EVENT_CONT_WIDTH 1
#define       MUM_EVENT_LEVEL_LBN 33
#define       MUM_EVENT_LEVEL_WIDTH 3
/* enum: Info. */
#define          MUM_EVENT_LEVEL_INFO 0x0
/* enum: Warning. */
#define          MUM_EVENT_LEVEL_WARN 0x1
/* enum: Error. */
#define          MUM_EVENT_LEVEL_ERR 0x2
/* enum: Fatal. */
#define          MUM_EVENT_LEVEL_FATAL 0x3
#define       MUM_EVENT_DATA_OFST 0
#define       MUM_EVENT_DATA_LEN 4
#define        MUM_EVENT_SENSOR_ID_OFST 0
#define        MUM_EVENT_SENSOR_ID_LBN 0
#define        MUM_EVENT_SENSOR_ID_WIDTH 8
/*             Enum values, see field(s): */
/*                MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
#define        MUM_EVENT_SENSOR_STATE_OFST 0
#define        MUM_EVENT_SENSOR_STATE_LBN 8
#define        MUM_EVENT_SENSOR_STATE_WIDTH 8
#define        MUM_EVENT_PORT_PHY_READY_OFST 0
#define        MUM_EVENT_PORT_PHY_READY_LBN 0
#define        MUM_EVENT_PORT_PHY_READY_WIDTH 1
#define        MUM_EVENT_PORT_PHY_LINK_UP_OFST 0
#define        MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
#define        MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
#define        MUM_EVENT_PORT_PHY_TX_LOL_OFST 0
#define        MUM_EVENT_PORT_PHY_TX_LOL_LBN 2
#define        MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
#define        MUM_EVENT_PORT_PHY_RX_LOL_OFST 0
#define        MUM_EVENT_PORT_PHY_RX_LOL_LBN 3
#define        MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
#define        MUM_EVENT_PORT_PHY_TX_LOS_OFST 0
#define        MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
#define        MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
#define        MUM_EVENT_PORT_PHY_RX_LOS_OFST 0
#define        MUM_EVENT_PORT_PHY_RX_LOS_LBN 5
#define        MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
#define        MUM_EVENT_PORT_PHY_TX_FAULT_OFST 0
#define        MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6
#define        MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
#define       MUM_EVENT_DATA_LBN 0
#define       MUM_EVENT_DATA_WIDTH 32
#define       MUM_EVENT_SRC_LBN 36
#define       MUM_EVENT_SRC_WIDTH 8
#define       MUM_EVENT_EV_CODE_LBN 60
#define       MUM_EVENT_EV_CODE_WIDTH 4
#define       MUM_EVENT_CODE_LBN 44
#define       MUM_EVENT_CODE_WIDTH 8
/* enum: The MUM was rebooted. */
#define          MUM_EVENT_CODE_REBOOT 0x1
/* enum: Bad assert. */
#define          MUM_EVENT_CODE_ASSERT 0x2
/* enum: Sensor failure. */
#define          MUM_EVENT_CODE_SENSOR 0x3
/* enum: Link fault has been asserted, or has cleared. */
#define          MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
#define       MUM_EVENT_SENSOR_DATA_OFST 0
#define       MUM_EVENT_SENSOR_DATA_LEN 4
#define       MUM_EVENT_SENSOR_DATA_LBN 0
#define       MUM_EVENT_SENSOR_DATA_WIDTH 32
#define       MUM_EVENT_PORT_PHY_FLAGS_OFST 0
#define       MUM_EVENT_PORT_PHY_FLAGS_LEN 4
#define       MUM_EVENT_PORT_PHY_FLAGS_LBN 0
#define       MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32
#define       MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
#define       MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
#define       MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
#define       MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32
#define       MUM_EVENT_PORT_PHY_CAPS_OFST 0
#define       MUM_EVENT_PORT_PHY_CAPS_LEN 4
#define       MUM_EVENT_PORT_PHY_CAPS_LBN 0
#define       MUM_EVENT_PORT_PHY_CAPS_WIDTH 32
#define       MUM_EVENT_PORT_PHY_TECH_OFST 0
#define       MUM_EVENT_PORT_PHY_TECH_LEN 4
#define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
#define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
#define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
#define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
#define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
#define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
#define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
#define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
#define       MUM_EVENT_PORT_PHY_TECH_LBN 0
#define       MUM_EVENT_PORT_PHY_TECH_WIDTH 32
#define       MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36
#define       MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
#define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
#define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
#define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
#define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
#define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
#define       MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40
#define       MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4


/***********************************/
/* MC_CMD_READ32
 * Read multiple 32byte words from MC memory. Note - this command really
 * belongs to INSECURE category but is required by shmboot. The command handler
 * has additional checks to reject insecure calls.
 */
#define MC_CMD_READ32 0x1
#undef MC_CMD_0x1_PRIVILEGE_CTG

#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_READ32_IN msgrequest */
#define    MC_CMD_READ32_IN_LEN 8
#define       MC_CMD_READ32_IN_ADDR_OFST 0
#define       MC_CMD_READ32_IN_ADDR_LEN 4
#define       MC_CMD_READ32_IN_NUMWORDS_OFST 4
#define       MC_CMD_READ32_IN_NUMWORDS_LEN 4

/* MC_CMD_READ32_OUT msgresponse */
#define    MC_CMD_READ32_OUT_LENMIN 4
#define    MC_CMD_READ32_OUT_LENMAX 252
#define    MC_CMD_READ32_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
#define    MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
#define       MC_CMD_READ32_OUT_BUFFER_OFST 0
#define       MC_CMD_READ32_OUT_BUFFER_LEN 4
#define       MC_CMD_READ32_OUT_BUFFER_MINNUM 1
#define       MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
#define       MC_CMD_READ32_OUT_BUFFER_MAXNUM_MCDI2 255


/***********************************/
/* MC_CMD_WRITE32
 * Write multiple 32byte words to MC memory.
 */
#define MC_CMD_WRITE32 0x2
#undef MC_CMD_0x2_PRIVILEGE_CTG

#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_WRITE32_IN msgrequest */
#define    MC_CMD_WRITE32_IN_LENMIN 8
#define    MC_CMD_WRITE32_IN_LENMAX 252
#define    MC_CMD_WRITE32_IN_LENMAX_MCDI2 1020
#define    MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
#define    MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
#define       MC_CMD_WRITE32_IN_ADDR_OFST 0
#define       MC_CMD_WRITE32_IN_ADDR_LEN 4
#define       MC_CMD_WRITE32_IN_BUFFER_OFST 4
#define       MC_CMD_WRITE32_IN_BUFFER_LEN 4
#define       MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
#define       MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
#define       MC_CMD_WRITE32_IN_BUFFER_MAXNUM_MCDI2 254

/* MC_CMD_WRITE32_OUT msgresponse */
#define    MC_CMD_WRITE32_OUT_LEN 0


/***********************************/
/* MC_CMD_COPYCODE
 * Copy MC code between two locations and jump. Note - this command really
 * belongs to INSECURE category but is required by shmboot. The command handler
 * has additional checks to reject insecure calls.
 */
#define MC_CMD_COPYCODE 0x3
#undef MC_CMD_0x3_PRIVILEGE_CTG

#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_COPYCODE_IN msgrequest */
#define    MC_CMD_COPYCODE_IN_LEN 16
/* Source address
 *
 * The main image should be entered via a copy of a single word from and to a
 * magic address, which controls various aspects of the boot. The magic address
 * is a bitfield, with each bit as documented below.
 */
#define       MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
#define       MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */
#define          MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and
 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)
 */
#define          MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,
 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see
 * below)
 */
#define          MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6
#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1
/* Destination address */
#define       MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
#define       MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
#define       MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
#define       MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
/* Address of where to jump after copy. */
#define       MC_CMD_COPYCODE_IN_JUMP_OFST 12
#define       MC_CMD_COPYCODE_IN_JUMP_LEN 4
/* enum: Control should return to the caller rather than jumping */
#define          MC_CMD_COPYCODE_JUMP_NONE 0x1

/* MC_CMD_COPYCODE_OUT msgresponse */
#define    MC_CMD_COPYCODE_OUT_LEN 0


/***********************************/
/* MC_CMD_SET_FUNC
 * Select function for function-specific commands.
 */
#define MC_CMD_SET_FUNC 0x4
#undef MC_CMD_0x4_PRIVILEGE_CTG

#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_SET_FUNC_IN msgrequest */
#define    MC_CMD_SET_FUNC_IN_LEN 4
/* Set function */
#define       MC_CMD_SET_FUNC_IN_FUNC_OFST 0
#define       MC_CMD_SET_FUNC_IN_FUNC_LEN 4

/* MC_CMD_SET_FUNC_OUT msgresponse */
#define    MC_CMD_SET_FUNC_OUT_LEN 0


/***********************************/
/* MC_CMD_GET_BOOT_STATUS
 * Get the instruction address from which the MC booted.
 */
#define MC_CMD_GET_BOOT_STATUS 0x5
#undef MC_CMD_0x5_PRIVILEGE_CTG

#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
#define    MC_CMD_GET_BOOT_STATUS_IN_LEN 0

/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
#define    MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
/* ?? */
#define       MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
#define       MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
/* enum: indicates that the MC wasn't flash booted */
#define          MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
#define       MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
#define       MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1


/***********************************/
/* MC_CMD_GET_ASSERTS
 * Get (and optionally clear) the current assertion status. Only
 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
 */
#define MC_CMD_GET_ASSERTS 0x6
#undef MC_CMD_0x6_PRIVILEGE_CTG

#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_GET_ASSERTS_IN msgrequest */
#define    MC_CMD_GET_ASSERTS_IN_LEN 4
/* Set to clear assertion */
#define       MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
#define       MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4

/* MC_CMD_GET_ASSERTS_OUT msgresponse */
#define    MC_CMD_GET_ASSERTS_OUT_LEN 140
/* Assertion status flag. */
#define       MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
#define       MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
/* enum: No assertions have failed. */
#define          MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
/* enum: A system-level assertion has failed. */
#define          MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
/* enum: A thread-level assertion has failed. */
#define          MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
/* enum: The system was reset by the watchdog. */
#define          MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
/* enum: An illegal address trap stopped the system (huntington and later) */
#define          MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
/* Failing PC value */
#define       MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
#define       MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
/* Saved GP regs */
#define       MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
#define       MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
/* enum: A magic value hinting that the value in this register at the time of
 * the failure has likely been lost.
 */
#define          MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
/* Failing thread address */
#define       MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
#define       MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
#define       MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4

/* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs
 * found on Riverhead designs
 */
#define    MC_CMD_GET_ASSERTS_OUT_V2_LEN 240
/* Assertion status flag. */
#define       MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
#define       MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
/* enum: No assertions have failed. */
/*               MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
/* enum: A system-level assertion has failed. */
/*               MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
/* enum: A thread-level assertion has failed. */
/*               MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
/* enum: The system was reset by the watchdog. */
/*               MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
/* enum: An illegal address trap stopped the system (huntington and later) */
/*               MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
/* Failing PC value */
#define       MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
#define       MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
/* Saved GP regs */
#define       MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 8
#define       MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 31
/* enum: A magic value hinting that the value in this register at the time of
 * the failure has likely been lost.
 */
/*               MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
/* Failing thread address */
#define       MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 132
#define       MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 136
#define       MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
/* Saved Special Function Registers */
#define       MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 136
#define       MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 26

/* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted
 * firmware version information
 */
#define    MC_CMD_GET_ASSERTS_OUT_V3_LEN 360
/* Assertion status flag. */
#define       MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
#define       MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
/* enum: No assertions have failed. */
/*               MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
/* enum: A system-level assertion has failed. */
/*               MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
/* enum: A thread-level assertion has failed. */
/*               MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
/* enum: The system was reset by the watchdog. */
/*               MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
/* enum: An illegal address trap stopped the system (huntington and later) */
/*               MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
/* Failing PC value */
#define       MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
#define       MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
/* Saved GP regs */
#define       MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 8
#define       MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 31
/* enum: A magic value hinting that the value in this register at the time of
 * the failure has likely been lost.
 */
/*               MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
/* Failing thread address */
#define       MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 132
#define       MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 136
#define       MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
/* Saved Special Function Registers */
#define       MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 136
#define       MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 26
/* MC firmware unique build ID (as binary SHA-1 value) */
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 240
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 20
/* MC firmware build date (as Unix timestamp) */
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LBN 2080
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_WIDTH 32
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LBN 2112
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_WIDTH 32
/* MC firmware version number */
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LBN 2144
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_WIDTH 32
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LBN 2176
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_WIDTH 32
/* MC firmware security level */
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
/* MC firmware extra version info (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 280
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 16
/* MC firmware build name (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 296
#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 64


/***********************************/
/* MC_CMD_LOG_CTRL
 * Configure the output stream for log events such as link state changes,
 * sensor notifications and MCDI completions
 */
#define MC_CMD_LOG_CTRL 0x7
#undef MC_CMD_0x7_PRIVILEGE_CTG

#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_LOG_CTRL_IN msgrequest */
#define    MC_CMD_LOG_CTRL_IN_LEN 8
/* Log destination */
#define       MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
#define       MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
/* enum: UART. */
#define          MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
/* enum: Event queue. */
#define          MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
/* Legacy argument. Must be zero. */
#define       MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
#define       MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4

/* MC_CMD_LOG_CTRL_OUT msgresponse */
#define    MC_CMD_LOG_CTRL_OUT_LEN 0


/***********************************/
/* MC_CMD_GET_VERSION
 * Get version information about adapter components.
 */
#define MC_CMD_GET_VERSION 0x8
#undef MC_CMD_0x8_PRIVILEGE_CTG

#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_GET_VERSION_IN msgrequest */
#define    MC_CMD_GET_VERSION_IN_LEN 0

/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
#define    MC_CMD_GET_VERSION_EXT_IN_LEN 4
/* placeholder, set to 0 */
#define       MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
#define       MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4

/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
#define    MC_CMD_GET_VERSION_V0_OUT_LEN 4
#define       MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
#define       MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
/* enum: Reserved version number to indicate "any" version. */
#define          MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
/* enum: Bootrom version value for Siena. */
#define          MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
/* enum: Bootrom version value for Huntington. */
#define          MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
/* enum: Bootrom version value for Medford2. */
#define          MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002

/* MC_CMD_GET_VERSION_OUT msgresponse */
#define    MC_CMD_GET_VERSION_OUT_LEN 32
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
/*            Enum values, see field(s): */
/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
#define       MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
#define       MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
/* 128bit mask of functions supported by the current firmware */
#define       MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
#define       MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
#define       MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
#define       MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
#define       MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
#define       MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4
#define       MC_CMD_GET_VERSION_OUT_VERSION_LO_LBN 192
#define       MC_CMD_GET_VERSION_OUT_VERSION_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
#define       MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4
#define       MC_CMD_GET_VERSION_OUT_VERSION_HI_LBN 224
#define       MC_CMD_GET_VERSION_OUT_VERSION_HI_WIDTH 32

/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
#define    MC_CMD_GET_VERSION_EXT_OUT_LEN 48
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
/*            Enum values, see field(s): */
/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
#define       MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
#define       MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
/* 128bit mask of functions supported by the current firmware */
#define       MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
#define       MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LBN 192
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LBN 224
#define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define       MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
#define       MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16

/* MC_CMD_GET_VERSION_V2_OUT msgresponse: Extended response providing version
 * information for all adapter components. For Riverhead based designs, base MC
 * firmware version fields refer to NMC firmware, while CMC firmware data is in
 * dedicated CMC fields. Flags indicate which data is present in the response
 * (depending on which components exist on a particular adapter)
 */
#define    MC_CMD_GET_VERSION_V2_OUT_LEN 304
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
/*            Enum values, see field(s): */
/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
#define       MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
#define       MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
/* 128bit mask of functions supported by the current firmware */
#define       MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_OFST 8
#define       MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_LEN 16
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LBN 192
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LBN 224
#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define       MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32
#define       MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16
/* Flags indicating which extended fields are valid */
#define       MC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 48
#define       MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
#define        MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
#define        MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
#define        MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 2
#define        MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
#define        MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
#define        MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
#define        MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
#define        MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
#define        MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_LBN 11
#define        MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_LBN 12
#define        MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_LBN 13
#define        MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
/* MC firmware unique build ID (as binary SHA-1 value) */
#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52
#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20
/* MC firmware security level */
#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_OFST 72
#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
/* MC firmware build name (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_OFST 76
#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_LEN 64
/* The SUC firmware version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_OFST 140
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
/* SUC firmware build date (as 64-bit Unix timestamp) */
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
/* The ID of the SUC chip. This is specific to the platform but typically
 * indicates family, memory sizes etc. See SF-116728-SW for further details.
 */
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_OFST 164
#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
/* The CMC firmware version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_OFST 168
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
/* CMC firmware build date (as 64-bit Unix timestamp) */
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
/* FPGA version as three numbers. On Riverhead based systems this field uses
 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
 * => B, ...) FPGA_VERSION[2]: Sub-revision number
 */
#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_OFST 192
#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_NUM 3
/* Extra FPGA revision information (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_OFST 204
#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_LEN 16
/* Board name / adapter model (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_OFST 220
#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_LEN 16
/* Board revision number */
#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_OFST 236
#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
/* Board serial number (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240
#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64

/* MC_CMD_GET_VERSION_V3_OUT msgresponse: Extended response providing version
 * information for all adapter components. For Riverhead based designs, base MC
 * firmware version fields refer to NMC firmware, while CMC firmware data is in
 * dedicated CMC fields. Flags indicate which data is present in the response
 * (depending on which components exist on a particular adapter)
 */
#define    MC_CMD_GET_VERSION_V3_OUT_LEN 328
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
/*            Enum values, see field(s): */
/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
#define       MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4
#define       MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4
/* 128bit mask of functions supported by the current firmware */
#define       MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_OFST 8
#define       MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_LEN 16
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_OFST 24
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_LEN 8
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_OFST 24
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LBN 192
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_OFST 28
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LBN 224
#define       MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define       MC_CMD_GET_VERSION_V3_OUT_EXTRA_OFST 32
#define       MC_CMD_GET_VERSION_V3_OUT_EXTRA_LEN 16
/* Flags indicating which extended fields are valid */
#define       MC_CMD_GET_VERSION_V3_OUT_FLAGS_OFST 48
#define       MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4
#define        MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
#define        MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
#define        MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_LBN 2
#define        MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
#define        MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
#define        MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
#define        MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
#define        MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
#define        MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_LBN 11
#define        MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_LBN 12
#define        MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_LBN 13
#define        MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
/* MC firmware unique build ID (as binary SHA-1 value) */
#define       MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_OFST 52
#define       MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_LEN 20
/* MC firmware security level */
#define       MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_OFST 72
#define       MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4
/* MC firmware build name (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_OFST 76
#define       MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_LEN 64
/* The SUC firmware version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_OFST 140
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4
/* SUC firmware build date (as 64-bit Unix timestamp) */
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_OFST 156
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LEN 8
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_OFST 156
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_OFST 160
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
/* The ID of the SUC chip. This is specific to the platform but typically
 * indicates family, memory sizes etc. See SF-116728-SW for further details.
 */
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_OFST 164
#define       MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4
/* The CMC firmware version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_OFST 168
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4
/* CMC firmware build date (as 64-bit Unix timestamp) */
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_OFST 184
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LEN 8
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_OFST 184
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_OFST 188
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
#define       MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
/* FPGA version as three numbers. On Riverhead based systems this field uses
 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
 * => B, ...) FPGA_VERSION[2]: Sub-revision number
 */
#define       MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_OFST 192
#define       MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_NUM 3
/* Extra FPGA revision information (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_OFST 204
#define       MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_LEN 16
/* Board name / adapter model (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_OFST 220
#define       MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_LEN 16
/* Board revision number */
#define       MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_OFST 236
#define       MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4
/* Board serial number (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_OFST 240
#define       MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_LEN 64
/* The version of the datapath hardware design as three number - a.b.c */
#define       MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_OFST 304
#define       MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_NUM 3
/* The version of the firmware library used to control the datapath as three
 * number - a.b.c
 */
#define       MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_OFST 316
#define       MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_NUM 3

/* MC_CMD_GET_VERSION_V4_OUT msgresponse: Extended response providing SoC
 * version information
 */
#define    MC_CMD_GET_VERSION_V4_OUT_LEN 392
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
/*            Enum values, see field(s): */
/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
#define       MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4
#define       MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4
/* 128bit mask of functions supported by the current firmware */
#define       MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_OFST 8
#define       MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_LEN 16
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_OFST 24
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_LEN 8
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_OFST 24
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LBN 192
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_OFST 28
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LBN 224
#define       MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define       MC_CMD_GET_VERSION_V4_OUT_EXTRA_OFST 32
#define       MC_CMD_GET_VERSION_V4_OUT_EXTRA_LEN 16
/* Flags indicating which extended fields are valid */
#define       MC_CMD_GET_VERSION_V4_OUT_FLAGS_OFST 48
#define       MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4
#define        MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
#define        MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
#define        MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_LBN 2
#define        MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
#define        MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
#define        MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
#define        MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
#define        MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
#define        MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_LBN 11
#define        MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_LBN 12
#define        MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_LBN 13
#define        MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
/* MC firmware unique build ID (as binary SHA-1 value) */
#define       MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_OFST 52
#define       MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_LEN 20
/* MC firmware security level */
#define       MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_OFST 72
#define       MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4
/* MC firmware build name (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_OFST 76
#define       MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_LEN 64
/* The SUC firmware version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_OFST 140
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4
/* SUC firmware build date (as 64-bit Unix timestamp) */
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_OFST 156
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LEN 8
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_OFST 156
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_OFST 160
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
/* The ID of the SUC chip. This is specific to the platform but typically
 * indicates family, memory sizes etc. See SF-116728-SW for further details.
 */
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_OFST 164
#define       MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4
/* The CMC firmware version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_OFST 168
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4
/* CMC firmware build date (as 64-bit Unix timestamp) */
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_OFST 184
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LEN 8
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_OFST 184
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_OFST 188
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
#define       MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
/* FPGA version as three numbers. On Riverhead based systems this field uses
 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
 * => B, ...) FPGA_VERSION[2]: Sub-revision number
 */
#define       MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_OFST 192
#define       MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_NUM 3
/* Extra FPGA revision information (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_OFST 204
#define       MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_LEN 16
/* Board name / adapter model (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_OFST 220
#define       MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_LEN 16
/* Board revision number */
#define       MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_OFST 236
#define       MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4
/* Board serial number (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_OFST 240
#define       MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_LEN 64
/* The version of the datapath hardware design as three number - a.b.c */
#define       MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_OFST 304
#define       MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_NUM 3
/* The version of the firmware library used to control the datapath as three
 * number - a.b.c
 */
#define       MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_OFST 316
#define       MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_NUM 3
/* The SOC boot version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_OFST 328
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4
/* The SOC uboot version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_OFST 344
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4
/* The SOC main rootfs version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
/* The SOC recovery buildroot version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4

/* MC_CMD_GET_VERSION_V5_OUT msgresponse: Extended response providing bundle
 * and board version information
 */
#define    MC_CMD_GET_VERSION_V5_OUT_LEN 424
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
/*            Enum values, see field(s): */
/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
#define       MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4
#define       MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4
/* 128bit mask of functions supported by the current firmware */
#define       MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_OFST 8
#define       MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_LEN 16
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_OFST 24
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_LEN 8
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_OFST 24
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LBN 192
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_OFST 28
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LBN 224
#define       MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define       MC_CMD_GET_VERSION_V5_OUT_EXTRA_OFST 32
#define       MC_CMD_GET_VERSION_V5_OUT_EXTRA_LEN 16
/* Flags indicating which extended fields are valid */
#define       MC_CMD_GET_VERSION_V5_OUT_FLAGS_OFST 48
#define       MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4
#define        MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
#define        MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
#define        MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_LBN 2
#define        MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
#define        MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
#define        MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
#define        MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
#define        MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
#define        MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_LBN 11
#define        MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_LBN 12
#define        MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_WIDTH 1
#define        MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_OFST 48
#define        MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_LBN 13
#define        MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
/* MC firmware unique build ID (as binary SHA-1 value) */
#define       MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_OFST 52
#define       MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_LEN 20
/* MC firmware security level */
#define       MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_OFST 72
#define       MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4
/* MC firmware build name (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_OFST 76
#define       MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_LEN 64
/* The SUC firmware version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_OFST 140
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4
/* SUC firmware build date (as 64-bit Unix timestamp) */
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_OFST 156
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LEN 8
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_OFST 156
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_OFST 160
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
/* The ID of the SUC chip. This is specific to the platform but typically
 * indicates family, memory sizes etc. See SF-116728-SW for further details.
 */
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_OFST 164
#define       MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4
/* The CMC firmware version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_OFST 168
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4
/* CMC firmware build date (as 64-bit Unix timestamp) */
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_OFST 184
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LEN 8
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_OFST 184
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_OFST 188
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
#define       MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
/* FPGA version as three numbers. On Riverhead based systems this field uses
 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
 * => B, ...) FPGA_VERSION[2]: Sub-revision number
 */
#define       MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_OFST 192
#define       MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_NUM 3
/* Extra FPGA revision information (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_OFST 204
#define       MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_LEN 16
/* Board name / adapter model (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_OFST 220
#define       MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_LEN 16
/* Board revision number */
#define       MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_OFST 236
#define       MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4
/* Board serial number (as null-terminated US-ASCII string) */
#define       MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_OFST 240
#define       MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_LEN 64
/* The version of the datapath hardware design as three number - a.b.c */
#define       MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_OFST 304
#define       MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_NUM 3
/* The version of the firmware library used to control the datapath as three
 * number - a.b.c
 */
#define       MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_OFST 316
#define       MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_NUM 3
/* The SOC boot version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_OFST 328
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4
/* The SOC uboot version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_OFST 344
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4
/* The SOC main rootfs version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
/* The SOC recovery buildroot version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
/* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
 * BOARD_REVISION field
 */
#define       MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_OFST 392
#define       MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4
/* Bundle version as four numbers - a.b.c.d */
#define       MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_OFST 408
#define       MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4
#define       MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4


/***********************************/
/* MC_CMD_PTP
 * Perform PTP operation
 */
#define MC_CMD_PTP 0xb
#undef MC_CMD_0xb_PRIVILEGE_CTG

#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_PTP_IN msgrequest */
#define    MC_CMD_PTP_IN_LEN 1
/* PTP operation code */
#define       MC_CMD_PTP_IN_OP_OFST 0
#define       MC_CMD_PTP_IN_OP_LEN 1
/* enum: Enable PTP packet timestamping operation. */
#define          MC_CMD_PTP_OP_ENABLE 0x1
/* enum: Disable PTP packet timestamping operation. */
#define          MC_CMD_PTP_OP_DISABLE 0x2
/* enum: Send a PTP packet. This operation is used on Siena and Huntington.
 * From Medford onwards it is not supported: on those platforms PTP transmit
 * timestamping is done using the fast path.
 */
#define          MC_CMD_PTP_OP_TRANSMIT 0x3
/* enum: Read the current NIC time. */
#define          MC_CMD_PTP_OP_READ_NIC_TIME 0x4
/* enum: Get the current PTP status. Note that the clock frequency returned (in
 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).
 */
#define          MC_CMD_PTP_OP_STATUS 0x5
/* enum: Adjust the PTP NIC's time. */
#define          MC_CMD_PTP_OP_ADJUST 0x6
/* enum: Synchronize host and NIC time. */
#define          MC_CMD_PTP_OP_SYNCHRONIZE 0x7
/* enum: Basic manufacturing tests. Siena PTP adapters only. */
#define          MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
/* enum: Packet based manufacturing tests. Siena PTP adapters only. */
#define          MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
/* enum: Reset some of the PTP related statistics */
#define          MC_CMD_PTP_OP_RESET_STATS 0xa
/* enum: Debug operations to MC. */
#define          MC_CMD_PTP_OP_DEBUG 0xb
/* enum: Read an FPGA register. Siena PTP adapters only. */
#define          MC_CMD_PTP_OP_FPGAREAD 0xc
/* enum: Write an FPGA register. Siena PTP adapters only. */
#define          MC_CMD_PTP_OP_FPGAWRITE 0xd
/* enum: Apply an offset to the NIC clock */
#define          MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
/* enum: Change the frequency correction applied to the NIC clock */
#define          MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
/* enum: Set the MC packet filter VLAN tags for received PTP packets.
 * Deprecated for Huntington onwards.
 */
#define          MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
/* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for
 * Huntington onwards.
 */
#define          MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
/* enum: Set the MC packet filter Domain for received PTP packets. Deprecated
 * for Huntington onwards.
 */
#define          MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
/* enum: Set the clock source. Required for snapper tests on Huntington and
 * Medford. Not implemented for Siena or Medford2.
 */
#define          MC_CMD_PTP_OP_SET_CLK_SRC 0x13
/* enum: Reset value of Timer Reg. Not implemented. */
#define          MC_CMD_PTP_OP_RST_CLK 0x14
/* enum: Enable the forwarding of PPS events to the host */
#define          MC_CMD_PTP_OP_PPS_ENABLE 0x15
/* enum: Get the time format used by this NIC for PTP operations */
#define          MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
/* enum: Get the clock attributes. NOTE- extended version of
 * MC_CMD_PTP_OP_GET_TIME_FORMAT
 */
#define          MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
/* enum: Get corrections that should be applied to the various different
 * timestamps
 */
#define          MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
/* enum: Subscribe to receive periodic time events indicating the current NIC
 * time
 */
#define          MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
/* enum: Unsubscribe to stop receiving time events */
#define          MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
 * input on the same NIC. Siena PTP adapters only.
 */
#define          MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
/* enum: Set the PTP sync status. Status is used by firmware to report to event
 * subscribers.
 */
#define          MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
/* enum: Above this for future use. */
#define          MC_CMD_PTP_OP_MAX 0x1c

/* MC_CMD_PTP_IN_ENABLE msgrequest */
#define    MC_CMD_PTP_IN_ENABLE_LEN 16
#define       MC_CMD_PTP_IN_CMD_OFST 0
#define       MC_CMD_PTP_IN_CMD_LEN 4
#define       MC_CMD_PTP_IN_PERIPH_ID_OFST 4
#define       MC_CMD_PTP_IN_PERIPH_ID_LEN 4
/* Not used, initialize to 0. Events are always sent to function relative queue
 * 0.
 */
#define       MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
#define       MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
/* PTP timestamping mode. Not used from Huntington onwards. */
#define       MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
#define       MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
/* enum: PTP, version 1 */
#define          MC_CMD_PTP_MODE_V1 0x0
/* enum: PTP, version 1, with VLAN headers - deprecated */
#define          MC_CMD_PTP_MODE_V1_VLAN 0x1
/* enum: PTP, version 2 */
#define          MC_CMD_PTP_MODE_V2 0x2
/* enum: PTP, version 2, with VLAN headers - deprecated */
#define          MC_CMD_PTP_MODE_V2_VLAN 0x3
/* enum: PTP, version 2, with improved UUID filtering */
#define          MC_CMD_PTP_MODE_V2_ENHANCED 0x4
/* enum: FCoE (seconds and microseconds) */
#define          MC_CMD_PTP_MODE_FCOE 0x5

/* MC_CMD_PTP_IN_DISABLE msgrequest */
#define    MC_CMD_PTP_IN_DISABLE_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_TRANSMIT msgrequest */
#define    MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
#define    MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
#define    MC_CMD_PTP_IN_TRANSMIT_LENMAX_MCDI2 1020
#define    MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
#define    MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Transmit packet length */
#define       MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
#define       MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
/* Transmit packet data */
#define       MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
#define       MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
#define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
#define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
#define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM_MCDI2 1008

/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
#define    MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */
#define    MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_STATUS msgrequest */
#define    MC_CMD_PTP_IN_STATUS_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_ADJUST msgrequest */
#define    MC_CMD_PTP_IN_ADJUST_LEN 24
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Frequency adjustment 40 bit fixed point ns */
#define       MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
#define       MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
#define       MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
#define       MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4
#define       MC_CMD_PTP_IN_ADJUST_FREQ_LO_LBN 64
#define       MC_CMD_PTP_IN_ADJUST_FREQ_LO_WIDTH 32
#define       MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
#define       MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4
#define       MC_CMD_PTP_IN_ADJUST_FREQ_HI_LBN 96
#define       MC_CMD_PTP_IN_ADJUST_FREQ_HI_WIDTH 32
/* enum: Number of fractional bits in frequency adjustment */
#define          MC_CMD_PTP_IN_ADJUST_BITS 0x28
/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
 * field.
 */
#define          MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
/* Time adjustment in seconds */
#define       MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
#define       MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
/* Time adjustment major value */
#define       MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
#define       MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
/* Time adjustment in nanoseconds */
#define       MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
#define       MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
/* Time adjustment minor value */
#define       MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
#define       MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4

/* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */
#define    MC_CMD_PTP_IN_ADJUST_V2_LEN 28
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Frequency adjustment 40 bit fixed point ns */
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LBN 64
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_WIDTH 32
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LBN 96
#define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_WIDTH 32
/* enum: Number of fractional bits in frequency adjustment */
/*               MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
 * field.
 */
/*               MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
/* Time adjustment in seconds */
#define       MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16
#define       MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
/* Time adjustment major value */
#define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16
#define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
/* Time adjustment in nanoseconds */
#define       MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20
#define       MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
/* Time adjustment minor value */
#define       MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20
#define       MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
/* Upper 32bits of major time offset adjustment */
#define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24
#define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4

/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
#define    MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Number of time readings to capture */
#define       MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
#define       MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
/* Host address in which to write "synchronization started" indication (64
 * bits)
 */
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LBN 96
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_WIDTH 32
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LBN 128
#define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_WIDTH 32

/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
#define    MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
#define    MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Enable or disable packet testing */
#define       MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
#define       MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4

/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */
#define    MC_CMD_PTP_IN_RESET_STATS_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_DEBUG msgrequest */
#define    MC_CMD_PTP_IN_DEBUG_LEN 12
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Debug operations */
#define       MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
#define       MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4

/* MC_CMD_PTP_IN_FPGAREAD msgrequest */
#define    MC_CMD_PTP_IN_FPGAREAD_LEN 16
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
#define       MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
#define       MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
#define       MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
#define       MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4

/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
#define    MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
#define    MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
#define    MC_CMD_PTP_IN_FPGAWRITE_LENMAX_MCDI2 1020
#define    MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
#define    MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
#define       MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
#define       MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
#define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
#define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
#define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
#define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
#define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM_MCDI2 1008

/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
#define    MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Time adjustment in seconds */
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
/* Time adjustment major value */
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
/* Time adjustment in nanoseconds */
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
/* Time adjustment minor value */
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4

/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */
#define    MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Time adjustment in seconds */
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
/* Time adjustment major value */
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
/* Time adjustment in nanoseconds */
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
/* Time adjustment minor value */
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
/* Upper 32bits of major time offset adjustment */
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16
#define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4

/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
#define    MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Frequency adjustment 40 bit fixed point ns */
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LBN 64
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_WIDTH 32
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LBN 96
#define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */

/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
#define    MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Number of VLAN tags, 0 if not VLAN */
#define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
#define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
/* Set of VLAN tags to filter against */
#define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
#define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
#define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3

/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
#define    MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* 1 to enable UUID filtering, 0 to disable */
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
/* UUID to filter against */
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LBN 96
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_WIDTH 32
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LBN 128
#define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_WIDTH 32

/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
#define    MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* 1 to enable Domain filtering, 0 to disable */
#define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
#define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
/* Domain number to filter against */
#define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
#define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4

/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
#define    MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Set the clock source. */
#define       MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
#define       MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
/* enum: Internal. */
#define          MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
/* enum: External. */
#define          MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1

/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */
#define    MC_CMD_PTP_IN_RST_CLK_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
#define    MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/* Enable or disable */
#define       MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
#define       MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
/* enum: Enable */
#define          MC_CMD_PTP_ENABLE_PPS 0x0
/* enum: Disable */
#define          MC_CMD_PTP_DISABLE_PPS 0x1
/* Not used, initialize to 0. Events are always sent to function relative queue
 * 0.
 */
#define       MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
#define       MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4

/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
#define    MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
#define    MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
#define    MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
#define    MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Original field containing queue ID. Now extended to include flags. */
#define       MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
#define       MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
#define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_OFST 8
#define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
#define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
#define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_OFST 8
#define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
#define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1

/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
#define    MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* Unsubscribe options */
#define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
#define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
/* enum: Unsubscribe a single queue */
#define          MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
/* enum: Unsubscribe all queues */
#define          MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
/* Event queue ID */
#define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
#define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4

/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
#define    MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* 1 to enable PPS test mode, 0 to disable and return result. */
#define       MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
#define       MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4

/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */
#define    MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24
/*            MC_CMD_PTP_IN_CMD_OFST 0 */
/*            MC_CMD_PTP_IN_CMD_LEN 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
/* NIC - Host System Clock Synchronization status */
#define       MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8
#define       MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
/* enum: Host System clock and NIC clock are not in sync */
#define          MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
/* enum: Host System clock and NIC clock are synchronized */
#define          MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
/* If synchronized, number of seconds until clocks should be considered to be
 * no longer in sync.
 */
#define       MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12
#define       MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
#define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16
#define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
#define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20
#define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4

/* MC_CMD_PTP_OUT msgresponse */
#define    MC_CMD_PTP_OUT_LEN 0

/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
#define    MC_CMD_PTP_OUT_TRANSMIT_LEN 8
/* Value of seconds timestamp */
#define       MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
#define       MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
/* Timestamp major value */
#define       MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
#define       MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
/* Value of nanoseconds timestamp */
#define       MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
#define       MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
/* Timestamp minor value */
#define       MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
#define       MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4

/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
#define    MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0

/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
#define    MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0

/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
#define    MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
/* Value of seconds timestamp */
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
/* Timestamp major value */
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
/* Value of nanoseconds timestamp */
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
/* Timestamp minor value */
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4

/* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */
#define    MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12
/* Value of seconds timestamp */
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
/* Timestamp major value */
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
/* Value of nanoseconds timestamp */
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
/* Timestamp minor value */
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
/* Upper 32bits of major timestamp value */
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8
#define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4

/* MC_CMD_PTP_OUT_STATUS msgresponse */
#define    MC_CMD_PTP_OUT_STATUS_LEN 64
/* Frequency of NIC's hardware clock */
#define       MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
#define       MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
/* Number of packets transmitted and timestamped */
#define       MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
#define       MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
/* Number of packets received and timestamped */
#define       MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
#define       MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
/* Number of packets timestamped by the FPGA */
#define       MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
#define       MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
/* Number of packets filter matched */
#define       MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
#define       MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
/* Number of packets not filter matched */
#define       MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
#define       MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
/* Number of PPS overflows (noise on input?) */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
/* Number of PPS bad periods */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
/* Minimum period of PPS pulse in nanoseconds */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
/* Maximum period of PPS pulse in nanoseconds */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
/* Last period of PPS pulse in nanoseconds */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
/* Mean period of PPS pulse in nanoseconds */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
/* Minimum offset of PPS pulse in nanoseconds (signed) */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
/* Maximum offset of PPS pulse in nanoseconds (signed) */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
/* Last offset of PPS pulse in nanoseconds (signed) */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
/* Mean offset of PPS pulse in nanoseconds (signed) */
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
#define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4

/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
#define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
#define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
#define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 1020
#define    MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
#define    MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
/* A set of host and NIC times */
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM_MCDI2 51
/* Host time immediately before NIC's hardware clock read */
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
/* Value of seconds timestamp */
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
/* Timestamp major value */
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
/* Value of nanoseconds timestamp */
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
/* Timestamp minor value */
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
/* Host time immediately after NIC's hardware clock read */
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
/* Number of nanoseconds waited after reading NIC's hardware clock */
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
#define       MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4

/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
#define    MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
/* Results of testing */
#define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
#define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
/* enum: Successful test */
#define          MC_CMD_PTP_MANF_SUCCESS 0x0
/* enum: FPGA load failed */
#define          MC_CMD_PTP_MANF_FPGA_LOAD 0x1
/* enum: FPGA version invalid */
#define          MC_CMD_PTP_MANF_FPGA_VERSION 0x2
/* enum: FPGA registers incorrect */
#define          MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
/* enum: Oscillator possibly not working? */
#define          MC_CMD_PTP_MANF_OSCILLATOR 0x4
/* enum: Timestamps not increasing */
#define          MC_CMD_PTP_MANF_TIMESTAMPS 0x5
/* enum: Mismatched packet count */
#define          MC_CMD_PTP_MANF_PACKET_COUNT 0x6
/* enum: Mismatched packet count (Siena filter and FPGA) */
#define          MC_CMD_PTP_MANF_FILTER_COUNT 0x7
/* enum: Not enough packets to perform timestamp check */
#define          MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
/* enum: Timestamp trigger GPIO not working */
#define          MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
/* enum: Insufficient PPS events to perform checks */
#define          MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
/* enum: PPS time event period not sufficiently close to 1s. */
#define          MC_CMD_PTP_MANF_PPS_PERIOD 0xb
/* enum: PPS time event nS reading not sufficiently close to zero. */
#define          MC_CMD_PTP_MANF_PPS_NS 0xc
/* enum: PTP peripheral registers incorrect */
#define          MC_CMD_PTP_MANF_REGISTERS 0xd
/* enum: Failed to read time from PTP peripheral */
#define          MC_CMD_PTP_MANF_CLOCK_READ 0xe
/* Presence of external oscillator */
#define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
#define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4

/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
#define    MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
/* Results of testing */
#define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
#define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
/* Number of packets received by FPGA */
#define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
#define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
/* Number of packets received by Siena filters */
#define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
#define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4

/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
#define    MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
#define    MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
#define    MC_CMD_PTP_OUT_FPGAREAD_LENMAX_MCDI2 1020
#define    MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
#define    MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
#define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
#define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
#define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
#define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
#define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM_MCDI2 1020

/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
#define    MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
/* Time format required/used by for this NIC. Applies to all PTP MCDI
 * operations that pass times between the host and firmware. If this operation
 * is not supported (older firmware) a format of seconds and nanoseconds should
 * be assumed. Note this enum is deprecated. Do not add to it- use the
 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.
 */
#define       MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
#define       MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
/* enum: Times are in seconds and nanoseconds */
#define          MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
#define          MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
/* enum: Major register has units of seconds, minor 2^-27s per tick */
#define          MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2

/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
#define    MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24
/* Time format required/used by for this NIC. Applies to all PTP MCDI
 * operations that pass times between the host and firmware. If this operation
 * is not supported (older firmware) a format of seconds and nanoseconds should
 * be assumed.
 */
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
/* enum: Times are in seconds and nanoseconds */
#define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
#define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
/* enum: Major register has units of seconds, minor 2^-27s per tick */
#define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
/* enum: Major register units are seconds, minor units are quarter nanoseconds
 */
#define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
/* Minimum acceptable value for a corrected synchronization timeset. When
 * comparing host and NIC clock times, the MC returns a set of samples that
 * contain the host start and end time, the MC time when the host start was
 * detected and the time the MC waited between reading the time and detecting
 * the host end. The corrected sync window is the difference between the host
 * end and start times minus the time that the MC waited for host end.
 */
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
/* Various PTP capabilities */
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 8
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 8
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 8
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 8
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4

/* MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2 msgresponse */
#define    MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_LEN 40
/* Time format required/used by for this NIC. Applies to all PTP MCDI
 * operations that pass times between the host and firmware. If this operation
 * is not supported (older firmware) a format of seconds and nanoseconds should
 * be assumed.
 */
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_OFST 0
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_LEN 4
/* enum: Times are in seconds and nanoseconds */
#define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_NANOSECONDS 0x0
/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
#define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_16SECONDS_8NANOSECONDS 0x1
/* enum: Major register has units of seconds, minor 2^-27s per tick */
#define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_27FRACTION 0x2
/* enum: Major register units are seconds, minor units are quarter nanoseconds
 */
#define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_QTR_NANOSECONDS 0x3
/* Minimum acceptable value for a corrected synchronization timeset. When
 * comparing host and NIC clock times, the MC returns a set of samples that
 * contain the host start and end time, the MC time when the host start was
 * detected and the time the MC waited between reading the time and detecting
 * the host end. The corrected sync window is the difference between the host
 * end and start times minus the time that the MC waited for host end.
 */
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_OFST 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_LEN 4
/* Various PTP capabilities */
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_OFST 8
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_LEN 4
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_OFST 8
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_LBN 0
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_WIDTH 1
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_OFST 8
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_LBN 1
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_WIDTH 1
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_OFST 8
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_LBN 2
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_WIDTH 1
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_OFST 8
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_LBN 3
#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_WIDTH 1
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_OFST 12
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_LEN 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_OFST 16
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_LEN 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_OFST 20
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_LEN 4
/* Minimum supported value for the FREQ field in
 * MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST and
 * MC_CMD_PTP/MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST message requests. If this message
 * response is not supported a value of -0.1 ns should be assumed, which is
 * equivalent to a -10% adjustment.
 */
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_OFST 24
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LEN 8
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_OFST 24
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LEN 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LBN 192
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_WIDTH 32
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_OFST 28
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LEN 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LBN 224
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_WIDTH 32
/* Maximum supported value for the FREQ field in
 * MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST and
 * MC_CMD_PTP/MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST message requests. If this message
 * response is not supported a value of 0.1 ns should be assumed, which is
 * equivalent to a +10% adjustment.
 */
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_OFST 32
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LEN 8
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_OFST 32
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LEN 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LBN 256
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_WIDTH 32
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_OFST 36
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LEN 4
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LBN 288
#define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_WIDTH 32

/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
#define    MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
/* Uncorrected error on PTP transmit timestamps in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
/* Uncorrected error on PTP receive timestamps in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
/* Uncorrected error on PPS output in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
/* Uncorrected error on PPS input in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4

/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */
#define    MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24
/* Uncorrected error on PTP transmit timestamps in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
/* Uncorrected error on PTP receive timestamps in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
/* Uncorrected error on PPS output in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
/* Uncorrected error on PPS input in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
/* Uncorrected error on non-PTP receive timestamps in NIC clock format */
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20
#define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4

/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
#define    MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
/* Results of testing */
#define       MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
#define       MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */

/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */
#define    MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0


/***********************************/
/* MC_CMD_CSR_READ32
 * Read 32bit words from the indirect memory map.
 */
#define MC_CMD_CSR_READ32 0xc
#undef MC_CMD_0xc_PRIVILEGE_CTG

#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_CSR_READ32_IN msgrequest */
#define    MC_CMD_CSR_READ32_IN_LEN 12
/* Address */
#define       MC_CMD_CSR_READ32_IN_ADDR_OFST 0
#define       MC_CMD_CSR_READ32_IN_ADDR_LEN 4
#define       MC_CMD_CSR_READ32_IN_STEP_OFST 4
#define       MC_CMD_CSR_READ32_IN_STEP_LEN 4
#define       MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
#define       MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4

/* MC_CMD_CSR_READ32_OUT msgresponse */
#define    MC_CMD_CSR_READ32_OUT_LENMIN 4
#define    MC_CMD_CSR_READ32_OUT_LENMAX 252
#define    MC_CMD_CSR_READ32_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
#define    MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
/* The last dword is the status, not a value read */
#define       MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
#define       MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
#define       MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
#define       MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
#define       MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM_MCDI2 255


/***********************************/
/* MC_CMD_CSR_WRITE32
 * Write 32bit dwords to the indirect memory map.
 */
#define MC_CMD_CSR_WRITE32 0xd
#undef MC_CMD_0xd_PRIVILEGE_CTG

#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_CSR_WRITE32_IN msgrequest */
#define    MC_CMD_CSR_WRITE32_IN_LENMIN 12
#define    MC_CMD_CSR_WRITE32_IN_LENMAX 252
#define    MC_CMD_CSR_WRITE32_IN_LENMAX_MCDI2 1020
#define    MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
#define    MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)
/* Address */
#define       MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
#define       MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
#define       MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
#define       MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
#define       MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
#define       MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
#define       MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
#define       MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
#define       MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM_MCDI2 253

/* MC_CMD_CSR_WRITE32_OUT msgresponse */
#define    MC_CMD_CSR_WRITE32_OUT_LEN 4
#define       MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
#define       MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4


/***********************************/
/* MC_CMD_HP
 * These commands are used for HP related features. They are grouped under one
 * MCDI command to avoid creating too many MCDI commands.
 */
#define MC_CMD_HP 0x54
#undef MC_CMD_0x54_PRIVILEGE_CTG

#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_HP_IN msgrequest */
#define    MC_CMD_HP_IN_LEN 16
/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
 * the specified address with the specified interval.When address is NULL,
 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
 * state / 2: (debug) Show temperature reported by one of the supported
 * sensors.
 */
#define       MC_CMD_HP_IN_SUBCMD_OFST 0
#define       MC_CMD_HP_IN_SUBCMD_LEN 4
/* enum: OCSD (Option Card Sensor Data) sub-command. */
#define          MC_CMD_HP_IN_OCSD_SUBCMD 0x0
/* enum: Last known valid HP sub-command. */
#define          MC_CMD_HP_IN_LAST_SUBCMD 0x0
/* The address to the array of sensor fields. (Or NULL to use a sub-command.)
 */
#define       MC_CMD_HP_IN_OCSD_ADDR_OFST 4
#define       MC_CMD_HP_IN_OCSD_ADDR_LEN 8
#define       MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
#define       MC_CMD_HP_IN_OCSD_ADDR_LO_LEN 4
#define       MC_CMD_HP_IN_OCSD_ADDR_LO_LBN 32
#define       MC_CMD_HP_IN_OCSD_ADDR_LO_WIDTH 32
#define       MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
#define       MC_CMD_HP_IN_OCSD_ADDR_HI_LEN 4
#define       MC_CMD_HP_IN_OCSD_ADDR_HI_LBN 64
#define       MC_CMD_HP_IN_OCSD_ADDR_HI_WIDTH 32
/* The requested update interval, in seconds. (Or the sub-command if ADDR is
 * NULL.)
 */
#define       MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
#define       MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4

/* MC_CMD_HP_OUT msgresponse */
#define    MC_CMD_HP_OUT_LEN 4
#define       MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
#define       MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
/* enum: OCSD stopped for this card. */
#define          MC_CMD_HP_OUT_OCSD_STOPPED 0x1
/* enum: OCSD was successfully started with the address provided. */
#define          MC_CMD_HP_OUT_OCSD_STARTED 0x2
/* enum: OCSD was already started for this card. */
#define          MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3


/***********************************/
/* MC_CMD_STACKINFO
 * Get stack information.
 */
#define MC_CMD_STACKINFO 0xf
#undef MC_CMD_0xf_PRIVILEGE_CTG

#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_STACKINFO_IN msgrequest */
#define    MC_CMD_STACKINFO_IN_LEN 0

/* MC_CMD_STACKINFO_OUT msgresponse */
#define    MC_CMD_STACKINFO_OUT_LENMIN 12
#define    MC_CMD_STACKINFO_OUT_LENMAX 252
#define    MC_CMD_STACKINFO_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
#define    MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
/* (thread ptr, stack size, free space) for each thread in system */
#define       MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
#define       MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
#define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
#define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
#define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM_MCDI2 85


/***********************************/
/* MC_CMD_MDIO_READ
 * MDIO register read.
 */
#define MC_CMD_MDIO_READ 0x10
#undef MC_CMD_0x10_PRIVILEGE_CTG

#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_MDIO_READ_IN msgrequest */
#define    MC_CMD_MDIO_READ_IN_LEN 16
/* Bus number; there are two MDIO buses: one for the internal PHY, and one for
 * external devices.
 */
#define       MC_CMD_MDIO_READ_IN_BUS_OFST 0
#define       MC_CMD_MDIO_READ_IN_BUS_LEN 4
/* enum: Internal. */
#define          MC_CMD_MDIO_BUS_INTERNAL 0x0
/* enum: External. */
#define          MC_CMD_MDIO_BUS_EXTERNAL 0x1
/* Port address */
#define       MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
#define       MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
/* Device Address or clause 22. */
#define       MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
#define       MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
 */
#define          MC_CMD_MDIO_CLAUSE22 0x20
/* Address */
#define       MC_CMD_MDIO_READ_IN_ADDR_OFST 12
#define       MC_CMD_MDIO_READ_IN_ADDR_LEN 4

/* MC_CMD_MDIO_READ_OUT msgresponse */
#define    MC_CMD_MDIO_READ_OUT_LEN 8
/* Value */
#define       MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
#define       MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
/* Status the MDIO commands return the raw status bits from the MDIO block. A
 * "good" transaction should have the DONE bit set and all other bits clear.
 */
#define       MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
#define       MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
/* enum: Good. */
#define          MC_CMD_MDIO_STATUS_GOOD 0x8


/***********************************/
/* MC_CMD_MDIO_WRITE
 * MDIO register write.
 */
#define MC_CMD_MDIO_WRITE 0x11
#undef MC_CMD_0x11_PRIVILEGE_CTG

#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_MDIO_WRITE_IN msgrequest */
#define    MC_CMD_MDIO_WRITE_IN_LEN 20
/* Bus number; there are two MDIO buses: one for the internal PHY, and one for
 * external devices.
 */
#define       MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
#define       MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
/* enum: Internal. */
/*               MC_CMD_MDIO_BUS_INTERNAL 0x0 */
/* enum: External. */
/*               MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
/* Port address */
#define       MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
#define       MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
/* Device Address or clause 22. */
#define       MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
#define       MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
 */
/*               MC_CMD_MDIO_CLAUSE22 0x20 */
/* Address */
#define       MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
#define       MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
/* Value */
#define       MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
#define       MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4

/* MC_CMD_MDIO_WRITE_OUT msgresponse */
#define    MC_CMD_MDIO_WRITE_OUT_LEN 4
/* Status; the MDIO commands return the raw status bits from the MDIO block. A
 * "good" transaction should have the DONE bit set and all other bits clear.
 */
#define       MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
#define       MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
/* enum: Good. */
/*               MC_CMD_MDIO_STATUS_GOOD 0x8 */


/***********************************/
/* MC_CMD_DBI_WRITE
 * Write DBI register(s).
 */
#define MC_CMD_DBI_WRITE 0x12
#undef MC_CMD_0x12_PRIVILEGE_CTG

#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_DBI_WRITE_IN msgrequest */
#define    MC_CMD_DBI_WRITE_IN_LENMIN 12
#define    MC_CMD_DBI_WRITE_IN_LENMAX 252
#define    MC_CMD_DBI_WRITE_IN_LENMAX_MCDI2 1020
#define    MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
#define    MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
 */
#define       MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
#define       MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
#define       MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
#define       MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
#define       MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM_MCDI2 85

/* MC_CMD_DBI_WRITE_OUT msgresponse */
#define    MC_CMD_DBI_WRITE_OUT_LEN 0

/* MC_CMD_DBIWROP_TYPEDEF structuredef */
#define    MC_CMD_DBIWROP_TYPEDEF_LEN 12
#define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
#define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
#define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
#define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
#define       MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
#define       MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
#define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4
#define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
#define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
#define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4
#define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
#define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
#define        MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4
#define        MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
#define        MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
#define       MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
#define       MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32
#define       MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
#define       MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
#define       MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
#define       MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32


/***********************************/
/* MC_CMD_PORT_READ32
 * Read a 32-bit register from the indirect port register map. The port to
 * access is implied by the Shared memory channel used.
 */
#define MC_CMD_PORT_READ32 0x14

/* MC_CMD_PORT_READ32_IN msgrequest */
#define    MC_CMD_PORT_READ32_IN_LEN 4
/* Address */
#define       MC_CMD_PORT_READ32_IN_ADDR_OFST 0
#define       MC_CMD_PORT_READ32_IN_ADDR_LEN 4

/* MC_CMD_PORT_READ32_OUT msgresponse */
#define    MC_CMD_PORT_READ32_OUT_LEN 8
/* Value */
#define       MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
#define       MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
/* Status */
#define       MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
#define       MC_CMD_PORT_READ32_OUT_STATUS_LEN 4


/***********************************/
/* MC_CMD_PORT_WRITE32
 * Write a 32-bit register to the indirect port register map. The port to
 * access is implied by the Shared memory channel used.
 */
#define MC_CMD_PORT_WRITE32 0x15

/* MC_CMD_PORT_WRITE32_IN msgrequest */
#define    MC_CMD_PORT_WRITE32_IN_LEN 8
/* Address */
#define       MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
#define       MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
/* Value */
#define       MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
#define       MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4

/* MC_CMD_PORT_WRITE32_OUT msgresponse */
#define    MC_CMD_PORT_WRITE32_OUT_LEN 4
/* Status */
#define       MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
#define       MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4


/***********************************/
/* MC_CMD_PORT_READ128
 * Read a 128-bit register from the indirect port register map. The port to
 * access is implied by the Shared memory channel used.
 */
#define MC_CMD_PORT_READ128 0x16

/* MC_CMD_PORT_READ128_IN msgrequest */
#define    MC_CMD_PORT_READ128_IN_LEN 4
/* Address */
#define       MC_CMD_PORT_READ128_IN_ADDR_OFST 0
#define       MC_CMD_PORT_READ128_IN_ADDR_LEN 4

/* MC_CMD_PORT_READ128_OUT msgresponse */
#define    MC_CMD_PORT_READ128_OUT_LEN 20
/* Value */
#define       MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
#define       MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
/* Status */
#define       MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
#define       MC_CMD_PORT_READ128_OUT_STATUS_LEN 4


/***********************************/
/* MC_CMD_PORT_WRITE128
 * Write a 128-bit register to the indirect port register map. The port to
 * access is implied by the Shared memory channel used.
 */
#define MC_CMD_PORT_WRITE128 0x17

/* MC_CMD_PORT_WRITE128_IN msgrequest */
#define    MC_CMD_PORT_WRITE128_IN_LEN 20
/* Address */
#define       MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
#define       MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
/* Value */
#define       MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
#define       MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16

/* MC_CMD_PORT_WRITE128_OUT msgresponse */
#define    MC_CMD_PORT_WRITE128_OUT_LEN 4
/* Status */
#define       MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
#define       MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4

/* MC_CMD_CAPABILITIES structuredef */
#define    MC_CMD_CAPABILITIES_LEN 4
/* Small buf table. */
#define       MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
#define       MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
/* Turbo mode (for Maranello). */
#define       MC_CMD_CAPABILITIES_TURBO_LBN 1
#define       MC_CMD_CAPABILITIES_TURBO_WIDTH 1
/* Turbo mode active (for Maranello). */
#define       MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2
#define       MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
/* PTP offload. */
#define       MC_CMD_CAPABILITIES_PTP_LBN 3
#define       MC_CMD_CAPABILITIES_PTP_WIDTH 1
/* AOE mode. */
#define       MC_CMD_CAPABILITIES_AOE_LBN 4
#define       MC_CMD_CAPABILITIES_AOE_WIDTH 1
/* AOE mode active. */
#define       MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5
#define       MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
/* AOE mode active. */
#define       MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6
#define       MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
#define       MC_CMD_CAPABILITIES_RESERVED_LBN 7
#define       MC_CMD_CAPABILITIES_RESERVED_WIDTH 25


/***********************************/
/* MC_CMD_GET_BOARD_CFG
 * Returns the MC firmware configuration structure.
 */
#define MC_CMD_GET_BOARD_CFG 0x18
#undef MC_CMD_0x18_PRIVILEGE_CTG

#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_GET_BOARD_CFG_IN msgrequest */
#define    MC_CMD_GET_BOARD_CFG_IN_LEN 0

/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
#define    MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
#define    MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
#define    MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 136
#define    MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
#define    MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
#define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
#define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
#define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
#define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
/* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on
 * EF10 and later (use MC_CMD_GET_CAPABILITIES).
 */
#define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
#define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
/* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on
 * EF10 and later (use MC_CMD_GET_CAPABILITIES).
 */
#define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
#define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
/* Base MAC address for Siena Port0. Unused on EF10 and later (use
 * MC_CMD_GET_MAC_ADDRESSES).
 */
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
/* Base MAC address for Siena Port1. Unused on EF10 and later (use
 * MC_CMD_GET_MAC_ADDRESSES).
 */
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
/* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use
 * MC_CMD_GET_MAC_ADDRESSES).
 */
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
/* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use
 * MC_CMD_GET_MAC_ADDRESSES).
 */
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
/* Increment between addresses in MAC address pool for Siena Port0. Unused on
 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
 */
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
/* Increment between addresses in MAC address pool for Siena Port1. Unused on
 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
 */
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
#define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
/* Siena only. This field contains a 16-bit value for each of the types of
 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a
 * specific board type, but otherwise have no meaning to the MC; they are used
 * by the driver to manage selection of appropriate firmware updates. Unused on
 * EF10 and later (use MC_CMD_NVRAM_METADATA).
 */
#define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
#define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
#define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
#define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
#define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 32


/***********************************/
/* MC_CMD_DBI_READX
 * Read DBI register(s) -- extended functionality
 */
#define MC_CMD_DBI_READX 0x19
#undef MC_CMD_0x19_PRIVILEGE_CTG

#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_DBI_READX_IN msgrequest */
#define    MC_CMD_DBI_READX_IN_LENMIN 8
#define    MC_CMD_DBI_READX_IN_LENMAX 248
#define    MC_CMD_DBI_READX_IN_LENMAX_MCDI2 1016
#define    MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
#define    MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
/* Each Read op consists of an address (offset 0), VF/CS2) */
#define       MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
#define       MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
#define       MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
#define       MC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 4
#define       MC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 0
#define       MC_CMD_DBI_READX_IN_DBIRDOP_LO_WIDTH 32
#define       MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
#define       MC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 4
#define       MC_CMD_DBI_READX_IN_DBIRDOP_HI_LBN 32
#define       MC_CMD_DBI_READX_IN_DBIRDOP_HI_WIDTH 32
#define       MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
#define       MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
#define       MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127

/* MC_CMD_DBI_READX_OUT msgresponse */
#define    MC_CMD_DBI_READX_OUT_LENMIN 4
#define    MC_CMD_DBI_READX_OUT_LENMAX 252
#define    MC_CMD_DBI_READX_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
#define    MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
/* Value */
#define       MC_CMD_DBI_READX_OUT_VALUE_OFST 0
#define       MC_CMD_DBI_READX_OUT_VALUE_LEN 4
#define       MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
#define       MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
#define       MC_CMD_DBI_READX_OUT_VALUE_MAXNUM_MCDI2 255

/* MC_CMD_DBIRDOP_TYPEDEF structuredef */
#define    MC_CMD_DBIRDOP_TYPEDEF_LEN 8
#define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
#define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
#define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
#define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
#define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
#define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
#define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4
#define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
#define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
#define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4
#define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
#define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
#define        MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4
#define        MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
#define        MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
#define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
#define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32


/***********************************/
/* MC_CMD_SET_RAND_SEED
 * Set the 16byte seed for the MC pseudo-random generator.
 */
#define MC_CMD_SET_RAND_SEED 0x1a
#undef MC_CMD_0x1a_PRIVILEGE_CTG

#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_SET_RAND_SEED_IN msgrequest */
#define    MC_CMD_SET_RAND_SEED_IN_LEN 16
/* Seed value. */
#define       MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
#define       MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16

/* MC_CMD_SET_RAND_SEED_OUT msgresponse */
#define    MC_CMD_SET_RAND_SEED_OUT_LEN 0


/***********************************/
/* MC_CMD_LTSSM_HIST
 * Retrieve the history of the LTSSM, if the build supports it.
 */
#define MC_CMD_LTSSM_HIST 0x1b

/* MC_CMD_LTSSM_HIST_IN msgrequest */
#define    MC_CMD_LTSSM_HIST_IN_LEN 0

/* MC_CMD_LTSSM_HIST_OUT msgresponse */
#define    MC_CMD_LTSSM_HIST_OUT_LENMIN 0
#define    MC_CMD_LTSSM_HIST_OUT_LENMAX 252
#define    MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
#define    MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
/* variable number of LTSSM values, as bytes. The history is read-to-clear. */
#define       MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
#define       MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
#define       MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
#define       MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
#define       MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM_MCDI2 255


/***********************************/
/* MC_CMD_DRV_ATTACH
 * Inform MCPU that this port is managed on the host (i.e. driver active). For
 * Huntington, also request the preferred datapath firmware to use if possible
 * (it may not be possible for this request to be fulfilled; the driver must
 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
 * features are actually available). The FIRMWARE_ID field is ignored by older
 * platforms.
 */
#define MC_CMD_DRV_ATTACH 0x1c
#undef MC_CMD_0x1c_PRIVILEGE_CTG

#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_DRV_ATTACH_IN msgrequest */
#define    MC_CMD_DRV_ATTACH_IN_LEN 12
/* new state to set if UPDATE=1 */
#define       MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
#define       MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
#define        MC_CMD_DRV_ATTACH_OFST 0
#define        MC_CMD_DRV_ATTACH_LBN 0
#define        MC_CMD_DRV_ATTACH_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
#define        MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
#define        MC_CMD_DRV_PREBOOT_OFST 0
#define        MC_CMD_DRV_PREBOOT_LBN 1
#define        MC_CMD_DRV_PREBOOT_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
#define        MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
#define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3
#define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
#define        MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
#define        MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 5
#define        MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1
/* 1 to set new state, or 0 to just report the existing state */
#define       MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
#define       MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
/* preferred datapath firmware (for Huntington; ignored for Siena) */
#define       MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
#define       MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
/* enum: Prefer to use full featured firmware */
#define          MC_CMD_FW_FULL_FEATURED 0x0
/* enum: Prefer to use firmware with fewer features but lower latency */
#define          MC_CMD_FW_LOW_LATENCY 0x1
/* enum: Prefer to use firmware for SolarCapture packed stream mode */
#define          MC_CMD_FW_PACKED_STREAM 0x2
/* enum: Prefer to use firmware with fewer features and simpler TX event
 * batching but higher TX packet rate
 */
#define          MC_CMD_FW_HIGH_TX_RATE 0x3
/* enum: Reserved value */
#define          MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
/* enum: Prefer to use firmware with additional "rules engine" filtering
 * support
 */
#define          MC_CMD_FW_RULES_ENGINE 0x5
/* enum: Prefer to use firmware with additional DPDK support */
#define          MC_CMD_FW_DPDK 0x6
/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
 * bug69716)
 */
#define          MC_CMD_FW_L3XUDP 0x7
/* enum: Requests that the MC keep whatever datapath firmware is currently
 * running. It's used for test purposes, where we want to be able to shmboot
 * special test firmware variants. This option is only recognised in eftest
 * (i.e. non-production) builds.
 */
#define          MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
/* enum: Only this option is allowed for non-admin functions */
#define          MC_CMD_FW_DONT_CARE 0xffffffff

/* MC_CMD_DRV_ATTACH_IN_V2 msgrequest: Updated DRV_ATTACH to include driver
 * version
 */
#define    MC_CMD_DRV_ATTACH_IN_V2_LEN 32
/* new state to set if UPDATE=1 */
#define       MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0
#define       MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
/*             MC_CMD_DRV_ATTACH_OFST 0 */
/*             MC_CMD_DRV_ATTACH_LBN 0 */
/*             MC_CMD_DRV_ATTACH_WIDTH 1 */
#define        MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0
#define        MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1
/*             MC_CMD_DRV_PREBOOT_OFST 0 */
/*             MC_CMD_DRV_PREBOOT_LBN 1 */
/*             MC_CMD_DRV_PREBOOT_WIDTH 1 */
#define        MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1
#define        MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 2
#define        MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 3
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 5
#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1
/* 1 to set new state, or 0 to just report the existing state */
#define       MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
#define       MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
/* preferred datapath firmware (for Huntington; ignored for Siena) */
#define       MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_OFST 8
#define       MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
/* enum: Prefer to use full featured firmware */
/*               MC_CMD_FW_FULL_FEATURED 0x0 */
/* enum: Prefer to use firmware with fewer features but lower latency */
/*               MC_CMD_FW_LOW_LATENCY 0x1 */
/* enum: Prefer to use firmware for SolarCapture packed stream mode */
/*               MC_CMD_FW_PACKED_STREAM 0x2 */
/* enum: Prefer to use firmware with fewer features and simpler TX event
 * batching but higher TX packet rate
 */
/*               MC_CMD_FW_HIGH_TX_RATE 0x3 */
/* enum: Reserved value */
/*               MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */
/* enum: Prefer to use firmware with additional "rules engine" filtering
 * support
 */
/*               MC_CMD_FW_RULES_ENGINE 0x5 */
/* enum: Prefer to use firmware with additional DPDK support */
/*               MC_CMD_FW_DPDK 0x6 */
/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
 * bug69716)
 */
/*               MC_CMD_FW_L3XUDP 0x7 */
/* enum: Requests that the MC keep whatever datapath firmware is currently
 * running. It's used for test purposes, where we want to be able to shmboot
 * special test firmware variants. This option is only recognised in eftest
 * (i.e. non-production) builds.
 */
/*               MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */
/* enum: Only this option is allowed for non-admin functions */
/*               MC_CMD_FW_DONT_CARE 0xffffffff */
/* Version of the driver to be reported by management protocols (e.g. NC-SI)
 * handled by the NIC. This is a zero-terminated ASCII string.
 */
#define       MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_OFST 12
#define       MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN 20

/* MC_CMD_DRV_ATTACH_OUT msgresponse */
#define    MC_CMD_DRV_ATTACH_OUT_LEN 4
/* previous or existing state, see the bitmask at NEW_STATE */
#define       MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
#define       MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4

/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
#define    MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
/* previous or existing state, see the bitmask at NEW_STATE */
#define       MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
#define       MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
/* Flags associated with this function */
#define       MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
#define       MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
/* enum: Labels the lowest-numbered function visible to the OS */
#define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
/* enum: The function can control the link state of the physical port it is
 * bound to.
 */
#define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
/* enum: The function can perform privileged operations */
#define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
/* enum: The function does not have an active port associated with it. The port
 * refers to the Sorrento external FPGA port.
 */
#define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
/* enum: If set, indicates that VI spreading is currently enabled. Will always
 * indicate the current state, regardless of the value in the WANT_VI_SPREADING
 * input.
 */
#define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
/* enum: Used during development only. Should no longer be used. */
#define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
/* enum: If set, indicates that TX only spreading is enabled. Even-numbered
 * TXQs will use one engine, and odd-numbered TXQs will use the other. This
 * also has the effect that only even-numbered RXQs will receive traffic.
 */
#define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5


/***********************************/
/* MC_CMD_SHMUART
 * Route UART output to circular buffer in shared memory instead.
 */
#define MC_CMD_SHMUART 0x1f

/* MC_CMD_SHMUART_IN msgrequest */
#define    MC_CMD_SHMUART_IN_LEN 4
/* ??? */
#define       MC_CMD_SHMUART_IN_FLAG_OFST 0
#define       MC_CMD_SHMUART_IN_FLAG_LEN 4

/* MC_CMD_SHMUART_OUT msgresponse */
#define    MC_CMD_SHMUART_OUT_LEN 0


/***********************************/
/* MC_CMD_PORT_RESET
 * Generic per-port reset. There is no equivalent for per-board reset. Locks
 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
 * use MC_CMD_ENTITY_RESET instead.
 */
#define MC_CMD_PORT_RESET 0x20
#undef MC_CMD_0x20_PRIVILEGE_CTG

#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_PORT_RESET_IN msgrequest */
#define    MC_CMD_PORT_RESET_IN_LEN 0

/* MC_CMD_PORT_RESET_OUT msgresponse */
#define    MC_CMD_PORT_RESET_OUT_LEN 0


/***********************************/
/* MC_CMD_ENTITY_RESET
 * Generic per-resource reset. There is no equivalent for per-board reset.
 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
 */
#define MC_CMD_ENTITY_RESET 0x20
/*      MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */

/* MC_CMD_ENTITY_RESET_IN msgrequest */
#define    MC_CMD_ENTITY_RESET_IN_LEN 4
/* Optional flags field. Omitting this will perform a "legacy" reset action
 * (TBD).
 */
#define       MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
#define       MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
#define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0
#define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
#define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1

/* MC_CMD_ENTITY_RESET_OUT msgresponse */
#define    MC_CMD_ENTITY_RESET_OUT_LEN 0


/***********************************/
/* MC_CMD_PCIE_CREDITS
 * Read instantaneous and minimum flow control thresholds.
 */
#define MC_CMD_PCIE_CREDITS 0x21

/* MC_CMD_PCIE_CREDITS_IN msgrequest */
#define    MC_CMD_PCIE_CREDITS_IN_LEN 8
/* poll period. 0 is disabled */
#define       MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
#define       MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
/* wipe statistics */
#define       MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
#define       MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4

/* MC_CMD_PCIE_CREDITS_OUT msgresponse */
#define    MC_CMD_PCIE_CREDITS_OUT_LEN 16
#define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
#define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
#define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
#define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
#define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
#define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
#define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
#define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
#define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
#define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
#define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
#define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
#define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
#define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
#define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
#define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2


/***********************************/
/* MC_CMD_RXD_MONITOR
 * Get histogram of RX queue fill level.
 */
#define MC_CMD_RXD_MONITOR 0x22

/* MC_CMD_RXD_MONITOR_IN msgrequest */
#define    MC_CMD_RXD_MONITOR_IN_LEN 12
#define       MC_CMD_RXD_MONITOR_IN_QID_OFST 0
#define       MC_CMD_RXD_MONITOR_IN_QID_LEN 4
#define       MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
#define       MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
#define       MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
#define       MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4

/* MC_CMD_RXD_MONITOR_OUT msgresponse */
#define    MC_CMD_RXD_MONITOR_OUT_LEN 80
#define       MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
#define       MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
#define       MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
#define       MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
#define       MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4


/***********************************/
/* MC_CMD_PUTS
 * Copy the given ASCII string out onto UART and/or out of the network port.
 */
#define MC_CMD_PUTS 0x23
#undef MC_CMD_0x23_PRIVILEGE_CTG

#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_PUTS_IN msgrequest */
#define    MC_CMD_PUTS_IN_LENMIN 13
#define    MC_CMD_PUTS_IN_LENMAX 252
#define    MC_CMD_PUTS_IN_LENMAX_MCDI2 1020
#define    MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
#define    MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
#define       MC_CMD_PUTS_IN_DEST_OFST 0
#define       MC_CMD_PUTS_IN_DEST_LEN 4
#define        MC_CMD_PUTS_IN_UART_OFST 0
#define        MC_CMD_PUTS_IN_UART_LBN 0
#define        MC_CMD_PUTS_IN_UART_WIDTH 1
#define        MC_CMD_PUTS_IN_PORT_OFST 0
#define        MC_CMD_PUTS_IN_PORT_LBN 1
#define        MC_CMD_PUTS_IN_PORT_WIDTH 1
#define       MC_CMD_PUTS_IN_DHOST_OFST 4
#define       MC_CMD_PUTS_IN_DHOST_LEN 6
#define       MC_CMD_PUTS_IN_STRING_OFST 12
#define       MC_CMD_PUTS_IN_STRING_LEN 1
#define       MC_CMD_PUTS_IN_STRING_MINNUM 1
#define       MC_CMD_PUTS_IN_STRING_MAXNUM 240
#define       MC_CMD_PUTS_IN_STRING_MAXNUM_MCDI2 1008

/* MC_CMD_PUTS_OUT msgresponse */
#define    MC_CMD_PUTS_OUT_LEN 0


/***********************************/
/* MC_CMD_GET_PHY_CFG
 * Report PHY configuration. This guarantees to succeed even if the PHY is in a
 * 'zombie' state. Locks required: None
 */
#define MC_CMD_GET_PHY_CFG 0x24
#undef MC_CMD_0x24_PRIVILEGE_CTG

#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_GET_PHY_CFG_IN msgrequest */
#define    MC_CMD_GET_PHY_CFG_IN_LEN 0

/* MC_CMD_GET_PHY_CFG_OUT msgresponse */
#define    MC_CMD_GET_PHY_CFG_OUT_LEN 72
/* flags */
#define       MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
#define       MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
#define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0
#define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
#define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
#define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0
#define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
#define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
#define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0
#define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
#define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
#define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0
#define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
#define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
#define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0
#define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
#define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
#define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0
#define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
#define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
#define        MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0
#define        MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
#define        MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
/* ?? */
#define       MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
#define       MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
/* Bitmask of supported capabilities */
#define       MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
#define       MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
#define        MC_CMD_PHY_CAP_10HDX_OFST 8
#define        MC_CMD_PHY_CAP_10HDX_LBN 1
#define        MC_CMD_PHY_CAP_10HDX_WIDTH 1
#define        MC_CMD_PHY_CAP_10FDX_OFST 8
#define        MC_CMD_PHY_CAP_10FDX_LBN 2
#define        MC_CMD_PHY_CAP_10FDX_WIDTH 1
#define        MC_CMD_PHY_CAP_100HDX_OFST 8
#define        MC_CMD_PHY_CAP_100HDX_LBN 3
#define        MC_CMD_PHY_CAP_100HDX_WIDTH 1
#define        MC_CMD_PHY_CAP_100FDX_OFST 8
#define        MC_CMD_PHY_CAP_100FDX_LBN 4
#define        MC_CMD_PHY_CAP_100FDX_WIDTH 1
#define        MC_CMD_PHY_CAP_1000HDX_OFST 8
#define        MC_CMD_PHY_CAP_1000HDX_LBN 5
#define        MC_CMD_PHY_CAP_1000HDX_WIDTH 1
#define        MC_CMD_PHY_CAP_1000FDX_OFST 8
#define        MC_CMD_PHY_CAP_1000FDX_LBN 6
#define        MC_CMD_PHY_CAP_1000FDX_WIDTH 1
#define        MC_CMD_PHY_CAP_10000FDX_OFST 8
#define        MC_CMD_PHY_CAP_10000FDX_LBN 7
#define        MC_CMD_PHY_CAP_10000FDX_WIDTH 1
#define        MC_CMD_PHY_CAP_PAUSE_OFST 8
#define        MC_CMD_PHY_CAP_PAUSE_LBN 8
#define        MC_CMD_PHY_CAP_PAUSE_WIDTH 1
#define        MC_CMD_PHY_CAP_ASYM_OFST 8
#define        MC_CMD_PHY_CAP_ASYM_LBN 9
#define        MC_CMD_PHY_CAP_ASYM_WIDTH 1
#define        MC_CMD_PHY_CAP_AN_OFST 8
#define        MC_CMD_PHY_CAP_AN_LBN 10
#define        MC_CMD_PHY_CAP_AN_WIDTH 1
#define        MC_CMD_PHY_CAP_40000FDX_OFST 8
#define        MC_CMD_PHY_CAP_40000FDX_LBN 11
#define        MC_CMD_PHY_CAP_40000FDX_WIDTH 1
#define        MC_CMD_PHY_CAP_DDM_OFST 8
#define        MC_CMD_PHY_CAP_DDM_LBN 12
#define        MC_CMD_PHY_CAP_DDM_WIDTH 1
#define        MC_CMD_PHY_CAP_100000FDX_OFST 8
#define        MC_CMD_PHY_CAP_100000FDX_LBN 13
#define        MC_CMD_PHY_CAP_100000FDX_WIDTH 1
#define        MC_CMD_PHY_CAP_25000FDX_OFST 8
#define        MC_CMD_PHY_CAP_25000FDX_LBN 14
#define        MC_CMD_PHY_CAP_25000FDX_WIDTH 1
#define        MC_CMD_PHY_CAP_50000FDX_OFST 8
#define        MC_CMD_PHY_CAP_50000FDX_LBN 15
#define        MC_CMD_PHY_CAP_50000FDX_WIDTH 1
#define        MC_CMD_PHY_CAP_BASER_FEC_OFST 8
#define        MC_CMD_PHY_CAP_BASER_FEC_LBN 16
#define        MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
#define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_OFST 8
#define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17
#define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
#define        MC_CMD_PHY_CAP_RS_FEC_OFST 8
#define        MC_CMD_PHY_CAP_RS_FEC_LBN 18
#define        MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
#define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_OFST 8
#define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19
#define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
#define        MC_CMD_PHY_CAP_25G_BASER_FEC_OFST 8
#define        MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20
#define        MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
#define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 8
#define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21
#define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
/* ?? */
#define       MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
#define       MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
/* ?? */
#define       MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
#define       MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
/* ?? */
#define       MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
#define       MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
/* ?? */
#define       MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
#define       MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
/* ?? */
#define       MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
#define       MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
/* enum: Xaui. */
#define          MC_CMD_MEDIA_XAUI 0x1
/* enum: CX4. */
#define          MC_CMD_MEDIA_CX4 0x2
/* enum: KX4. */
#define          MC_CMD_MEDIA_KX4 0x3
/* enum: XFP Far. */
#define          MC_CMD_MEDIA_XFP 0x4
/* enum: SFP+. */
#define          MC_CMD_MEDIA_SFP_PLUS 0x5
/* enum: 10GBaseT. */
#define          MC_CMD_MEDIA_BASE_T 0x6
/* enum: QSFP+. */
#define          MC_CMD_MEDIA_QSFP_PLUS 0x7
/* enum: DSFP. */
#define          MC_CMD_MEDIA_DSFP 0x8
#define       MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
#define       MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
/* enum: Native clause 22 */
#define          MC_CMD_MMD_CLAUSE22 0x0
#define          MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
#define          MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
#define          MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
#define          MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
#define          MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
#define          MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
#define          MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
/* enum: Clause22 proxied over clause45 by PHY. */
#define          MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
#define          MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
#define          MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
#define       MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
#define       MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20


/***********************************/
/* MC_CMD_START_BIST
 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
 */
#define MC_CMD_START_BIST 0x25
#undef MC_CMD_0x25_PRIVILEGE_CTG

#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_START_BIST_IN msgrequest */
#define    MC_CMD_START_BIST_IN_LEN 4
/* Type of test. */
#define       MC_CMD_START_BIST_IN_TYPE_OFST 0
#define       MC_CMD_START_BIST_IN_TYPE_LEN 4
/* enum: Run the PHY's short cable BIST. */
#define          MC_CMD_PHY_BIST_CABLE_SHORT 0x1
/* enum: Run the PHY's long cable BIST. */
#define          MC_CMD_PHY_BIST_CABLE_LONG 0x2
/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
#define          MC_CMD_BPX_SERDES_BIST 0x3
/* enum: Run the MC loopback tests. */
#define          MC_CMD_MC_LOOPBACK_BIST 0x4
/* enum: Run the PHY's standard BIST. */
#define          MC_CMD_PHY_BIST 0x5
/* enum: Run MC RAM test. */
#define          MC_CMD_MC_MEM_BIST 0x6
/* enum: Run Port RAM test. */
#define          MC_CMD_PORT_MEM_BIST 0x7
/* enum: Run register test. */
#define          MC_CMD_REG_BIST 0x8

/* MC_CMD_START_BIST_OUT msgresponse */
#define    MC_CMD_START_BIST_OUT_LEN 0


/***********************************/
/* MC_CMD_POLL_BIST
 * Poll for BIST completion. Returns a single status code, and optionally some
 * PHY specific bist output. The driver should only consume the BIST output
 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
 * successfully parse the BIST output, it should still respect the pass/Fail in
 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
 * EACCES (if PHY_LOCK is not held).
 */
#define MC_CMD_POLL_BIST 0x26
#undef MC_CMD_0x26_PRIVILEGE_CTG

#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_POLL_BIST_IN msgrequest */
#define    MC_CMD_POLL_BIST_IN_LEN 0

/* MC_CMD_POLL_BIST_OUT msgresponse */
#define    MC_CMD_POLL_BIST_OUT_LEN 8
/* result */
#define       MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
#define       MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
/* enum: Running. */
#define          MC_CMD_POLL_BIST_RUNNING 0x1
/* enum: Passed. */
#define          MC_CMD_POLL_BIST_PASSED 0x2
/* enum: Failed. */
#define          MC_CMD_POLL_BIST_FAILED 0x3
/* enum: Timed-out. */
#define          MC_CMD_POLL_BIST_TIMEOUT 0x4
#define       MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
#define       MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4

/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
#define    MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
/* result */
/*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
/*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
/*            Enum values, see field(s): */
/*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
/* Status of each channel A */
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
/* enum: Ok. */
#define          MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
/* enum: Open. */
#define          MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
/* enum: Intra-pair short. */
#define          MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
/* enum: Inter-pair short. */
#define          MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
/* enum: Busy. */
#define          MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
/* Status of each channel B */
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
/*            Enum values, see field(s): */
/*               CABLE_STATUS_A */
/* Status of each channel C */
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
/*            Enum values, see field(s): */
/*               CABLE_STATUS_A */
/* Status of each channel D */
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
#define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
/*            Enum values, see field(s): */
/*               CABLE_STATUS_A */

/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
#define    MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
/* result */
/*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
/*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
/*            Enum values, see field(s): */
/*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
#define       MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
#define       MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
/* enum: Complete. */
#define          MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
/* enum: Bus switch off I2C write. */
#define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
/* enum: Bus switch off I2C no access IO exp. */
#define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
/* enum: Bus switch off I2C no access module. */
#define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
/* enum: IO exp I2C configure. */
#define          MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
/* enum: Bus switch I2C no cross talk. */
#define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
/* enum: Module presence. */
#define          MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
/* enum: Module ID I2C access. */
#define          MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
/* enum: Module ID sane value. */
#define          MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8

/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
#define    MC_CMD_POLL_BIST_OUT_MEM_LEN 36
/* result */
/*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
/*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
/*            Enum values, see field(s): */
/*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
#define       MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
#define       MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
/* enum: Test has completed. */
#define          MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
/* enum: RAM test - walk ones. */
#define          MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
/* enum: RAM test - walk zeros. */
#define          MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
/* enum: RAM test - walking inversions zeros/ones. */
#define          MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
/* enum: RAM test - walking inversions checkerboard. */
#define          MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
/* enum: Register test - set / clear individual bits. */
#define          MC_CMD_POLL_BIST_MEM_REG 0x5
/* enum: ECC error detected. */
#define          MC_CMD_POLL_BIST_MEM_ECC 0x6
/* Failure address, only valid if result is POLL_BIST_FAILED */
#define       MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
#define       MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
/* Bus or address space to which the failure address corresponds */
#define       MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
#define       MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
/* enum: MC MIPS bus. */
#define          MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
/* enum: CSR IREG bus. */
#define          MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
/* enum: RX0 DPCPU bus. */
#define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
/* enum: TX0 DPCPU bus. */
#define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
/* enum: TX1 DPCPU bus. */
#define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
/* enum: RX0 DICPU bus. */
#define          MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
/* enum: TX DICPU bus. */
#define          MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
/* enum: RX1 DPCPU bus. */
#define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
/* enum: RX1 DICPU bus. */
#define          MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
/* Pattern written to RAM / register */
#define       MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
#define       MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
/* Actual value read from RAM / register */
#define       MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
#define       MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
/* ECC error mask */
#define       MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
#define       MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
/* ECC parity error mask */
#define       MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
#define       MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
/* ECC fatal error mask */
#define       MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
#define       MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4


/***********************************/
/* MC_CMD_FLUSH_RX_QUEUES
 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ
 * flushes should be initiated via this MCDI operation, rather than via
 * directly writing FLUSH_CMD.
 *
 * The flush is completed (either done/fail) asynchronously (after this command
 * returns). The driver must still wait for flush done/failure events as usual.
 */
#define MC_CMD_FLUSH_RX_QUEUES 0x27

/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
#define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
#define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
#define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX_MCDI2 1020
#define    MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
#define    MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
#define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
#define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
#define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
#define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
#define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM_MCDI2 255

/* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
#define    MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0


/***********************************/
/* MC_CMD_GET_LOOPBACK_MODES
 * Returns a bitmask of loopback modes available at each speed.
 */
#define MC_CMD_GET_LOOPBACK_MODES 0x28
#undef MC_CMD_0x28_PRIVILEGE_CTG

#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
#define    MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0

/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
#define    MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LBN 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_WIDTH 32
/* enum: None. */
#define          MC_CMD_LOOPBACK_NONE 0x0
/* enum: Data. */
#define          MC_CMD_LOOPBACK_DATA 0x1
/* enum: GMAC. */
#define          MC_CMD_LOOPBACK_GMAC 0x2
/* enum: XGMII. */
#define          MC_CMD_LOOPBACK_XGMII 0x3
/* enum: XGXS. */
#define          MC_CMD_LOOPBACK_XGXS 0x4
/* enum: XAUI. */
#define          MC_CMD_LOOPBACK_XAUI 0x5
/* enum: GMII. */
#define          MC_CMD_LOOPBACK_GMII 0x6
/* enum: SGMII. */
#define          MC_CMD_LOOPBACK_SGMII 0x7
/* enum: XGBR. */
#define          MC_CMD_LOOPBACK_XGBR 0x8
/* enum: XFI. */
#define          MC_CMD_LOOPBACK_XFI 0x9
/* enum: XAUI Far. */
#define          MC_CMD_LOOPBACK_XAUI_FAR 0xa
/* enum: GMII Far. */
#define          MC_CMD_LOOPBACK_GMII_FAR 0xb
/* enum: SGMII Far. */
#define          MC_CMD_LOOPBACK_SGMII_FAR 0xc
/* enum: XFI Far. */
#define          MC_CMD_LOOPBACK_XFI_FAR 0xd
/* enum: GPhy. */
#define          MC_CMD_LOOPBACK_GPHY 0xe
/* enum: PhyXS. */
#define          MC_CMD_LOOPBACK_PHYXS 0xf
/* enum: PCS. */
#define          MC_CMD_LOOPBACK_PCS 0x10
/* enum: PMA-PMD. */
#define          MC_CMD_LOOPBACK_PMAPMD 0x11
/* enum: Cross-Port. */
#define          MC_CMD_LOOPBACK_XPORT 0x12
/* enum: XGMII-Wireside. */
#define          MC_CMD_LOOPBACK_XGMII_WS 0x13
/* enum: XAUI Wireside. */
#define          MC_CMD_LOOPBACK_XAUI_WS 0x14
/* enum: XAUI Wireside Far. */
#define          MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
/* enum: XAUI Wireside near. */
#define          MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
/* enum: GMII Wireside. */
#define          MC_CMD_LOOPBACK_GMII_WS 0x17
/* enum: XFI Wireside. */
#define          MC_CMD_LOOPBACK_XFI_WS 0x18
/* enum: XFI Wireside Far. */
#define          MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
/* enum: PhyXS Wireside. */
#define          MC_CMD_LOOPBACK_PHYXS_WS 0x1a
/* enum: PMA lanes MAC-Serdes. */
#define          MC_CMD_LOOPBACK_PMA_INT 0x1b
/* enum: KR Serdes Parallel (Encoder). */
#define          MC_CMD_LOOPBACK_SD_NEAR 0x1c
/* enum: KR Serdes Serial. */
#define          MC_CMD_LOOPBACK_SD_FAR 0x1d
/* enum: PMA lanes MAC-Serdes Wireside. */
#define          MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
/* enum: KR Serdes Parallel Wireside (Full PCS). */
#define          MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
#define          MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
#define          MC_CMD_LOOPBACK_SD_FEP_WS 0x21
/* enum: KR Serdes Serial Wireside. */
#define          MC_CMD_LOOPBACK_SD_FES_WS 0x22
/* enum: Near side of AOE Siena side port */
#define          MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
/* enum: Medford Wireside datapath loopback */
#define          MC_CMD_LOOPBACK_DATA_WS 0x24
/* enum: Force link up without setting up any physical loopback (snapper use
 * only)
 */
#define          MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LBN 64
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LBN 96
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LBN 128
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LBN 160
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LBN 192
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LBN 224
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LBN 256
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LBN 288
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */

/* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for
 * newer NICs with 25G/50G/100G support
 */
#define    MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LBN 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_WIDTH 32
/* enum: None. */
/*               MC_CMD_LOOPBACK_NONE 0x0 */
/* enum: Data. */
/*               MC_CMD_LOOPBACK_DATA 0x1 */
/* enum: GMAC. */
/*               MC_CMD_LOOPBACK_GMAC 0x2 */
/* enum: XGMII. */
/*               MC_CMD_LOOPBACK_XGMII 0x3 */
/* enum: XGXS. */
/*               MC_CMD_LOOPBACK_XGXS 0x4 */
/* enum: XAUI. */
/*               MC_CMD_LOOPBACK_XAUI 0x5 */
/* enum: GMII. */
/*               MC_CMD_LOOPBACK_GMII 0x6 */
/* enum: SGMII. */
/*               MC_CMD_LOOPBACK_SGMII 0x7 */
/* enum: XGBR. */
/*               MC_CMD_LOOPBACK_XGBR 0x8 */
/* enum: XFI. */
/*               MC_CMD_LOOPBACK_XFI 0x9 */
/* enum: XAUI Far. */
/*               MC_CMD_LOOPBACK_XAUI_FAR 0xa */
/* enum: GMII Far. */
/*               MC_CMD_LOOPBACK_GMII_FAR 0xb */
/* enum: SGMII Far. */
/*               MC_CMD_LOOPBACK_SGMII_FAR 0xc */
/* enum: XFI Far. */
/*               MC_CMD_LOOPBACK_XFI_FAR 0xd */
/* enum: GPhy. */
/*               MC_CMD_LOOPBACK_GPHY 0xe */
/* enum: PhyXS. */
/*               MC_CMD_LOOPBACK_PHYXS 0xf */
/* enum: PCS. */
/*               MC_CMD_LOOPBACK_PCS 0x10 */
/* enum: PMA-PMD. */
/*               MC_CMD_LOOPBACK_PMAPMD 0x11 */
/* enum: Cross-Port. */
/*               MC_CMD_LOOPBACK_XPORT 0x12 */
/* enum: XGMII-Wireside. */
/*               MC_CMD_LOOPBACK_XGMII_WS 0x13 */
/* enum: XAUI Wireside. */
/*               MC_CMD_LOOPBACK_XAUI_WS 0x14 */
/* enum: XAUI Wireside Far. */
/*               MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
/* enum: XAUI Wireside near. */
/*               MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
/* enum: GMII Wireside. */
/*               MC_CMD_LOOPBACK_GMII_WS 0x17 */
/* enum: XFI Wireside. */
/*               MC_CMD_LOOPBACK_XFI_WS 0x18 */
/* enum: XFI Wireside Far. */
/*               MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
/* enum: PhyXS Wireside. */
/*               MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
/* enum: PMA lanes MAC-Serdes. */
/*               MC_CMD_LOOPBACK_PMA_INT 0x1b */
/* enum: KR Serdes Parallel (Encoder). */
/*               MC_CMD_LOOPBACK_SD_NEAR 0x1c */
/* enum: KR Serdes Serial. */
/*               MC_CMD_LOOPBACK_SD_FAR 0x1d */
/* enum: PMA lanes MAC-Serdes Wireside. */
/*               MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
/* enum: KR Serdes Parallel Wireside (Full PCS). */
/*               MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
/*               MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
/*               MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
/* enum: KR Serdes Serial Wireside. */
/*               MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
/* enum: Near side of AOE Siena side port */
/*               MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
/* enum: Medford Wireside datapath loopback */
/*               MC_CMD_LOOPBACK_DATA_WS 0x24 */
/* enum: Force link up without setting up any physical loopback (snapper use
 * only)
 */
/*               MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LBN 64
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LBN 96
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LBN 128
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LBN 160
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LBN 192
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LBN 224
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */
/* Supported loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LBN 256
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LBN 288
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */
/* Supported 25G loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LBN 320
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LBN 352
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */
/* Supported 50 loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LBN 384
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LBN 416
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */
/* Supported 100G loopbacks. */
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LBN 448
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_WIDTH 32
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LBN 480
#define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_WIDTH 32
/*            Enum values, see field(s): */
/*               100M */

/* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
#define    AN_TYPE_LEN 4
#define       AN_TYPE_TYPE_OFST 0
#define       AN_TYPE_TYPE_LEN 4
/* enum: None, AN disabled or not supported */
#define          MC_CMD_AN_NONE 0x0
/* enum: Clause 28 - BASE-T */
#define          MC_CMD_AN_CLAUSE28 0x1
/* enum: Clause 37 - BASE-X */
#define          MC_CMD_AN_CLAUSE37 0x2
/* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
 * assemblies. Includes Clause 72/Clause 92 link-training.
 */
#define          MC_CMD_AN_CLAUSE73 0x3
#define       AN_TYPE_TYPE_LBN 0
#define       AN_TYPE_TYPE_WIDTH 32

/* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3
 */
#define    FEC_TYPE_LEN 4
#define       FEC_TYPE_TYPE_OFST 0
#define       FEC_TYPE_TYPE_LEN 4
/* enum: No FEC */
#define          MC_CMD_FEC_NONE 0x0
/* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
#define          MC_CMD_FEC_BASER 0x1
/* enum: Clause 91/Clause 108 Reed-Solomon FEC */
#define          MC_CMD_FEC_RS 0x2
#define       FEC_TYPE_TYPE_LBN 0
#define       FEC_TYPE_TYPE_WIDTH 32


/***********************************/
/* MC_CMD_GET_LINK
 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
 * ETIME.
 */
#define MC_CMD_GET_LINK 0x29
#undef MC_CMD_0x29_PRIVILEGE_CTG

#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_GET_LINK_IN msgrequest */
#define    MC_CMD_GET_LINK_IN_LEN 0

/* MC_CMD_GET_LINK_OUT msgresponse */
#define    MC_CMD_GET_LINK_OUT_LEN 28
/* Near-side advertised capabilities. Refer to
 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
 */
#define       MC_CMD_GET_LINK_OUT_CAP_OFST 0
#define       MC_CMD_GET_LINK_OUT_CAP_LEN 4
/* Link-partner advertised capabilities. Refer to
 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
 */
#define       MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
#define       MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
/* Autonegotiated speed in mbit/s. The link may still be down even if this
 * reads non-zero.
 */
#define       MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
#define       MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
/* Current loopback setting. */
#define       MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
#define       MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
#define       MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
#define       MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
#define        MC_CMD_GET_LINK_OUT_LINK_UP_OFST 16
#define        MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
#define        MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_OFST 16
#define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
#define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_BPX_LINK_OFST 16
#define        MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
#define        MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_PHY_LINK_OFST 16
#define        MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
#define        MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_OFST 16
#define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
#define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_OFST 16
#define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
#define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_OFST 16
#define        MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_LBN 8
#define        MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_MODULE_UP_OFST 16
#define        MC_CMD_GET_LINK_OUT_MODULE_UP_LBN 9
#define        MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 1
/* This returns the negotiated flow control value. */
#define       MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
#define       MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
#define       MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
#define       MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
#define        MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24
#define        MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
#define        MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
#define        MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24
#define        MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
#define        MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
#define        MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24
#define        MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
#define        MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
#define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24
#define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
#define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1

/* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */
#define    MC_CMD_GET_LINK_OUT_V2_LEN 44
/* Near-side advertised capabilities. Refer to
 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
 */
#define       MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
#define       MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
/* Link-partner advertised capabilities. Refer to
 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
 */
#define       MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
#define       MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
/* Autonegotiated speed in mbit/s. The link may still be down even if this
 * reads non-zero.
 */
#define       MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8
#define       MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
/* Current loopback setting. */
#define       MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12
#define       MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
#define       MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16
#define       MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
#define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_OFST 16
#define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
#define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_OFST 16
#define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
#define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_OFST 16
#define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2
#define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_OFST 16
#define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3
#define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_OFST 16
#define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6
#define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_OFST 16
#define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7
#define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_OFST 16
#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_LBN 8
#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_OFST 16
#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_LBN 9
#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 1
/* This returns the negotiated flow control value. */
#define       MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
#define       MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
#define       MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
#define       MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
/*             MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 */
/*             MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
/*             MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
/*             MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 */
/*             MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
/*             MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
/*             MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 */
/*             MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */
/*             MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
/*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 */
/*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */
/*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
/* True local device capabilities (taking into account currently used PMD/MDI,
 * e.g. plugged-in module). In general, subset of
 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST
 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
 */
#define       MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28
#define       MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
/* Auto-negotiation type used on the link */
#define       MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32
#define       MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               AN_TYPE/TYPE */
/* Forward error correction used on the link */
#define       MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36
#define       MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               FEC_TYPE/TYPE */
#define       MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40
#define       MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
#define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
#define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
#define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2
#define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3
#define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
#define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5
#define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_HI_BER_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6
#define        MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7
#define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8
#define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
#define        MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_OFST 40
#define        MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_LBN 9
#define        MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 1


/***********************************/
/* MC_CMD_SET_LINK
 * Write the unified MAC/PHY link configuration. Locks required: None. Return
 * code: 0, EINVAL, ETIME, EAGAIN
 */
#define MC_CMD_SET_LINK 0x2a
#undef MC_CMD_0x2a_PRIVILEGE_CTG

#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK

/* MC_CMD_SET_LINK_IN msgrequest */
#define    MC_CMD_SET_LINK_IN_LEN 16
/* Near-side advertised capabilities. Refer to
 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
 */
#define       MC_CMD_SET_LINK_IN_CAP_OFST 0
#define       MC_CMD_SET_LINK_IN_CAP_LEN 4
/* Flags */
#define       MC_CMD_SET_LINK_IN_FLAGS_OFST 4
#define       MC_CMD_SET_LINK_IN_FLAGS_LEN 4
#define        MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
#define        MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
#define        MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
#define        MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
#define        MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
#define        MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
#define        MC_CMD_SET_LINK_IN_TXDIS_OFST 4
#define        MC_CMD_SET_LINK_IN_TXDIS_LBN 2
#define        MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
#define        MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
#define        MC_CMD_SET_LINK_IN_LINKDOWN_LBN 3
#define        MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 1
/* Loopback mode. */
#define       MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
#define       MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
/* A loopback speed of "0" is supported, and means (choose any available
 * speed).
 */
#define       MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
#define       MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4

/* MC_CMD_SET_LINK_IN_V2 msgrequest: Updated SET_LINK to include sequence
 * number to ensure this SET_LINK command corresponds to the latest
 * MODULECHANGE event.
 */
#define    MC_CMD_SET_LINK_IN_V2_LEN 17
/* Near-side advertised capabilities. Refer to
 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
 */
#define       MC_CMD_SET_LINK_IN_V2_CAP_OFST 0
#define       MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
/* Flags */
#define       MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
#define       MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
#define        MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
#define        MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0
#define        MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 1
#define        MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
#define        MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 1
#define        MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 1
#define        MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
#define        MC_CMD_SET_LINK_IN_V2_TXDIS_LBN 2
#define        MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 1
#define        MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
#define        MC_CMD_SET_LINK_IN_V2_LINKDOWN_LBN 3
#define        MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 1
/* Loopback mode. */
#define       MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_OFST 8
#define       MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
/* A loopback speed of "0" is supported, and means (choose any available
 * speed).
 */
#define       MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_OFST 12
#define       MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
#define       MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_OFST 16
#define       MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 1
#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_OFST 16
#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0
#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_WIDTH 7
#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_OFST 16
#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 7
#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1

/* MC_CMD_SET_LINK_OUT msgresponse */
#define    MC_CMD_SET_LINK_OUT_LEN 0


/***********************************/
/* MC_CMD_SET_ID_LED
 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
 */
#define MC_CMD_SET_ID_LED 0x2b
#undef MC_CMD_0x2b_PRIVILEGE_CTG

#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK

/* MC_CMD_SET_ID_LED_IN msgrequest */
#define    MC_CMD_SET_ID_LED_IN_LEN 4
/* Set LED state. */
#define       MC_CMD_SET_ID_LED_IN_STATE_OFST 0
#define       MC_CMD_SET_ID_LED_IN_STATE_LEN 4
#define          MC_CMD_LED_OFF 0x0 /* enum */
#define          MC_CMD_LED_ON 0x1 /* enum */
#define          MC_CMD_LED_DEFAULT 0x2 /* enum */

/* MC_CMD_SET_ID_LED_OUT msgresponse */
#define    MC_CMD_SET_ID_LED_OUT_LEN 0


/***********************************/
/* MC_CMD_SET_MAC
 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
 */
#define MC_CMD_SET_MAC 0x2c
#undef MC_CMD_0x2c_PRIVILEGE_CTG

#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_SET_MAC_IN msgrequest */
#define    MC_CMD_SET_MAC_IN_LEN 28
/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
 * EtherII, VLAN, bug16011 padding).
 */
#define       MC_CMD_SET_MAC_IN_MTU_OFST 0
#define       MC_CMD_SET_MAC_IN_MTU_LEN 4
#define       MC_CMD_SET_MAC_IN_DRAIN_OFST 4
#define       MC_CMD_SET_MAC_IN_DRAIN_LEN 4
#define       MC_CMD_SET_MAC_IN_ADDR_OFST 8
#define       MC_CMD_SET_MAC_IN_ADDR_LEN 8
#define       MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
#define       MC_CMD_SET_MAC_IN_ADDR_LO_LEN 4
#define       MC_CMD_SET_MAC_IN_ADDR_LO_LBN 64
#define       MC_CMD_SET_MAC_IN_ADDR_LO_WIDTH 32
#define       MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
#define       MC_CMD_SET_MAC_IN_ADDR_HI_LEN 4
#define       MC_CMD_SET_MAC_IN_ADDR_HI_LBN 96
#define       MC_CMD_SET_MAC_IN_ADDR_HI_WIDTH 32
#define       MC_CMD_SET_MAC_IN_REJECT_OFST 16
#define       MC_CMD_SET_MAC_IN_REJECT_LEN 4
#define        MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16
#define        MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
#define        MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
#define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_OFST 16
#define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
#define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
#define       MC_CMD_SET_MAC_IN_FCNTL_OFST 20
#define       MC_CMD_SET_MAC_IN_FCNTL_LEN 4
/* enum: Flow control is off. */
#define          MC_CMD_FCNTL_OFF 0x0
/* enum: Respond to flow control. */
#define          MC_CMD_FCNTL_RESPOND 0x1
/* enum: Respond to and Issue flow control. */
#define          MC_CMD_FCNTL_BIDIR 0x2
/* enum: Auto neg flow control. */
#define          MC_CMD_FCNTL_AUTO 0x3
/* enum: Priority flow control (eftest builds only). */
#define          MC_CMD_FCNTL_QBB 0x4
/* enum: Issue flow control. */
#define          MC_CMD_FCNTL_GENERATE 0x5
#define       MC_CMD_SET_MAC_IN_FLAGS_OFST 24
#define       MC_CMD_SET_MAC_IN_FLAGS_LEN 4
#define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24
#define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
#define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1

/* MC_CMD_SET_MAC_EXT_IN msgrequest */
#define    MC_CMD_SET_MAC_EXT_IN_LEN 32
/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
 * EtherII, VLAN, bug16011 padding).
 */
#define       MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
#define       MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
#define       MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
#define       MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LBN 64
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_LO_WIDTH 32
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LBN 96
#define       MC_CMD_SET_MAC_EXT_IN_ADDR_HI_WIDTH 32
#define       MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
#define       MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
#define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16
#define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
#define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
#define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_OFST 16
#define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
#define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
#define       MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
#define       MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
/* enum: Flow control is off. */
/*               MC_CMD_FCNTL_OFF 0x0 */
/* enum: Respond to flow control. */
/*               MC_CMD_FCNTL_RESPOND 0x1 */
/* enum: Respond to and Issue flow control. */
/*               MC_CMD_FCNTL_BIDIR 0x2 */
/* enum: Auto neg flow control. */
/*               MC_CMD_FCNTL_AUTO 0x3 */
/* enum: Priority flow control (eftest builds only). */
/*               MC_CMD_FCNTL_QBB 0x4 */
/* enum: Issue flow control. */
/*               MC_CMD_FCNTL_GENERATE 0x5 */
#define       MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
#define       MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
#define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_OFST 24
#define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
#define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
/* Select which parameters to configure. A parameter will only be modified if
 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
 * capabilities then this field is ignored (and all flags are assumed to be
 * set).
 */
#define       MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
#define       MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
#define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_OFST 28
#define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
#define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
#define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_OFST 28
#define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
#define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
#define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_OFST 28
#define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
#define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
#define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_OFST 28
#define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
#define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
#define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_OFST 28
#define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
#define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1

/* MC_CMD_SET_MAC_V3_IN msgrequest */
#define    MC_CMD_SET_MAC_V3_IN_LEN 40
/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
 * EtherII, VLAN, bug16011 padding).
 */
#define       MC_CMD_SET_MAC_V3_IN_MTU_OFST 0
#define       MC_CMD_SET_MAC_V3_IN_MTU_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4
#define       MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_ADDR_OFST 8
#define       MC_CMD_SET_MAC_V3_IN_ADDR_LEN 8
#define       MC_CMD_SET_MAC_V3_IN_ADDR_LO_OFST 8
#define       MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_ADDR_LO_LBN 64
#define       MC_CMD_SET_MAC_V3_IN_ADDR_LO_WIDTH 32
#define       MC_CMD_SET_MAC_V3_IN_ADDR_HI_OFST 12
#define       MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_ADDR_HI_LBN 96
#define       MC_CMD_SET_MAC_V3_IN_ADDR_HI_WIDTH 32
#define       MC_CMD_SET_MAC_V3_IN_REJECT_OFST 16
#define       MC_CMD_SET_MAC_V3_IN_REJECT_LEN 4
#define        MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_OFST 16
#define        MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0
#define        MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_WIDTH 1
#define        MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_OFST 16
#define        MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_LBN 1
#define        MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_WIDTH 1
#define       MC_CMD_SET_MAC_V3_IN_FCNTL_OFST 20
#define       MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4
/* enum: Flow control is off. */
/*               MC_CMD_FCNTL_OFF 0x0 */
/* enum: Respond to flow control. */
/*               MC_CMD_FCNTL_RESPOND 0x1 */
/* enum: Respond to and Issue flow control. */
/*               MC_CMD_FCNTL_BIDIR 0x2 */
/* enum: Auto neg flow control. */
/*               MC_CMD_FCNTL_AUTO 0x3 */
/* enum: Priority flow control (eftest builds only). */
/*               MC_CMD_FCNTL_QBB 0x4 */
/* enum: Issue flow control. */
/*               MC_CMD_FCNTL_GENERATE 0x5 */
#define       MC_CMD_SET_MAC_V3_IN_FLAGS_OFST 24
#define       MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4
#define        MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_OFST 24
#define        MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0
#define        MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_WIDTH 1
/* Select which parameters to configure. A parameter will only be modified if
 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
 * capabilities then this field is ignored (and all flags are assumed to be
 * set).
 */
#define       MC_CMD_SET_MAC_V3_IN_CONTROL_OFST 28
#define       MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4
#define        MC_CMD_SET_MAC_V3_IN_CFG_MTU_OFST 28
#define        MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0
#define        MC_CMD_SET_MAC_V3_IN_CFG_MTU_WIDTH 1
#define        MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_OFST 28
#define        MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_LBN 1
#define        MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_WIDTH 1
#define        MC_CMD_SET_MAC_V3_IN_CFG_REJECT_OFST 28
#define        MC_CMD_SET_MAC_V3_IN_CFG_REJECT_LBN 2
#define        MC_CMD_SET_MAC_V3_IN_CFG_REJECT_WIDTH 1
#define        MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_OFST 28
#define        MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_LBN 3
#define        MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_WIDTH 1
#define        MC_CMD_SET_MAC_V3_IN_CFG_FCS_OFST 28
#define        MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4
#define        MC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 1
/* Identifies the MAC to update by the specifying the end of a logical MAE
 * link. Setting TARGET to MAE_LINK_ENDPOINT_COMPAT is equivalent to using the
 * previous version of the command (MC_CMD_SET_MAC_EXT). Not all possible
 * combinations of MPORT_END and MPORT_SELECTOR in TARGET will work in all
 * circumstances. 1. Some will always work (e.g. a VF can always address its
 * logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC), 2. Some are not
 * meaningful and will always fail with EINVAL (e.g. attempting to address the
 * VNIC end of a link to a physical port), 3. Some are meaningful but require
 * the MCDI client to have the required permission and fail with EPERM
 * otherwise (e.g. trying to set the MAC on a VF the caller cannot administer),
 * and 4. Some could be implementation-specific and fail with ENOTSUP if not
 * available (no examples exist right now). See SF-123581-TC section 4.3 for
 * more details.
 */
#define       MC_CMD_SET_MAC_V3_IN_TARGET_OFST 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_LEN 8
#define       MC_CMD_SET_MAC_V3_IN_TARGET_LO_OFST 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_LO_LBN 256
#define       MC_CMD_SET_MAC_V3_IN_TARGET_LO_WIDTH 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_HI_OFST 36
#define       MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_HI_LBN 288
#define       MC_CMD_SET_MAC_V3_IN_TARGET_HI_WIDTH 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_OFST 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 35
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 256
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 276
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 272
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 34
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
#define       MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_OFST 36
#define       MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_OFST 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LEN 8
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_OFST 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LBN 256
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_WIDTH 32
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_OFST 36
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LBN 288
#define       MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_WIDTH 32

/* MC_CMD_SET_MAC_OUT msgresponse */
#define    MC_CMD_SET_MAC_OUT_LEN 0

/* MC_CMD_SET_MAC_V2_OUT msgresponse */
#define    MC_CMD_SET_MAC_V2_OUT_LEN 4
/* MTU as configured after processing the request. See comment at
 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL
 * to 0.
 */
#define       MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
#define       MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4


/***********************************/
/* MC_CMD_PHY_STATS
 * Get generic PHY statistics. This call returns the statistics for a generic
 * PHY in a sparse array (indexed by the enumerate). Each value is represented
 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
 * statistics may be read from the message response. If DMA_ADDR != 0, then the
 * statistics are dmad to that (page-aligned location). Locks required: None.
 * Returns: 0, ETIME
 */
#define MC_CMD_PHY_STATS 0x2d
#undef MC_CMD_0x2d_PRIVILEGE_CTG

#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK

/* MC_CMD_PHY_STATS_IN msgrequest */
#define    MC_CMD_PHY_STATS_IN_LEN 8
/* ??? */
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_WIDTH 32
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LBN 32
#define       MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_WIDTH 32

/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
#define    MC_CMD_PHY_STATS_OUT_DMA_LEN 0

/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
#define    MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
#define       MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
#define       MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
#define       MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
/* enum: OUI. */
#define          MC_CMD_OUI 0x0
/* enum: PMA-PMD Link Up. */
#define          MC_CMD_PMA_PMD_LINK_UP 0x1
/* enum: PMA-PMD RX Fault. */
#define          MC_CMD_PMA_PMD_RX_FAULT 0x2
/* enum: PMA-PMD TX Fault. */
#define          MC_CMD_PMA_PMD_TX_FAULT 0x3
/* enum: PMA-PMD Signal */
#define          MC_CMD_PMA_PMD_SIGNAL 0x4
/* enum: PMA-PMD SNR A. */
#define          MC_CMD_PMA_PMD_SNR_A 0x5
/* enum: PMA-PMD SNR B. */
#define          MC_CMD_PMA_PMD_SNR_B 0x6
/* enum: PMA-PMD SNR C. */
#define          MC_CMD_PMA_PMD_SNR_C 0x7
/* enum: PMA-PMD SNR D. */
#define          MC_CMD_PMA_PMD_SNR_D 0x8
/* enum: PCS Link Up. */
#define          MC_CMD_PCS_LINK_UP 0x9
/* enum: PCS RX Fault. */
#define          MC_CMD_PCS_RX_FAULT 0xa
/* enum: PCS TX Fault. */
#define          MC_CMD_PCS_TX_FAULT 0xb
/* enum: PCS BER. */
#define          MC_CMD_PCS_BER 0xc
/* enum: PCS Block Errors. */
#define          MC_CMD_PCS_BLOCK_ERRORS 0xd
/* enum: PhyXS Link Up. */
#define          MC_CMD_PHYXS_LINK_UP 0xe
/* enum: PhyXS RX Fault. */
#define          MC_CMD_PHYXS_RX_FAULT 0xf
/* enum: PhyXS TX Fault. */
#define          MC_CMD_PHYXS_TX_FAULT 0x10
/* enum: PhyXS Align. */
#define          MC_CMD_PHYXS_ALIGN 0x11
/* enum: PhyXS Sync. */
#define          MC_CMD_PHYXS_SYNC 0x12
/* enum: AN link-up. */
#define          MC_CMD_AN_LINK_UP 0x13
/* enum: AN Complete. */
#define          MC_CMD_AN_COMPLETE 0x14
/* enum: AN 10GBaseT Status. */
#define          MC_CMD_AN_10GBT_STATUS 0x15
/* enum: Clause 22 Link-Up. */
#define          MC_CMD_CL22_LINK_UP 0x16
/* enum: (Last entry) */
#define          MC_CMD_PHY_NSTATS 0x17


/***********************************/
/* MC_CMD_MAC_STATS
 * Get generic MAC statistics. This call returns unified statistics maintained
 * by the MC as it switches between the GMAC and XMAC. The MC will write out
 * all supported stats. The driver should zero initialise the buffer to
 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
 * performed, and the statistics may be read from the message response. If
 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no
 * effect. Returns: 0, ETIME
 */
#define MC_CMD_MAC_STATS 0x2e
#undef MC_CMD_0x2e_PRIVILEGE_CTG

#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_MAC_STATS_IN msgrequest */
#define    MC_CMD_MAC_STATS_IN_LEN 20
/* ??? */
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_WIDTH 32
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LBN 32
#define       MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_WIDTH 32
#define       MC_CMD_MAC_STATS_IN_CMD_OFST 8
#define       MC_CMD_MAC_STATS_IN_CMD_LEN 4
#define        MC_CMD_MAC_STATS_IN_DMA_OFST 8
#define        MC_CMD_MAC_STATS_IN_DMA_LBN 0
#define        MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
#define        MC_CMD_MAC_STATS_IN_CLEAR_OFST 8
#define        MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
#define        MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
#define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_OFST 8
#define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
#define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
#define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_OFST 8
#define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
#define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
#define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_OFST 8
#define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
#define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
#define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_OFST 8
#define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
#define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
#define        MC_CMD_MAC_STATS_IN_PERIOD_MS_OFST 8
#define        MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
#define        MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
/* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as
 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not
 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to
 * MC_CMD_MAC_NSTATS * sizeof(uint64_t)
 */
#define       MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
#define       MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
/* port id so vadapter stats can be provided */
#define       MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16
#define       MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4

/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
#define    MC_CMD_MAC_STATS_OUT_DMA_LEN 0

/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
#define    MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LBN 32
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
#define          MC_CMD_MAC_GENERATION_START 0x0 /* enum */
#define          MC_CMD_MAC_DMABUF_START 0x1 /* enum */
#define          MC_CMD_MAC_TX_PKTS 0x1 /* enum */
#define          MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
#define          MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
#define          MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
#define          MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
#define          MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
#define          MC_CMD_MAC_TX_BYTES 0x7 /* enum */
#define          MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
#define          MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
#define          MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
#define          MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
#define          MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
#define          MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
#define          MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
#define          MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
#define          MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
#define          MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
#define          MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
#define          MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
#define          MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
#define          MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
#define          MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
#define          MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
#define          MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
#define          MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
#define          MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
#define          MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
#define          MC_CMD_MAC_RX_PKTS 0x1c /* enum */
#define          MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
#define          MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
#define          MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
#define          MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
#define          MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
#define          MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
#define          MC_CMD_MAC_RX_BYTES 0x23 /* enum */
#define          MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
#define          MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
#define          MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
#define          MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
#define          MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
#define          MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
#define          MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
#define          MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
#define          MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
#define          MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
#define          MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
#define          MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
#define          MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
#define          MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
#define          MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
#define          MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
#define          MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
#define          MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
#define          MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
#define          MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
#define          MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
#define          MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
#define          MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
#define          MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
 * capability only.
 */
#define          MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
/* enum: PM discard_bb_overflow counter. Valid for EF10 with
 * PM_AND_RXDP_COUNTERS capability only.
 */
#define          MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
 * capability only.
 */
#define          MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
/* enum: PM discard_vfifo_full counter. Valid for EF10 with
 * PM_AND_RXDP_COUNTERS capability only.
 */
#define          MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
 * capability only.
 */
#define          MC_CMD_MAC_PM_TRUNC_QBB 0x40
/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
 * capability only.
 */
#define          MC_CMD_MAC_PM_DISCARD_QBB 0x41
/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
 * capability only.
 */
#define          MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
/* enum: RXDP counter: Number of packets dropped due to the queue being
 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
 */
#define          MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
 * with PM_AND_RXDP_COUNTERS capability only.
 */
#define          MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
 * PM_AND_RXDP_COUNTERS capability only.
 */
#define          MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
 */
#define          MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
/* enum: RXDP counter: Number of times the DPCPU waited for an existing
 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
 */
#define          MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
#define          MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
#define          MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
#define          MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
#define          MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
#define          MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
#define          MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
#define          MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
#define          MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
#define          MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
#define          MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
#define          MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
/* enum: Start of GMAC stats buffer space, for Siena only. */
#define          MC_CMD_GMAC_DMABUF_START 0x40
/* enum: End of GMAC stats buffer space, for Siena only. */
#define          MC_CMD_GMAC_DMABUF_END 0x5f
/* enum: GENERATION_END value, used together with GENERATION_START to verify
 * consistency of DMAd data. For legacy firmware / drivers without extended
 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *
 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,
 * this value is invalid/ reserved and GENERATION_END is written as the last
 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
 * this is consistent with the legacy behaviour, in the sense that entry 96 is
 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
 */
#define          MC_CMD_MAC_GENERATION_END 0x60
#define          MC_CMD_MAC_NSTATS 0x61 /* enum */

/* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */
#define    MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0

/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */
#define    MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LBN 32
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
/* enum: Start of FEC stats buffer space, Medford2 and up */
#define          MC_CMD_MAC_FEC_DMABUF_START 0x61
/* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
 */
#define          MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
/* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
 */
#define          MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
#define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
#define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
#define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
#define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
/* enum: This includes the space at offset 103 which is the final
 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.
 */
#define          MC_CMD_MAC_NSTATS_V2 0x68
/*            Other enum values, see field(s): */
/*               MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */

/* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */
#define    MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0

/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */
#define    MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3)
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LBN 32
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
/* enum: Start of CTPIO stats buffer space, Medford2 and up */
#define          MC_CMD_MAC_CTPIO_DMABUF_START 0x68
/* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the
 * target VI
 */
#define          MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
/* enum: Number of times a CTPIO send wrote beyond frame end (informational
 * only)
 */
#define          MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
/* enum: Number of CTPIO failures because the TX doorbell was written before
 * the end of the frame data
 */
#define          MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
/* enum: Number of CTPIO failures because the internal FIFO overflowed */
#define          MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
/* enum: Number of CTPIO failures because the host did not deliver data fast
 * enough to avoid MAC underflow
 */
#define          MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
/* enum: Number of CTPIO failures because the host did not deliver all the
 * frame data within the timeout
 */
#define          MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
/* enum: Number of CTPIO failures because the frame data arrived out of order
 * or with gaps
 */
#define          MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
/* enum: Number of CTPIO failures because the host started a new frame before
 * completing the previous one
 */
#define          MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
/* enum: Number of CTPIO failures because a write was not a multiple of 32 bits
 * or not 32-bit aligned
 */
#define          MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
/* enum: Number of CTPIO fallbacks because another VI on the same port was
 * sending a CTPIO frame
 */
#define          MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
/* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
 */
#define          MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
/* enum: Number of CTPIO fallbacks because length in header was less than 29
 * bytes
 */
#define          MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
/* enum: Total number of successful CTPIO sends on this port */
#define          MC_CMD_MAC_CTPIO_SUCCESS 0x74
/* enum: Total number of CTPIO fallbacks on this port */
#define          MC_CMD_MAC_CTPIO_FALLBACK 0x75
/* enum: Total number of CTPIO poisoned frames on this port, whether erased or
 * not
 */
#define          MC_CMD_MAC_CTPIO_POISON 0x76
/* enum: Total number of CTPIO erased frames on this port */
#define          MC_CMD_MAC_CTPIO_ERASE 0x77
/* enum: This includes the space at offset 120 which is the final
 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.
 */
#define          MC_CMD_MAC_NSTATS_V3 0x79
/*            Other enum values, see field(s): */
/*               MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */

/* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */
#define    MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0

/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */
#define    MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3)
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LBN 32
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4
/* enum: Start of V4 stats buffer space */
#define          MC_CMD_MAC_V4_DMABUF_START 0x79
/* enum: RXDP counter: Number of packets truncated because scattering was
 * disabled.
 */
#define          MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
/* enum: RXDP counter: Number of times the RXDP head of line blocked waiting
 * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set.
 */
#define          MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
/* enum: RXDP counter: Number of times the RXDP timed out while head of line
 * blocking. Will be zero unless RXDP_HLB_IDLE capability is set.
 */
#define          MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
/* enum: This includes the space at offset 124 which is the final
 * GENERATION_END in a MAC_STATS_V4 response and otherwise unused.
 */
#define          MC_CMD_MAC_NSTATS_V4 0x7d
/*            Other enum values, see field(s): */
/*               MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */


/***********************************/
/* MC_CMD_SRIOV
 * to be documented
 */
#define MC_CMD_SRIOV 0x30

/* MC_CMD_SRIOV_IN msgrequest */
#define    MC_CMD_SRIOV_IN_LEN 12
#define       MC_CMD_SRIOV_IN_ENABLE_OFST 0
#define       MC_CMD_SRIOV_IN_ENABLE_LEN 4
#define       MC_CMD_SRIOV_IN_VI_BASE_OFST 4
#define       MC_CMD_SRIOV_IN_VI_BASE_LEN 4
#define       MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
#define       MC_CMD_SRIOV_IN_VF_COUNT_LEN 4

/* MC_CMD_SRIOV_OUT msgresponse */
#define    MC_CMD_SRIOV_OUT_LEN 8
#define       MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
#define       MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
#define       MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
#define       MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4

/* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
#define    MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
/* this is only used for the first record */
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 4
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LBN 64
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_WIDTH 32
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 4
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LBN 96
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_WIDTH 32
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
#define          MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 4
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LBN 160
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_WIDTH 32
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 4
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LBN 192
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_WIDTH 32
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
#define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32


/***********************************/
/* MC_CMD_MEMCPY
 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data
 * embedded directly in the command.
 *
 * A common pattern is for a client to use generation counts to signal a dma
 * update of a datastructure. To facilitate this, this MCDI operation can
 * contain multiple requests which are executed in strict order. Requests take
 * the form of duplicating the entire MCDI request continuously (including the
 * requests record, which is ignored in all but the first structure)
 *
 * The source data can either come from a DMA from the host, or it can be
 * embedded within the request directly, thereby eliminating a DMA read. To
 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
 * ADDR_LO=offset, and inserts the data at %offset from the start of the
 * payload. It's the callers responsibility to ensure that the embedded data
 * doesn't overlap the records.
 *
 * Returns: 0, EINVAL (invalid RID)
 */
#define MC_CMD_MEMCPY 0x31

/* MC_CMD_MEMCPY_IN msgrequest */
#define    MC_CMD_MEMCPY_IN_LENMIN 32
#define    MC_CMD_MEMCPY_IN_LENMAX 224
#define    MC_CMD_MEMCPY_IN_LENMAX_MCDI2 992
#define    MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
#define    MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
#define       MC_CMD_MEMCPY_IN_RECORD_OFST 0
#define       MC_CMD_MEMCPY_IN_RECORD_LEN 32
#define       MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
#define       MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
#define       MC_CMD_MEMCPY_IN_RECORD_MAXNUM_MCDI2 31

/* MC_CMD_MEMCPY_OUT msgresponse */
#define    MC_CMD_MEMCPY_OUT_LEN 0


/***********************************/
/* MC_CMD_WOL_FILTER_SET
 * Set a WoL filter.
 */
#define MC_CMD_WOL_FILTER_SET 0x32
#undef MC_CMD_0x32_PRIVILEGE_CTG

#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK

/* MC_CMD_WOL_FILTER_SET_IN msgrequest */
#define    MC_CMD_WOL_FILTER_SET_IN_LEN 192
#define       MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
#define       MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
#define          MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
#define          MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
/* A type value of 1 is unused. */
#define       MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
#define       MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
/* enum: Magic */
#define          MC_CMD_WOL_TYPE_MAGIC 0x0
/* enum: MS Windows Magic */
#define          MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
/* enum: IPv4 Syn */
#define          MC_CMD_WOL_TYPE_IPV4_SYN 0x3
/* enum: IPv6 Syn */
#define          MC_CMD_WOL_TYPE_IPV6_SYN 0x4
/* enum: Bitmap */
#define          MC_CMD_WOL_TYPE_BITMAP 0x5
/* enum: Link */
#define          MC_CMD_WOL_TYPE_LINK 0x6
/* enum: (Above this for future use) */
#define          MC_CMD_WOL_TYPE_MAX 0x7
#define       MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
#define       MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
#define       MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46

/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
#define    MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LBN 64
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_WIDTH 32
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LBN 96
#define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_WIDTH 32

/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
#define    MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
#define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
#define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
#define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
#define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
#define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
#define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
#define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
#define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2

/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
#define    MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
#define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
#define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
#define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
#define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
#define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
#define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
#define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
#define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2

/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
#define    MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
#define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1

/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
#define    MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
#define       MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
#define       MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
#define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_OFST 8
#define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
#define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
#define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_OFST 8
#define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
#define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1

/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
#define    MC_CMD_WOL_FILTER_SET_OUT_LEN 4
#define       MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
#define       MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4


/***********************************/
/* MC_CMD_WOL_FILTER_REMOVE
 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
 */
#define MC_CMD_WOL_FILTER_REMOVE 0x33
#undef MC_CMD_0x33_PRIVILEGE_CTG

#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK

/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
#define    MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
#define       MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
#define       MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4

/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
#define    MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0


/***********************************/
/* MC_CMD_WOL_FILTER_RESET
 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
 * ENOSYS
 */
#define MC_CMD_WOL_FILTER_RESET 0x34
#undef MC_CMD_0x34_PRIVILEGE_CTG

#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK

/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
#define    MC_CMD_WOL_FILTER_RESET_IN_LEN 4
#define       MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
#define       MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
#define          MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
#define          MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */

/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
#define    MC_CMD_WOL_FILTER_RESET_OUT_LEN 0


/***********************************/
/* MC_CMD_SET_MCAST_HASH
 * Set the MCAST hash value without otherwise reconfiguring the MAC
 */
#define MC_CMD_SET_MCAST_HASH 0x35

/* MC_CMD_SET_MCAST_HASH_IN msgrequest */
#define    MC_CMD_SET_MCAST_HASH_IN_LEN 32
#define       MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
#define       MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
#define       MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
#define       MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16

/* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
#define    MC_CMD_SET_MCAST_HASH_OUT_LEN 0


/***********************************/
/* MC_CMD_NVRAM_TYPES
 * Return bitfield indicating available types of virtual NVRAM partitions.
 * Locks required: none. Returns: 0
 */
#define MC_CMD_NVRAM_TYPES 0x36
#undef MC_CMD_0x36_PRIVILEGE_CTG

#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_TYPES_IN msgrequest */
#define    MC_CMD_NVRAM_TYPES_IN_LEN 0

/* MC_CMD_NVRAM_TYPES_OUT msgresponse */
#define    MC_CMD_NVRAM_TYPES_OUT_LEN 4
/* Bit mask of supported types. */
#define       MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
#define       MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
/* enum: Disabled callisto. */
#define          MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
/* enum: MC firmware. */
#define          MC_CMD_NVRAM_TYPE_MC_FW 0x1
/* enum: MC backup firmware. */
#define          MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
/* enum: Static configuration Port0. */
#define          MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
/* enum: Static configuration Port1. */
#define          MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
/* enum: Dynamic configuration Port0. */
#define          MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
/* enum: Dynamic configuration Port1. */
#define          MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
/* enum: Expansion Rom. */
#define          MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
/* enum: Expansion Rom Configuration Port0. */
#define          MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
/* enum: Expansion Rom Configuration Port1. */
#define          MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
/* enum: Phy Configuration Port0. */
#define          MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
/* enum: Phy Configuration Port1. */
#define          MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
/* enum: Log. */
#define          MC_CMD_NVRAM_TYPE_LOG 0xc
/* enum: FPGA image. */
#define          MC_CMD_NVRAM_TYPE_FPGA 0xd
/* enum: FPGA backup image */
#define          MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
/* enum: FC firmware. */
#define          MC_CMD_NVRAM_TYPE_FC_FW 0xf
/* enum: FC backup firmware. */
#define          MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
/* enum: CPLD image. */
#define          MC_CMD_NVRAM_TYPE_CPLD 0x11
/* enum: Licensing information. */
#define          MC_CMD_NVRAM_TYPE_LICENSE 0x12
/* enum: FC Log. */
#define          MC_CMD_NVRAM_TYPE_FC_LOG 0x13
/* enum: Additional flash on FPGA. */
#define          MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14


/***********************************/
/* MC_CMD_NVRAM_INFO
 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
 * EINVAL (bad type).
 */
#define MC_CMD_NVRAM_INFO 0x37
#undef MC_CMD_0x37_PRIVILEGE_CTG

#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_INFO_IN msgrequest */
#define    MC_CMD_NVRAM_INFO_IN_LEN 4
#define       MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */

/* MC_CMD_NVRAM_INFO_OUT msgresponse */
#define    MC_CMD_NVRAM_INFO_OUT_LEN 24
#define       MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
#define       MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
#define       MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
#define       MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
#define       MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
#define       MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
#define       MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
#define       MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
#define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_OFST 12
#define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
#define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
#define        MC_CMD_NVRAM_INFO_OUT_TLV_OFST 12
#define        MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
#define        MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
#define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
#define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
#define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
#define        MC_CMD_NVRAM_INFO_OUT_CRC_OFST 12
#define        MC_CMD_NVRAM_INFO_OUT_CRC_LBN 3
#define        MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 1
#define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_OFST 12
#define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
#define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
#define        MC_CMD_NVRAM_INFO_OUT_CMAC_OFST 12
#define        MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
#define        MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
#define        MC_CMD_NVRAM_INFO_OUT_A_B_OFST 12
#define        MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
#define        MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
#define       MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
#define       MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
#define       MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
#define       MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4

/* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */
#define    MC_CMD_NVRAM_INFO_V2_OUT_LEN 28
#define       MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
#define       MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
#define       MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
#define       MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
#define       MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8
#define       MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
#define       MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12
#define       MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
#define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_OFST 12
#define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
#define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
#define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_OFST 12
#define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
#define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
#define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
#define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
#define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
#define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_OFST 12
#define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
#define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
#define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 12
#define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
#define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
#define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16
#define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
#define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20
#define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
/* Writes must be multiples of this size. Added to support the MUM on Sorrento.
 */
#define       MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24
#define       MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4


/***********************************/
/* MC_CMD_NVRAM_UPDATE_START
 * Start a group of update operations on a virtual NVRAM partition. Locks
 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
 * PHY_LOCK required and not held). In an adapter bound to a TSA controller,
 * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types
 * i.e. static config, dynamic config and expansion ROM config. Attempting to
 * perform this operation on a restricted partition will return the error
 * EPERM.
 */
#define MC_CMD_NVRAM_UPDATE_START 0x38
#undef MC_CMD_0x38_PRIVILEGE_CTG

#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.
 * Use NVRAM_UPDATE_START_V2_IN in new code
 */
#define    MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
#define       MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */

/* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START
 * request with additional flags indicating version of command in use. See
 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use
 * paired up with NVRAM_UPDATE_FINISH_V2_IN.
 */
#define    MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8
#define       MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
#define       MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
#define       MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
#define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
#define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
#define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1

/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
#define    MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0


/***********************************/
/* MC_CMD_NVRAM_READ
 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
 * PHY_LOCK required and not held)
 */
#define MC_CMD_NVRAM_READ 0x39
#undef MC_CMD_0x39_PRIVILEGE_CTG

#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_READ_IN msgrequest */
#define    MC_CMD_NVRAM_READ_IN_LEN 12
#define       MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
#define       MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
#define       MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
/* amount to read in bytes */
#define       MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
#define       MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4

/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */
#define    MC_CMD_NVRAM_READ_IN_V2_LEN 16
#define       MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
#define       MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
#define       MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
#define       MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
/* amount to read in bytes */
#define       MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8
#define       MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
/* Optional control info. If a partition is stored with an A/B versioning
 * scheme (i.e. in more than one physical partition in NVRAM) the host can set
 * this to control which underlying physical partition is used to read data
 * from. This allows it to perform a read-modify-write-verify with the write
 * lock continuously held by calling NVRAM_UPDATE_START, reading the old
 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then
 * verifying by reading with MODE=TARGET_BACKUP.
 */
#define       MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12
#define       MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
/* enum: Same as omitting MODE: caller sees data in current partition unless it
 * holds the write lock in which case it sees data in the partition it is
 * updating.
 */
#define          MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
/* enum: Read from the current partition of an A/B pair, even if holding the
 * write lock.
 */
#define          MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
/* enum: Read from the non-current (i.e. to be updated) partition of an A/B
 * pair
 */
#define          MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2

/* MC_CMD_NVRAM_READ_OUT msgresponse */
#define    MC_CMD_NVRAM_READ_OUT_LENMIN 1
#define    MC_CMD_NVRAM_READ_OUT_LENMAX 252
#define    MC_CMD_NVRAM_READ_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
#define    MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
#define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
#define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
#define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
#define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
#define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM_MCDI2 1020


/***********************************/
/* MC_CMD_NVRAM_WRITE
 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
 * PHY_LOCK required and not held)
 */
#define MC_CMD_NVRAM_WRITE 0x3a
#undef MC_CMD_0x3a_PRIVILEGE_CTG

#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_WRITE_IN msgrequest */
#define    MC_CMD_NVRAM_WRITE_IN_LENMIN 13
#define    MC_CMD_NVRAM_WRITE_IN_LENMAX 252
#define    MC_CMD_NVRAM_WRITE_IN_LENMAX_MCDI2 1020
#define    MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
#define    MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
#define       MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
#define       MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
#define       MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
#define       MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
#define       MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
#define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
#define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
#define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
#define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
#define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM_MCDI2 1008

/* MC_CMD_NVRAM_WRITE_OUT msgresponse */
#define    MC_CMD_NVRAM_WRITE_OUT_LEN 0


/***********************************/
/* MC_CMD_NVRAM_ERASE
 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
 * PHY_LOCK required and not held)
 */
#define MC_CMD_NVRAM_ERASE 0x3b
#undef MC_CMD_0x3b_PRIVILEGE_CTG

#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_ERASE_IN msgrequest */
#define    MC_CMD_NVRAM_ERASE_IN_LEN 12
#define       MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
#define       MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
#define       MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
#define       MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
#define       MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4

/* MC_CMD_NVRAM_ERASE_OUT msgresponse */
#define    MC_CMD_NVRAM_ERASE_OUT_LEN 0


/***********************************/
/* MC_CMD_NVRAM_UPDATE_FINISH
 * Finish a group of update operations on a virtual NVRAM partition. Locks
 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
 * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to
 * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of
 * partition types i.e. static config, dynamic config and expansion ROM config.
 * Attempting to perform this operation on a restricted partition will return
 * the error EPERM.
 */
#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
#undef MC_CMD_0x3c_PRIVILEGE_CTG

#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH
 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code
 */
#define    MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
#define       MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
#define       MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
#define       MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4

/* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH
 * request with additional flags indicating version of NVRAM_UPDATE commands in
 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended
 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.
 */
#define    MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12
#define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
#define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
#define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
#define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8
#define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 8
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 8
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_OFST 8
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_LBN 3
#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_WIDTH 1

/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
 */
#define    MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0

/* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:
 *
 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure
 * firmware validation where applicable back to the host.
 *
 * Medford only: For signed firmware images, such as those for medford, the MC
 * firmware verifies the signature before marking the firmware image as valid.
 * This process takes a few seconds to complete. So is likely to take more than
 * the MCDI timeout. Hence signature verification is initiated when
 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the
 * MCDI command is run in a background MCDI processing thread. This response
 * payload includes the results of the signature verification. Note that the
 * per-partition nvram lock in firmware is only released after the verification
 * has completed.
 */
#define    MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
/* Result of nvram update completion processing. Result codes that indicate an
 * internal build failure and therefore not expected to be seen by customers in
 * the field are marked with a prefix 'Internal-error'.
 */
#define       MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
#define       MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
/* enum: Invalid return code; only non-zero values are defined. Defined as
 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
/* enum: Verify succeeded without any errors. */
#define          MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
/* enum: CMS format verification failed due to an internal error. */
#define          MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
/* enum: Invalid CMS format in image metadata. */
#define          MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
/* enum: Message digest verification failed due to an internal error. */
#define          MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
/* enum: Error in message digest calculated over the reflash-header, payload
 * and reflash-trailer.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
/* enum: Signature verification failed due to an internal error. */
#define          MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
/* enum: There are no valid signatures in the image. */
#define          MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
/* enum: Trusted approvers verification failed due to an internal error. */
#define          MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
/* enum: The Trusted approver's list is empty. */
#define          MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
/* enum: Signature chain verification failed due to an internal error. */
#define          MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
/* enum: The signers of the signatures in the image are not listed in the
 * Trusted approver's list.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
/* enum: The image contains a test-signed certificate, but the adapter accepts
 * only production signed images.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
/* enum: The image has a lower security level than the current firmware. */
#define          MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
/* enum: Internal-error. The signed image is missing the 'contents' section,
 * where the 'contents' section holds the actual image payload to be applied.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
/* enum: Internal-error. The bundle header is invalid. */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
/* enum: Internal-error. The bundle does not have a valid reflash image layout.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
/* enum: Internal-error. The bundle has an inconsistent layout of components or
 * incorrect checksum.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
/* enum: Internal-error. The bundle manifest is inconsistent with components in
 * the bundle.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
/* enum: Internal-error. The number of components in a bundle do not match the
 * number of components advertised by the bundle manifest.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
/* enum: Internal-error. The bundle contains too many components for the MC
 * firmware to process
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
/* enum: Internal-error. The bundle manifest has an invalid/inconsistent
 * component.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
/* enum: Internal-error. The hash of a component does not match the hash stored
 * in the bundle manifest.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
/* enum: Internal-error. Component hash calculation failed. */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
/* enum: Internal-error. The component does not have a valid reflash image
 * layout.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
/* enum: The bundle processing code failed to copy a component to its target
 * partition.
 */
#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
/* enum: The update operation is in-progress. */
#define          MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a


/***********************************/
/* MC_CMD_REBOOT
 * Reboot the MC.
 *
 * The AFTER_ASSERTION flag is intended to be used when the driver notices an
 * assertion failure (at which point it is expected to perform a complete tear
 * down and reinitialise), to allow both ports to reset the MC once in an
 * atomic fashion.
 *
 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
 * which means that they will automatically reboot out of the assertion
 * handler, so this is in practise an optional operation. It is still
 * recommended that drivers execute this to support custom firmwares with
 * REBOOT_ON_ASSERT=0.
 *
 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
 * DATALEN=0
 */
#define MC_CMD_REBOOT 0x3d
#undef MC_CMD_0x3d_PRIVILEGE_CTG

#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_REBOOT_IN msgrequest */
#define    MC_CMD_REBOOT_IN_LEN 4
#define       MC_CMD_REBOOT_IN_FLAGS_OFST 0
#define       MC_CMD_REBOOT_IN_FLAGS_LEN 4
#define          MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */

/* MC_CMD_REBOOT_OUT msgresponse */
#define    MC_CMD_REBOOT_OUT_LEN 0


/***********************************/
/* MC_CMD_SCHEDINFO
 * Request scheduler info. Locks required: NONE. Returns: An array of
 * (timeslice,maximum overrun), one for each thread, in ascending order of
 * thread address.
 */
#define MC_CMD_SCHEDINFO 0x3e
#undef MC_CMD_0x3e_PRIVILEGE_CTG

#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_SCHEDINFO_IN msgrequest */
#define    MC_CMD_SCHEDINFO_IN_LEN 0

/* MC_CMD_SCHEDINFO_OUT msgresponse */
#define    MC_CMD_SCHEDINFO_OUT_LENMIN 4
#define    MC_CMD_SCHEDINFO_OUT_LENMAX 252
#define    MC_CMD_SCHEDINFO_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
#define    MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
#define       MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
#define       MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
#define       MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
#define       MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
#define       MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM_MCDI2 255


/***********************************/
/* MC_CMD_REBOOT_MODE
 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
 * mode to the specified value. Returns the old mode.
 */
#define MC_CMD_REBOOT_MODE 0x3f
#undef MC_CMD_0x3f_PRIVILEGE_CTG

#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_REBOOT_MODE_IN msgrequest */
#define    MC_CMD_REBOOT_MODE_IN_LEN 4
#define       MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
#define       MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
/* enum: Normal. */
#define          MC_CMD_REBOOT_MODE_NORMAL 0x0
/* enum: Power-on Reset. */
#define          MC_CMD_REBOOT_MODE_POR 0x2
/* enum: Snapper. */
#define          MC_CMD_REBOOT_MODE_SNAPPER 0x3
/* enum: snapper fake POR */
#define          MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
#define        MC_CMD_REBOOT_MODE_IN_FAKE_OFST 0
#define        MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
#define        MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1

/* MC_CMD_REBOOT_MODE_OUT msgresponse */
#define    MC_CMD_REBOOT_MODE_OUT_LEN 4
#define       MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
#define       MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4


/***********************************/
/* MC_CMD_SENSOR_INFO
 * Returns information about every available sensor.
 *
 * Each sensor has a single (16bit) value, and a corresponding state. The
 * mapping between value and state is nominally determined by the MC, but may
 * be implemented using up to 2 ranges per sensor.
 *
 * This call returns a mask (32bit) of the sensors that are supported by this
 * platform, then an array of sensor information structures, in order of sensor
 * type (but without gaps for unimplemented sensors). Each structure defines
 * the ranges for the corresponding sensor. An unused range is indicated by
 * equal limit values. If one range is used, a value outside that range results
 * in STATE_FATAL. If two ranges are used, a value outside the second range
 * results in STATE_FATAL while a value outside the first and inside the second
 * range results in STATE_WARNING.
 *
 * Sensor masks and sensor information arrays are organised into pages. For
 * backward compatibility, older host software can only use sensors in page 0.
 * Bit 32 in the sensor mask was previously unused, and is no reserved for use
 * as the next page flag.
 *
 * If the request does not contain a PAGE value then firmware will only return
 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
 *
 * If the request contains a PAGE value then firmware responds with the sensor
 * mask and sensor information array for that page of sensors. In this case bit
 * 31 in the mask is set if another page exists.
 *
 * Locks required: None Returns: 0
 */
#define MC_CMD_SENSOR_INFO 0x41
#undef MC_CMD_0x41_PRIVILEGE_CTG

#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_SENSOR_INFO_IN msgrequest */
#define    MC_CMD_SENSOR_INFO_IN_LEN 0

/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
#define    MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
/* Which page of sensors to report.
 *
 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
 *
 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
 */
#define       MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
#define       MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4

/* MC_CMD_SENSOR_INFO_EXT_IN_V2 msgrequest */
#define    MC_CMD_SENSOR_INFO_EXT_IN_V2_LEN 8
/* Which page of sensors to report.
 *
 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
 *
 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
 */
#define       MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0
#define       MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
/* Flags controlling information retrieved */
#define       MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
#define       MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
#define        MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
#define        MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0
#define        MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1

/* MC_CMD_SENSOR_INFO_OUT msgresponse */
#define    MC_CMD_SENSOR_INFO_OUT_LENMIN 4
#define    MC_CMD_SENSOR_INFO_OUT_LENMAX 252
#define    MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
#define    MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
#define       MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
#define       MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
/* enum: Controller temperature: degC */
#define          MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
/* enum: Phy common temperature: degC */
#define          MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
/* enum: Controller cooling: bool */
#define          MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
/* enum: Phy 0 temperature: degC */
#define          MC_CMD_SENSOR_PHY0_TEMP 0x3
/* enum: Phy 0 cooling: bool */
#define          MC_CMD_SENSOR_PHY0_COOLING 0x4
/* enum: Phy 1 temperature: degC */
#define          MC_CMD_SENSOR_PHY1_TEMP 0x5
/* enum: Phy 1 cooling: bool */
#define          MC_CMD_SENSOR_PHY1_COOLING 0x6
/* enum: 1.0v power: mV */
#define          MC_CMD_SENSOR_IN_1V0 0x7
/* enum: 1.2v power: mV */
#define          MC_CMD_SENSOR_IN_1V2 0x8
/* enum: 1.8v power: mV */
#define          MC_CMD_SENSOR_IN_1V8 0x9
/* enum: 2.5v power: mV */
#define          MC_CMD_SENSOR_IN_2V5 0xa
/* enum: 3.3v power: mV */
#define          MC_CMD_SENSOR_IN_3V3 0xb
/* enum: 12v power: mV */
#define          MC_CMD_SENSOR_IN_12V0 0xc
/* enum: 1.2v analogue power: mV */
#define          MC_CMD_SENSOR_IN_1V2A 0xd
/* enum: reference voltage: mV */
#define          MC_CMD_SENSOR_IN_VREF 0xe
/* enum: AOE FPGA power: mV */
#define          MC_CMD_SENSOR_OUT_VAOE 0xf
/* enum: AOE FPGA temperature: degC */
#define          MC_CMD_SENSOR_AOE_TEMP 0x10
/* enum: AOE FPGA PSU temperature: degC */
#define          MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
/* enum: AOE PSU temperature: degC */
#define          MC_CMD_SENSOR_PSU_TEMP 0x12
/* enum: Fan 0 speed: RPM */
#define          MC_CMD_SENSOR_FAN_0 0x13
/* enum: Fan 1 speed: RPM */
#define          MC_CMD_SENSOR_FAN_1 0x14
/* enum: Fan 2 speed: RPM */
#define          MC_CMD_SENSOR_FAN_2 0x15
/* enum: Fan 3 speed: RPM */
#define          MC_CMD_SENSOR_FAN_3 0x16
/* enum: Fan 4 speed: RPM */
#define          MC_CMD_SENSOR_FAN_4 0x17
/* enum: AOE FPGA input power: mV */
#define          MC_CMD_SENSOR_IN_VAOE 0x18
/* enum: AOE FPGA current: mA */
#define          MC_CMD_SENSOR_OUT_IAOE 0x19
/* enum: AOE FPGA input current: mA */
#define          MC_CMD_SENSOR_IN_IAOE 0x1a
/* enum: NIC power consumption: W */
#define          MC_CMD_SENSOR_NIC_POWER 0x1b
/* enum: 0.9v power voltage: mV */
#define          MC_CMD_SENSOR_IN_0V9 0x1c
/* enum: 0.9v power current: mA */
#define          MC_CMD_SENSOR_IN_I0V9 0x1d
/* enum: 1.2v power current: mA */
#define          MC_CMD_SENSOR_IN_I1V2 0x1e
/* enum: Not a sensor: reserved for the next page flag */
#define          MC_CMD_SENSOR_PAGE0_NEXT 0x1f
/* enum: 0.9v power voltage (at ADC): mV */
#define          MC_CMD_SENSOR_IN_0V9_ADC 0x20
/* enum: Controller temperature 2: degC */
#define          MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
/* enum: Voltage regulator internal temperature: degC */
#define          MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
/* enum: 0.9V voltage regulator temperature: degC */
#define          MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
/* enum: 1.2V voltage regulator temperature: degC */
#define          MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
/* enum: controller internal temperature sensor voltage (internal ADC): mV */
#define          MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
/* enum: controller internal temperature (internal ADC): degC */
#define          MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
/* enum: controller internal temperature sensor voltage (external ADC): mV */
#define          MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
/* enum: controller internal temperature (external ADC): degC */
#define          MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
/* enum: ambient temperature: degC */
#define          MC_CMD_SENSOR_AMBIENT_TEMP 0x29
/* enum: air flow: bool */
#define          MC_CMD_SENSOR_AIRFLOW 0x2a
/* enum: voltage between VSS08D and VSS08D at CSR: mV */
#define          MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
#define          MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
/* enum: Hotpoint temperature: degC */
#define          MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
/* enum: Port 0 PHY power switch over-current: bool */
#define          MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
/* enum: Port 1 PHY power switch over-current: bool */
#define          MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
/* enum: Mop-up microcontroller reference voltage: mV */
#define          MC_CMD_SENSOR_MUM_VCC 0x30
/* enum: 0.9v power phase A voltage: mV */
#define          MC_CMD_SENSOR_IN_0V9_A 0x31
/* enum: 0.9v power phase A current: mA */
#define          MC_CMD_SENSOR_IN_I0V9_A 0x32
/* enum: 0.9V voltage regulator phase A temperature: degC */
#define          MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
/* enum: 0.9v power phase B voltage: mV */
#define          MC_CMD_SENSOR_IN_0V9_B 0x34
/* enum: 0.9v power phase B current: mA */
#define          MC_CMD_SENSOR_IN_I0V9_B 0x35
/* enum: 0.9V voltage regulator phase B temperature: degC */
#define          MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
#define          MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
/* enum: CCOM AVREG 1v2 supply (external ADC): mV */
#define          MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
#define          MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
/* enum: CCOM AVREG 1v8 supply (external ADC): mV */
#define          MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
/* enum: CCOM RTS temperature: degC */
#define          MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
/* enum: Not a sensor: reserved for the next page flag */
#define          MC_CMD_SENSOR_PAGE1_NEXT 0x3f
/* enum: controller internal temperature sensor voltage on master core
 * (internal ADC): mV
 */
#define          MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
/* enum: controller internal temperature on master core (internal ADC): degC */
#define          MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
/* enum: controller internal temperature sensor voltage on master core
 * (external ADC): mV
 */
#define          MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
/* enum: controller internal temperature on master core (external ADC): degC */
#define          MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
/* enum: controller internal temperature on slave core sensor voltage (internal
 * ADC): mV
 */
#define          MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
/* enum: controller internal temperature on slave core (internal ADC): degC */
#define          MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
/* enum: controller internal temperature on slave core sensor voltage (external
 * ADC): mV
 */
#define          MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
/* enum: controller internal temperature on slave core (external ADC): degC */
#define          MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
/* enum: Voltage supplied to the SODIMMs from their power supply: mV */
#define          MC_CMD_SENSOR_SODIMM_VOUT 0x49
/* enum: Temperature of SODIMM 0 (if installed): degC */
#define          MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
/* enum: Temperature of SODIMM 1 (if installed): degC */
#define          MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
#define          MC_CMD_SENSOR_PHY0_VCC 0x4c
/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
#define          MC_CMD_SENSOR_PHY1_VCC 0x4d
/* enum: Controller die temperature (TDIODE): degC */
#define          MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
/* enum: Board temperature (front): degC */
#define          MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
/* enum: Board temperature (back): degC */
#define          MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
/* enum: 1.8v power current: mA */
#define          MC_CMD_SENSOR_IN_I1V8 0x51
/* enum: 2.5v power current: mA */
#define          MC_CMD_SENSOR_IN_I2V5 0x52
/* enum: 3.3v power current: mA */
#define          MC_CMD_SENSOR_IN_I3V3 0x53
/* enum: 12v power current: mA */
#define          MC_CMD_SENSOR_IN_I12V0 0x54
/* enum: 1.3v power: mV */
#define          MC_CMD_SENSOR_IN_1V3 0x55
/* enum: 1.3v power current: mA */
#define          MC_CMD_SENSOR_IN_I1V3 0x56
/* enum: Engineering sensor 1 */
#define          MC_CMD_SENSOR_ENGINEERING_1 0x57
/* enum: Engineering sensor 2 */
#define          MC_CMD_SENSOR_ENGINEERING_2 0x58
/* enum: Engineering sensor 3 */
#define          MC_CMD_SENSOR_ENGINEERING_3 0x59
/* enum: Engineering sensor 4 */
#define          MC_CMD_SENSOR_ENGINEERING_4 0x5a
/* enum: Engineering sensor 5 */
#define          MC_CMD_SENSOR_ENGINEERING_5 0x5b
/* enum: Engineering sensor 6 */
#define          MC_CMD_SENSOR_ENGINEERING_6 0x5c
/* enum: Engineering sensor 7 */
#define          MC_CMD_SENSOR_ENGINEERING_7 0x5d
/* enum: Engineering sensor 8 */
#define          MC_CMD_SENSOR_ENGINEERING_8 0x5e
/* enum: Not a sensor: reserved for the next page flag */
#define          MC_CMD_SENSOR_PAGE2_NEXT 0x5f
/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
#define       MC_CMD_SENSOR_ENTRY_OFST 4
#define       MC_CMD_SENSOR_ENTRY_LEN 8
#define       MC_CMD_SENSOR_ENTRY_LO_OFST 4
#define       MC_CMD_SENSOR_ENTRY_LO_LEN 4
#define       MC_CMD_SENSOR_ENTRY_LO_LBN 32
#define       MC_CMD_SENSOR_ENTRY_LO_WIDTH 32
#define       MC_CMD_SENSOR_ENTRY_HI_OFST 8
#define       MC_CMD_SENSOR_ENTRY_HI_LEN 4
#define       MC_CMD_SENSOR_ENTRY_HI_LBN 64
#define       MC_CMD_SENSOR_ENTRY_HI_WIDTH 32
#define       MC_CMD_SENSOR_ENTRY_MINNUM 0
#define       MC_CMD_SENSOR_ENTRY_MAXNUM 31
#define       MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127

/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
#define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
#define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
#define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
#define    MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
#define       MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
#define       MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_SENSOR_INFO_OUT */
#define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0
#define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
#define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
/*            MC_CMD_SENSOR_ENTRY_OFST 4 */
/*            MC_CMD_SENSOR_ENTRY_LEN 8 */
/*            MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
/*            MC_CMD_SENSOR_ENTRY_LO_LEN 4 */
/*            MC_CMD_SENSOR_ENTRY_LO_LBN 32 */
/*            MC_CMD_SENSOR_ENTRY_LO_WIDTH 32 */
/*            MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
/*            MC_CMD_SENSOR_ENTRY_HI_LEN 4 */
/*            MC_CMD_SENSOR_ENTRY_HI_LBN 64 */
/*            MC_CMD_SENSOR_ENTRY_HI_WIDTH 32 */
/*            MC_CMD_SENSOR_ENTRY_MINNUM 0 */
/*            MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
/*            MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */

/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
#define    MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
#define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16


/***********************************/
/* MC_CMD_READ_SENSORS
 * Returns the current reading from each sensor. DMAs an array of sensor
 * readings, in order of sensor type (but without gaps for unimplemented
 * sensors), into host memory. Each array element is a
 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
 *
 * If the request does not contain the LENGTH field then only sensors 0 to 30
 * are reported, to avoid DMA buffer overflow in older host software. If the
 * sensor reading require more space than the LENGTH allows, then return
 * EINVAL.
 *
 * The MC will send a SENSOREVT event every time any sensor changes state. The
 * driver is responsible for ensuring that it doesn't miss any events. The
 * board will function normally if all sensors are in STATE_OK or
 * STATE_WARNING. Otherwise the board should not be expected to function.
 */
#define MC_CMD_READ_SENSORS 0x42
#undef MC_CMD_0x42_PRIVILEGE_CTG

#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_READ_SENSORS_IN msgrequest */
#define    MC_CMD_READ_SENSORS_IN_LEN 8
/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
 *
 * If the address is 0xffffffffffffffff send the readings in the response (used
 * by cmdclient).
 */
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_WIDTH 32
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LBN 32
#define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_WIDTH 32

/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
#define    MC_CMD_READ_SENSORS_EXT_IN_LEN 12
/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
 *
 * If the address is 0xffffffffffffffff send the readings in the response (used
 * by cmdclient).
 */
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LBN 32
#define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_WIDTH 32
/* Size in bytes of host buffer. */
#define       MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
#define       MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4

/* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */
#define    MC_CMD_READ_SENSORS_EXT_IN_V2_LEN 16
/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
 *
 * If the address is 0xffffffffffffffff send the readings in the response (used
 * by cmdclient).
 */
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_WIDTH 32
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LBN 32
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_WIDTH 32
/* Size in bytes of host buffer. */
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
/* Flags controlling information retrieved */
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 12
#define       MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
#define        MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 12
#define        MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0
#define        MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1

/* MC_CMD_READ_SENSORS_OUT msgresponse */
#define    MC_CMD_READ_SENSORS_OUT_LEN 0

/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
#define    MC_CMD_READ_SENSORS_EXT_OUT_LEN 0

/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
#define    MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
/* enum: Ok. */
#define          MC_CMD_SENSOR_STATE_OK 0x0
/* enum: Breached warning threshold. */
#define          MC_CMD_SENSOR_STATE_WARNING 0x1
/* enum: Breached fatal threshold. */
#define          MC_CMD_SENSOR_STATE_FATAL 0x2
/* enum: Fault with sensor. */
#define          MC_CMD_SENSOR_STATE_BROKEN 0x3
/* enum: Sensor is working but does not currently have a reading. */
#define          MC_CMD_SENSOR_STATE_NO_READING 0x4
/* enum: Sensor initialisation failed. */
#define          MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
/*            Enum values, see field(s): */
/*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
#define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8


/***********************************/
/* MC_CMD_GET_PHY_STATE
 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
 * (e.g. due to missing or corrupted firmware). Locks required: None. Return
 * code: 0
 */
#define MC_CMD_GET_PHY_STATE 0x43
#undef MC_CMD_0x43_PRIVILEGE_CTG

#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_GET_PHY_STATE_IN msgrequest */
#define    MC_CMD_GET_PHY_STATE_IN_LEN 0

/* MC_CMD_GET_PHY_STATE_OUT msgresponse */
#define    MC_CMD_GET_PHY_STATE_OUT_LEN 4
#define       MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
#define       MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
/* enum: Ok. */
#define          MC_CMD_PHY_STATE_OK 0x1
/* enum: Faulty. */
#define          MC_CMD_PHY_STATE_ZOMBIE 0x2


/***********************************/
/* MC_CMD_SETUP_8021QBB
 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
 * disable 802.Qbb for a given priority.
 */
#define MC_CMD_SETUP_8021QBB 0x44

/* MC_CMD_SETUP_8021QBB_IN msgrequest */
#define    MC_CMD_SETUP_8021QBB_IN_LEN 32
#define       MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
#define       MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32

/* MC_CMD_SETUP_8021QBB_OUT msgresponse */
#define    MC_CMD_SETUP_8021QBB_OUT_LEN 0


/***********************************/
/* MC_CMD_WOL_FILTER_GET
 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
 */
#define MC_CMD_WOL_FILTER_GET 0x45
#undef MC_CMD_0x45_PRIVILEGE_CTG

#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK

/* MC_CMD_WOL_FILTER_GET_IN msgrequest */
#define    MC_CMD_WOL_FILTER_GET_IN_LEN 0

/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
#define    MC_CMD_WOL_FILTER_GET_OUT_LEN 4
#define       MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
#define       MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4


/***********************************/
/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
 * Add a protocol offload to NIC for lights-out state. Locks required: None.
 * Returns: 0, ENOSYS
 */
#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
#undef MC_CMD_0x46_PRIVILEGE_CTG

#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK

/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX_MCDI2 1020
#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
#define          MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
#define          MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM_MCDI2 254

/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
/*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
/*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4

/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
/*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
/*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16

/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4


/***********************************/
/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
 * Remove a protocol offload from NIC for lights-out state. Locks required:
 * None. Returns: 0, ENOSYS
 */
#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
#undef MC_CMD_0x47_PRIVILEGE_CTG

#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK

/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
#define    MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
#define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
#define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
#define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
#define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4

/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
#define    MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0


/***********************************/
/* MC_CMD_MAC_RESET_RESTORE
 * Restore MAC after block reset. Locks required: None. Returns: 0.
 */
#define MC_CMD_MAC_RESET_RESTORE 0x48

/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
#define    MC_CMD_MAC_RESET_RESTORE_IN_LEN 0

/* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
#define    MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0


/***********************************/
/* MC_CMD_TESTASSERT
 * Deliberately trigger an assert-detonation in the firmware for testing
 * purposes (i.e. to allow tests that the driver copes gracefully). Locks
 * required: None Returns: 0
 */
#define MC_CMD_TESTASSERT 0x49
#undef MC_CMD_0x49_PRIVILEGE_CTG

#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_TESTASSERT_IN msgrequest */
#define    MC_CMD_TESTASSERT_IN_LEN 0

/* MC_CMD_TESTASSERT_OUT msgresponse */
#define    MC_CMD_TESTASSERT_OUT_LEN 0

/* MC_CMD_TESTASSERT_V2_IN msgrequest */
#define    MC_CMD_TESTASSERT_V2_IN_LEN 4
/* How to provoke the assertion */
#define       MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
#define       MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
/* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless
 * you're testing firmware, this is what you want.
 */
#define          MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
/* enum: Assert using assert(0); */
#define          MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
/* enum: Deliberately trigger a watchdog */
#define          MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
/* enum: Deliberately trigger a trap by loading from an invalid address */
#define          MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
/* enum: Deliberately trigger a trap by storing to an invalid address */
#define          MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
/* enum: Jump to an invalid address */
#define          MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5

/* MC_CMD_TESTASSERT_V2_OUT msgresponse */
#define    MC_CMD_TESTASSERT_V2_OUT_LEN 0


/***********************************/
/* MC_CMD_WORKAROUND
 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
 * understand the given workaround number - which should not be treated as a
 * hard error by client code. This op does not imply any semantics about each
 * workaround, that's between the driver and the mcfw on a per-workaround
 * basis. Locks required: None. Returns: 0, EINVAL .
 */
#define MC_CMD_WORKAROUND 0x4a
#undef MC_CMD_0x4a_PRIVILEGE_CTG

#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_WORKAROUND_IN msgrequest */
#define    MC_CMD_WORKAROUND_IN_LEN 8
/* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */
#define       MC_CMD_WORKAROUND_IN_TYPE_OFST 0
#define       MC_CMD_WORKAROUND_IN_TYPE_LEN 4
/* enum: Bug 17230 work around. */
#define          MC_CMD_WORKAROUND_BUG17230 0x1
/* enum: Bug 35388 work around (unsafe EVQ writes). */
#define          MC_CMD_WORKAROUND_BUG35388 0x2
/* enum: Bug35017 workaround (A64 tables must be identity map) */
#define          MC_CMD_WORKAROUND_BUG35017 0x3
/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
#define          MC_CMD_WORKAROUND_BUG41750 0x4
/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
 * - before adding code that queries this workaround, remember that there's
 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
 * and will hence (incorrectly) report that the bug doesn't exist.
 */
#define          MC_CMD_WORKAROUND_BUG42008 0x5
/* enum: Bug 26807 features present in firmware (multicast filter chaining)
 * This feature cannot be turned on/off while there are any filters already
 * present. The behaviour in such case depends on the acting client's privilege
 * level. If the client has the admin privilege, then all functions that have
 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise
 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
 */
#define          MC_CMD_WORKAROUND_BUG26807 0x6
/* enum: Bug 61265 work around (broken EVQ TMR writes). */
#define          MC_CMD_WORKAROUND_BUG61265 0x7
/* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
 * the workaround
 */
#define       MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
#define       MC_CMD_WORKAROUND_IN_ENABLED_LEN 4

/* MC_CMD_WORKAROUND_OUT msgresponse */
#define    MC_CMD_WORKAROUND_OUT_LEN 0

/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used
 * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
 */
#define    MC_CMD_WORKAROUND_EXT_OUT_LEN 4
#define       MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
#define       MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
#define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0
#define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
#define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1


/***********************************/
/* MC_CMD_GET_PHY_MEDIA_INFO
 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
 * SFP+ PHYs). The "media type" can be found via GET_PHY_CFG
 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid "page number" input values, and the
 * output data, are interpreted on a per-type basis. For SFP+, PAGE=0 or 1
 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
 * For QSFP, PAGE=-1 is the lower (unbanked) page. PAGE=2 is the EEPROM and
 * PAGE=3 is the module limits. For DSFP, module addressing requires a
 * "BANK:PAGE". Not every bank has the same number of pages. See the Common
 * Management Interface Specification (CMIS) for further details. A BANK:PAGE
 * of "0xffff:0xffff" retrieves the lower (unbanked) page. Locks required -
 * None. Return code - 0.
 */
#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
#undef MC_CMD_0x4b_PRIVILEGE_CTG

#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
#define    MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
#define       MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
#define       MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
#define        MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_OFST 0
#define        MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_LBN 0
#define        MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_WIDTH 16
#define        MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_OFST 0
#define        MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_LBN 16
#define        MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_WIDTH 16

/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
#define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
#define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
#define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
#define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
/* in bytes */
#define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
#define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
#define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
#define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
#define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
#define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
#define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM_MCDI2 1016


/***********************************/
/* MC_CMD_NVRAM_TEST
 * Test a particular NVRAM partition for valid contents (where "valid" depends
 * on the type of partition).
 */
#define MC_CMD_NVRAM_TEST 0x4c
#undef MC_CMD_0x4c_PRIVILEGE_CTG

#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_TEST_IN msgrequest */
#define    MC_CMD_NVRAM_TEST_IN_LEN 4
#define       MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */

/* MC_CMD_NVRAM_TEST_OUT msgresponse */
#define    MC_CMD_NVRAM_TEST_OUT_LEN 4
#define       MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
#define       MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
/* enum: Passed. */
#define          MC_CMD_NVRAM_TEST_PASS 0x0
/* enum: Failed. */
#define          MC_CMD_NVRAM_TEST_FAIL 0x1
/* enum: Not supported. */
#define          MC_CMD_NVRAM_TEST_NOTSUPP 0x2


/***********************************/
/* MC_CMD_MRSFP_TWEAK
 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.
 * I2C I/O expander bits are always read; if equaliser parameters are supplied,
 * they are configured first. Locks required: None. Return code: 0, EINVAL.
 */
#define MC_CMD_MRSFP_TWEAK 0x4d

/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
#define    MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
/* 0-6 low->high de-emph. */
#define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
#define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
/* 0-8 low->high ref.V */
#define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
#define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
/* 0-8 0-8 low->high boost */
#define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
#define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
/* 0-8 low->high ref.V */
#define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
#define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4

/* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
#define    MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0

/* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
#define    MC_CMD_MRSFP_TWEAK_OUT_LEN 12
/* input bits */
#define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
#define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
/* output bits */
#define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
#define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
/* direction */
#define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
#define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
/* enum: Out. */
#define          MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
/* enum: In. */
#define          MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1


/***********************************/
/* MC_CMD_SENSOR_SET_LIMS
 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out
 * of range.
 */
#define MC_CMD_SENSOR_SET_LIMS 0x4e
#undef MC_CMD_0x4e_PRIVILEGE_CTG

#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
#define    MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
#define       MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
#define       MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
/*            Enum values, see field(s): */
/*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
/* interpretation is is sensor-specific. */
#define       MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
#define       MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
/* interpretation is is sensor-specific. */
#define       MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
#define       MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
/* interpretation is is sensor-specific. */
#define       MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
#define       MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
/* interpretation is is sensor-specific. */
#define       MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
#define       MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4

/* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
#define    MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0


/***********************************/
/* MC_CMD_GET_RESOURCE_LIMITS
 */
#define MC_CMD_GET_RESOURCE_LIMITS 0x4f

/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
#define    MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0

/* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
#define    MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
#define       MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
#define       MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
#define       MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
#define       MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
#define       MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
#define       MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
#define       MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
#define       MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4


/***********************************/
/* MC_CMD_NVRAM_PARTITIONS
 * Reads the list of available virtual NVRAM partition types. Locks required:
 * none. Returns: 0, EINVAL (bad type).
 */
#define MC_CMD_NVRAM_PARTITIONS 0x51
#undef MC_CMD_0x51_PRIVILEGE_CTG

#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
#define    MC_CMD_NVRAM_PARTITIONS_IN_LEN 0

/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
#define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
#define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
#define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
#define    MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
/* total number of partitions */
#define       MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
#define       MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
/* type ID code for each of NUM_PARTITIONS partitions */
#define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
#define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
#define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
#define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
#define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM_MCDI2 254


/***********************************/
/* MC_CMD_NVRAM_METADATA
 * Reads soft metadata for a virtual NVRAM partition type. Locks required:
 * none. Returns: 0, EINVAL (bad type).
 */
#define MC_CMD_NVRAM_METADATA 0x52
#undef MC_CMD_0x52_PRIVILEGE_CTG

#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_NVRAM_METADATA_IN msgrequest */
#define    MC_CMD_NVRAM_METADATA_IN_LEN 4
/* Partition type ID code */
#define       MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
#define       MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4

/* MC_CMD_NVRAM_METADATA_OUT msgresponse */
#define    MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
#define    MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
#define    MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
#define    MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
/* Partition type ID code */
#define       MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
#define       MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
#define       MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
#define       MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
#define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
#define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
#define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
#define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
#define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
#define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
#define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
#define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
#define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
/* Subtype ID code for content of this partition */
#define       MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
#define       MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
/* 1st component of W.X.Y.Z version number for content of this partition */
#define       MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
#define       MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
/* 2nd component of W.X.Y.Z version number for content of this partition */
#define       MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
#define       MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
/* 3rd component of W.X.Y.Z version number for content of this partition */
#define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
#define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
/* 4th component of W.X.Y.Z version number for content of this partition */
#define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
#define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
/* Zero-terminated string describing the content of this partition */
#define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
#define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
#define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
#define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
#define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM_MCDI2 1000


/***********************************/
/* MC_CMD_GET_MAC_ADDRESSES
 * Returns the base MAC, count and stride for the requesting function
 */
#define MC_CMD_GET_MAC_ADDRESSES 0x55
#undef MC_CMD_0x55_PRIVILEGE_CTG

#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
#define    MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0

/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
#define    MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
/* Base MAC address */
#define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
#define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
/* Padding */
#define       MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
#define       MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
/* Number of allocated MAC addresses */
#define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
#define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
/* Spacing of allocated MAC addresses */
#define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
#define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4


/***********************************/
/* MC_CMD_CLP
 * Perform a CLP related operation, see SF-110495-PS for details of CLP
 * processing. This command has been extended to accomodate the requirements of
 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,
 * SF-120509-TC and SF-117282-PS.
 */
#define MC_CMD_CLP 0x56
#undef MC_CMD_0x56_PRIVILEGE_CTG

#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN

/* MC_CMD_CLP_IN msgrequest */
#define    MC_CMD_CLP_IN_LEN 4
/* Sub operation */
#define       MC_CMD_CLP_IN_OP_OFST 0
#define       MC_CMD_CLP_IN_OP_LEN 4
/* enum: Return to factory default settings */
#define          MC_CMD_CLP_OP_DEFAULT 0x1
/* enum: Set MAC address */
#define          MC_CMD_CLP_OP_SET_MAC 0x2
/* enum: Get MAC address */
#define          MC_CMD_CLP_OP_GET_MAC 0x3
/* enum: Set UEFI/GPXE boot mode */
#define          MC_CMD_CLP_OP_SET_BOOT 0x4
/* enum: Get UEFI/GPXE boot mode */
#define          MC_CMD_CLP_OP_GET_BOOT 0x5

/* MC_CMD_CLP_OUT msgresponse */
#define    MC_CMD_CLP_OUT_LEN 0

/* MC_CMD_CLP_IN_DEFAULT msgrequest */
#define    MC_CMD_CLP_IN_DEFAULT_LEN 4
/*            MC_CMD_CLP_IN_OP_OFST 0 */
/*            MC_CMD_CLP_IN_OP_LEN 4 */

/* MC_CMD_CLP_OUT_DEFAULT msgresponse */
#define    MC_CMD_CLP_OUT_DEFAULT_LEN 0

/* MC_CMD_CLP_IN_SET_MAC msgrequest */
#define    MC_CMD_CLP_IN_SET_MAC_LEN 12
/*            MC_CMD_CLP_IN_OP_OFST 0 */
/*            MC_CMD_CLP_IN_OP_LEN 4 */
/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00
 * restores the permanent (factory-programmed) MAC address associated with the
 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
 */
#define       MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
#define       MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6
/* Padding */
#define       MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10
#define       MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2

/* MC_CMD_CLP_OUT_SET_MAC msgresponse */
#define    MC_CMD_CLP_OUT_SET_MAC_LEN 0

/* MC_CMD_CLP_IN_SET_MAC_V2 msgrequest */
#define    MC_CMD_CLP_IN_SET_MAC_V2_LEN 16
/*            MC_CMD_CLP_IN_OP_OFST 0 */
/*            MC_CMD_CLP_IN_OP_LEN 4 */
/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00
 * restores the permanent (factory-programmed) MAC address associated with the
 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
 */
#define       MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4
#define       MC_CMD_CLP_IN_SET_MAC_V2_ADDR_LEN 6
/* Padding */
#define       MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_OFST 10
#define       MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 2
#define       MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 12
#define       MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4
#define        MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 12
#define        MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0
#define        MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1

/* MC_CMD_CLP_IN_GET_MAC msgrequest */
#define    MC_CMD_CLP_IN_GET_MAC_LEN 4
/*            MC_CMD_CLP_IN_OP_OFST 0 */
/*            MC_CMD_CLP_IN_OP_LEN 4 */

/* MC_CMD_CLP_IN_GET_MAC_V2 msgrequest */
#define    MC_CMD_CLP_IN_GET_MAC_V2_LEN 8
/*            MC_CMD_CLP_IN_OP_OFST 0 */
/*            MC_CMD_CLP_IN_OP_LEN 4 */
#define       MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4
#define       MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4
#define        MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4
#define        MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0
#define        MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 1

/* MC_CMD_CLP_OUT_GET_MAC msgresponse */
#define    MC_CMD_CLP_OUT_GET_MAC_LEN 8
/* MAC address assigned to port */
#define       MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
#define       MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6
/* Padding */
#define       MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6
#define       MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2

/* MC_CMD_CLP_IN_SET_BOOT msgrequest */
#define    MC_CMD_CLP_IN_SET_BOOT_LEN 5
/*            MC_CMD_CLP_IN_OP_OFST 0 */
/*            MC_CMD_CLP_IN_OP_LEN 4 */
/* Boot flag */
#define       MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
#define       MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1

/* MC_CMD_CLP_OUT_SET_BOOT msgresponse */
#define    MC_CMD_CLP_OUT_SET_BOOT_LEN 0

/* MC_CMD_CLP_IN_GET_BOOT msgrequest */
#define    MC_CMD_CLP_IN_GET_BOOT_LEN 4
/*            MC_CMD_CLP_IN_OP_OFST 0 */
/*            MC_CMD_CLP_IN_OP_LEN 4 */

/* MC_CMD_CLP_OUT_GET_BOOT msgresponse */
#define    MC_CMD_CLP_OUT_GET_BOOT_LEN 4
/* Boot flag */
#define       MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
#define       MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
/* Padding */
#define       MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
#define       MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3


/***********************************/
/* MC_CMD_MUM
 * Perform a MUM operation
 */
#define MC_CMD_MUM 0x57
#undef MC_CMD_0x57_PRIVILEGE_CTG

#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE

/* MC_CMD_MUM_IN msgrequest */
#define    MC_CMD_MUM_IN_LEN 4
#define       MC_CMD_MUM_IN_OP_HDR_OFST 0
#define       MC_CMD_MUM_IN_OP_HDR_LEN 4
#define        MC_CMD_MUM_IN_OP_OFST 0
#define        MC_CMD_MUM_IN_OP_LBN 0
#define        MC_CMD_MUM_IN_OP_WIDTH 8
/* enum: NULL MCDI command to MUM */
#define          MC_CMD_MUM_OP_NULL 0x1
/* enum: Get MUM version */
#define          MC_CMD_MUM_OP_GET_VERSION 0x2
/* enum: Issue raw I2C command to MUM */
#define          MC_CMD_MUM_OP_RAW_CMD 0x3
/* enum: Read from registers on devices connected to MUM. */
#define          MC_CMD_MUM_OP_READ 0x4
/* enum: Write to registers on devices connected to MUM. */
#define          MC_CMD_MUM_OP_WRITE 0x5
/* enum: Control UART logging. */
#define          MC_CMD_MUM_OP_LOG 0x6
/* enum: Operations on MUM GPIO lines */
#define          MC_CMD_MUM_OP_GPIO 0x7
/* enum: Get sensor readings from MUM */
#define          MC_CMD_MUM_OP_READ_SENSORS 0x8
/* enum: Initiate clock programming on the MUM */
#define          MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
/* enum: Initiate FPGA load from flash on the MUM */
#define          MC_CMD_MUM_OP_FPGA_LOAD 0xa
/* enum: Request sensor reading from MUM ADC resulting from earlier request via
 * MUM ATB
 */
#define          MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
/* enum: Send commands relating to the QSFP ports via the MUM for PHY
 * operations
 */
#define          MC_CMD_MUM_OP_QSFP 0xc
/* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage
 * level) from MUM
 */
#define          MC_CMD_MUM_OP_READ_DDR_INFO 0xd

/* MC_CMD_MUM_IN_NULL msgrequest */
#define    MC_CMD_MUM_IN_NULL_LEN 4
/* MUM cmd header */
#define       MC_CMD_MUM_IN_CMD_OFST 0
#define       MC_CMD_MUM_IN_CMD_LEN 4

/* MC_CMD_MUM_IN_GET_VERSION msgrequest */
#define    MC_CMD_MUM_IN_GET_VERSION_LEN 4
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */

/* MC_CMD_MUM_IN_READ msgrequest */
#define    MC_CMD_MUM_IN_READ_LEN 16
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
/* ID of (device connected to MUM) to read from registers of */
#define       MC_CMD_MUM_IN_READ_DEVICE_OFST 4
#define       MC_CMD_MUM_IN_READ_DEVICE_LEN 4
/* enum: Hittite HMC1035 clock generator on Sorrento board */
#define          MC_CMD_MUM_DEV_HITTITE 0x1
/* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
#define          MC_CMD_MUM_DEV_HITTITE_NIC 0x2
/* 32-bit address to read from */
#define       MC_CMD_MUM_IN_READ_ADDR_OFST 8
#define       MC_CMD_MUM_IN_READ_ADDR_LEN 4
/* Number of words to read. */
#define       MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12
#define       MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4

/* MC_CMD_MUM_IN_WRITE msgrequest */
#define    MC_CMD_MUM_IN_WRITE_LENMIN 16
#define    MC_CMD_MUM_IN_WRITE_LENMAX 252
#define    MC_CMD_MUM_IN_WRITE_LENMAX_MCDI2 1020
#define    MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
#define    MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
/* ID of (device connected to MUM) to write to registers of */
#define       MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
#define       MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
/* enum: Hittite HMC1035 clock generator on Sorrento board */
/*               MC_CMD_MUM_DEV_HITTITE 0x1 */
/* 32-bit address to write to */
#define       MC_CMD_MUM_IN_WRITE_ADDR_OFST 8
#define       MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
/* Words to write */
#define       MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12
#define       MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
#define       MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
#define       MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60
#define       MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM_MCDI2 252

/* MC_CMD_MUM_IN_RAW_CMD msgrequest */
#define    MC_CMD_MUM_IN_RAW_CMD_LENMIN 17
#define    MC_CMD_MUM_IN_RAW_CMD_LENMAX 252
#define    MC_CMD_MUM_IN_RAW_CMD_LENMAX_MCDI2 1020
#define    MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
#define    MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
/* MUM I2C cmd code */
#define       MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
#define       MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
/* Number of bytes to write */
#define       MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8
#define       MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
/* Number of bytes to read */
#define       MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12
#define       MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
/* Bytes to write */
#define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16
#define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
#define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
#define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236
#define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM_MCDI2 1004

/* MC_CMD_MUM_IN_LOG msgrequest */
#define    MC_CMD_MUM_IN_LOG_LEN 8
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_LOG_OP_OFST 4
#define       MC_CMD_MUM_IN_LOG_OP_LEN 4
#define          MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */

/* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */
#define    MC_CMD_MUM_IN_LOG_OP_UART_LEN 12
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
/*            MC_CMD_MUM_IN_LOG_OP_OFST 4 */
/*            MC_CMD_MUM_IN_LOG_OP_LEN 4 */
/* Enable/disable debug output to UART */
#define       MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8
#define       MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4

/* MC_CMD_MUM_IN_GPIO msgrequest */
#define    MC_CMD_MUM_IN_GPIO_LEN 8
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_HDR_LEN 4
#define        MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4
#define        MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
#define        MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8
#define          MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
#define          MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
#define          MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
#define          MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
#define          MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
#define          MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */

/* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */
#define    MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4

/* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */
#define    MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
/* The first 32-bit word to be written to the GPIO OUT register. */
#define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8
#define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
/* The second 32-bit word to be written to the GPIO OUT register. */
#define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12
#define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4

/* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */
#define    MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4

/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */
#define    MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
/* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
#define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8
#define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
/* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
#define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12
#define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4

/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */
#define    MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4

/* MC_CMD_MUM_IN_GPIO_OP msgrequest */
#define    MC_CMD_MUM_IN_GPIO_OP_LEN 8
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
#define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4
#define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8
#define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8
#define          MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
#define          MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
#define          MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
#define          MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
#define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4
#define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16
#define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8

/* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */
#define    MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4

/* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */
#define    MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
#define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4
#define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24
#define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8

/* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */
#define    MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
#define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4
#define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24
#define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8

/* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */
#define    MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
#define       MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
#define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4
#define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24
#define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8

/* MC_CMD_MUM_IN_READ_SENSORS msgrequest */
#define    MC_CMD_MUM_IN_READ_SENSORS_LEN 8
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
#define       MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
#define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4
#define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
#define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8
#define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4
#define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8
#define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8

/* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */
#define    MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
/* Bit-mask of clocks to be programmed */
#define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
#define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
#define          MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
#define          MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
#define          MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
/* Control flags for clock programming */
#define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8
#define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_OFST 8
#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_OFST 8
#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_OFST 8
#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2
#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1

/* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */
#define    MC_CMD_MUM_IN_FPGA_LOAD_LEN 8
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
/* Enable/Disable FPGA config from flash */
#define       MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
#define       MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4

/* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */
#define    MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */

/* MC_CMD_MUM_IN_QSFP msgrequest */
#define    MC_CMD_MUM_IN_QSFP_LEN 12
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_QSFP_HDR_OFST 4
#define       MC_CMD_MUM_IN_QSFP_HDR_LEN 4
#define        MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4
#define        MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
#define        MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
#define          MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
#define          MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
#define          MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
#define          MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
#define          MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
#define          MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
#define       MC_CMD_MUM_IN_QSFP_IDX_OFST 8
#define       MC_CMD_MUM_IN_QSFP_IDX_LEN 4

/* MC_CMD_MUM_IN_QSFP_INIT msgrequest */
#define    MC_CMD_MUM_IN_QSFP_INIT_LEN 16
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
#define       MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
#define       MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8
#define       MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
#define       MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12
#define       MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4

/* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */
#define    MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20
#define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4

/* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */
#define    MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
#define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
#define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8
#define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4

/* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */
#define    MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
#define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
#define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8
#define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
#define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12
#define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4

/* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */
#define    MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
#define       MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
#define       MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8
#define       MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4

/* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */
#define    MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */
#define       MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
#define       MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
#define       MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8
#define       MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4

/* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */
#define    MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
/* MUM cmd header */
/*            MC_CMD_MUM_IN_CMD_OFST 0 */
/*            MC_CMD_MUM_IN_CMD_LEN 4 */

/* MC_CMD_MUM_OUT msgresponse */
#define    MC_CMD_MUM_OUT_LEN 0

/* MC_CMD_MUM_OUT_NULL msgresponse */
#define    MC_CMD_MUM_OUT_NULL_LEN 0

/* MC_CMD_MUM_OUT_GET_VERSION msgresponse */
#define    MC_CMD_MUM_OUT_GET_VERSION_LEN 12
#define       MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
#define       MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 4
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LBN 32
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_WIDTH 32
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 4
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LBN 64
#define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_WIDTH 32

/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
#define    MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
#define    MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252
#define    MC_CMD_MUM_OUT_RAW_CMD_LENMAX_MCDI2 1020
#define    MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
#define    MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
/* returned data */
#define       MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
#define       MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
#define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
#define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252
#define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM_MCDI2 1020

/* MC_CMD_MUM_OUT_READ msgresponse */
#define    MC_CMD_MUM_OUT_READ_LENMIN 4
#define    MC_CMD_MUM_OUT_READ_LENMAX 252
#define    MC_CMD_MUM_OUT_READ_LENMAX_MCDI2 1020
#define    MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
#define    MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
#define       MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
#define       MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
#define       MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
#define       MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63
#define       MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM_MCDI2 255

/* MC_CMD_MUM_OUT_WRITE msgresponse */
#define    MC_CMD_MUM_OUT_WRITE_LEN 0

/* MC_CMD_MUM_OUT_LOG msgresponse */
#define    MC_CMD_MUM_OUT_LOG_LEN 0

/* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */
#define    MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0

/* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */
#define    MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8
/* The first 32-bit word read from the GPIO IN register. */
#define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
#define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
/* The second 32-bit word read from the GPIO IN register. */
#define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
#define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4

/* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */
#define    MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0

/* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */
#define    MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8
/* The first 32-bit word read from the GPIO OUT register. */
#define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
#define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
/* The second 32-bit word read from the GPIO OUT register. */
#define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
#define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4

/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */
#define    MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0

/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */
#define    MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8
#define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
#define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
#define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
#define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4

/* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */
#define    MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
#define       MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
#define       MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4

/* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */
#define    MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0

/* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */
#define    MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0

/* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */
#define    MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0

/* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */
#define    MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
#define    MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252
#define    MC_CMD_MUM_OUT_READ_SENSORS_LENMAX_MCDI2 1020
#define    MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
#define    MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
#define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
#define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
#define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
#define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63
#define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM_MCDI2 255
#define        MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0
#define        MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
#define        MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16
#define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0
#define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16
#define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8
#define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0
#define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24
#define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8

/* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */
#define    MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
#define       MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
#define       MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4

/* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */
#define    MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0

/* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */
#define    MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
#define       MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
#define       MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4

/* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */
#define    MC_CMD_MUM_OUT_QSFP_INIT_LEN 0

/* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */
#define    MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8
#define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
#define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
#define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
#define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
#define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4
#define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
#define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
#define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4
#define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
#define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1

/* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */
#define    MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
#define       MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
#define       MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4

/* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */
#define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5
#define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252
#define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX_MCDI2 1020
#define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
#define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
/* in bytes */
#define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
#define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
#define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
#define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
#define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
#define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248
#define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016

/* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */
#define    MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8
#define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
#define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
#define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
#define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4

/* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */
#define    MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
#define       MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
#define       MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4

/* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */
#define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24
#define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248
#define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 1016
#define    MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))
#define    MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)
/* Discrete (soldered) DDR resistor strap info */
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16
/* Number of SODIMM info records */
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
/* Array of SODIMM info records */
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 4
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LBN 64
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_WIDTH 32
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 4
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LBN 96
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_WIDTH 32
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8
/* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
/* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
/* enum: Total number of SODIMM banks */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
/* enum: Values 5-15 are reserved for future usage */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
/* enum: No module present */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
/* enum: Module present supported and powered on */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
/* enum: Module present but bad type */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
/* enum: Module present but incompatible voltage */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
/* enum: Module present but unknown SPD */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
/* enum: Module present but slot cannot support it */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
/* enum: Modules may or may not be present, but cannot establish contact by I2C
 */
#define          MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 8
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52
#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12

/* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This
 * should match the equivalent structure in the sensor_query SPHINX service.
 */
#define    MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 24
/* A value below this will trigger a warning event. */
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 32
/* A value below this will trigger a critical event. */
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 32
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 32
/* A value below this will shut down the card. */
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 8
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 64
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 32
/* A value above this will trigger a warning event. */
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 12
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 96
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 32
/* A value above this will trigger a critical event. */
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 16
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 128
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 32
/* A value above this will shut down the card. */
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 20
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 160
#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 32

/* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor.
 * This should match the equivalent structure in the sensor_query SPHINX
 * service.
 */
#define    MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 64
/* The handle used to identify the sensor in calls to
 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES
 */
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 32
/* A human-readable name for the sensor (zero terminated string, max 32 bytes)
 */
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 32
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 32
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 256
/* The type of the sensor device, and by implication the unit of that the
 * values will be reported in
 */
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 36
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
/* enum: A voltage sensor. Unit is mV */
#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
/* enum: A current sensor. Unit is mA */
#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
/* enum: A power sensor. Unit is mW */
#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
/* enum: A temperature sensor. Unit is Celsius */
#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
/* enum: A cooling fan sensor. Unit is RPM */
#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 288
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 32
/* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 40
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 24
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 320
#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 192

/* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor.
 * This should match the equivalent structure in the sensor_query SPHINX
 * service.
 */
#define    MC_CMD_DYNAMIC_SENSORS_READING_LEN 12
/* The handle used to identify the sensor */
#define       MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
#define       MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
#define       MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 32
/* The current value of the sensor */
#define       MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
#define       MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 32
#define       MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 32
/* The sensor's condition, e.g. good, broken or removed */
#define       MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 8
#define       MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
/* enum: Sensor working normally within limits */
#define          MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
/* enum: Warning threshold breached */
#define          MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
/* enum: Critical threshold breached */
#define          MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
/* enum: Fatal threshold breached */
#define          MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
/* enum: Sensor not working */
#define          MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
/* enum: Sensor working but no reading available */
#define          MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
/* enum: Sensor initialization failed */
#define          MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
#define       MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 64
#define       MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 32


/***********************************/
/* MC_CMD_DYNAMIC_SENSORS_LIST
 * Return a complete list of handles for sensors currently managed by the MC,
 * and a generation count for this version of the sensor table. On systems
 * advertising the DYNAMIC_SENSORS capability bit, this replaces the
 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
 * added by the NMC.
 *
 * Sensor handles are persistent for the lifetime of the sensor and are used to
 * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and
 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES.
 *
 * The generation count is maintained by the MC, is persistent across reboots
 * and will be incremented each time the sensor table is modified. When the
 * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated
 * containing the new generation count. The driver should compare this against
 * the current generation count, and if it is different, call
 * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table.
 *
 * The sensor count is provided to allow a future path to supporting more than
 * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e.
 * the maximum number that will fit in a single response. As this is a fairly
 * large number (253) it is not anticipated that this will be needed in the
 * near future, so can currently be ignored.
 *
 * On Riverhead this command is implemented as a wrapper for `list` in the
 * sensor_query SPHINX service.
 */
#define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
#undef MC_CMD_0x66_PRIVILEGE_CTG

#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_DYNAMIC_SENSORS_LIST_IN msgrequest */
#define    MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0

/* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */
#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 8
#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 252
#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
/* Generation count, which will be updated each time a sensor is added to or
 * removed from the MC sensor table.
 */
#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
/* Number of sensors managed by the MC. Note that in principle, this can be
 * larger than the size of the HANDLES array.
 */
#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
/* Array of sensor handles */
#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 8
#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 61
#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 253


/***********************************/
/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS
 * Get descriptions for a set of sensors, specified as an array of sensor
 * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST
 *
 * Any handles which do not correspond to a sensor currently managed by the MC
 * will be dropped from from the response. This may happen when a sensor table
 * update is in progress, and effectively means the set of usable sensors is
 * the intersection between the sets of sensors known to the driver and the MC.
 *
 * On Riverhead this command is implemented as a wrapper for
 * `get_descriptions` in the sensor_query SPHINX service.
 */
#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
#undef MC_CMD_0x67_PRIVILEGE_CTG

#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN msgrequest */
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX 252
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX_MCDI2 1020
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
/* Array of sensor handles */
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM 63
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM_MCDI2 255

/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT msgresponse */
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX 192
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX_MCDI2 960
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
/* Array of MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structures */
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_LEN 64
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM 3
#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM_MCDI2 15


/***********************************/
/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS
 * Read the state and value for a set of sensors, specified as an array of
 * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST.
 *
 * In the case of a broken sensor, then the state of the response's
 * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value
 * provided should be treated as erroneous.
 *
 * Any handles which do not correspond to a sensor currently managed by the MC
 * will be dropped from from the response. This may happen when a sensor table
 * update is in progress, and effectively means the set of usable sensors is
 * the intersection between the sets of sensors known to the driver and the MC.
 *
 * On Riverhead this command is implemented as a wrapper for `get_readings`
 * in the sensor_query SPHINX service.
 */
#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
#undef MC_CMD_0x68_PRIVILEGE_CTG

#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN msgrequest */
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX 252
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX_MCDI2 1020
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
/* Array of sensor handles */
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM 63
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 255

/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT msgresponse */
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX 252
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX_MCDI2 1020
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
/* Array of MC_CMD_DYNAMIC_SENSORS_READING structures */
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_LEN 12
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 21
#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 85


/***********************************/
/* MC_CMD_EVENT_CTRL
 * Configure which categories of unsolicited events the driver expects to
 * receive (Riverhead).
 */
#define MC_CMD_EVENT_CTRL 0x69
#undef MC_CMD_0x69_PRIVILEGE_CTG

#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL

/* MC_CMD_EVENT_CTRL_IN msgrequest */
#define    MC_CMD_EVENT_CTRL_IN_LENMIN 0
#define    MC_CMD_EVENT_CTRL_IN_LENMAX 252
#define    MC_CMD_EVENT_CTRL_IN_LENMAX_MCDI2 1020
#define    MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
#define    MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
/* Array of event categories for which the driver wishes to receive events. */
#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0
#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4
#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0
#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM 63
#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM_MCDI2 255
/* enum: Driver wishes to receive LINKCHANGE events. */
#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0
/* enum: Driver wishes to receive SENSOR_CHANGE and SENSOR_STATE_CHANGE events.
 */
#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1
/* enum: Driver wishes to receive receive errors. */
#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2
/* enum: Driver wishes to receive transmit errors. */
#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3
/* enum: Driver wishes to receive firmware alerts. */
#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4
/* enum: Driver wishes to receive reboot events. */
#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5

/* MC_CMD_EVENT_CTRL_OUT msgrequest */
#define    MC_CMD_EVENT_CTRL_OUT_LEN 0

/* EVB_PORT_ID structuredef */
#define    EVB_PORT_ID_LEN 4
#define       EVB_PORT_ID_PORT_ID_OFST 0
#define       EVB_PORT_ID_PORT_ID_LEN 4
/* enum: An invalid port handle. */
#define          EVB_PORT_ID_NULL 0x0
/* enum: The port assigned to this function.. */
#define          EVB_PORT_ID_ASSIGNED 0x1000000
/* enum: External network port 0 */
#define          EVB_PORT_ID_MAC0 0x2000000
/* enum: External network port 1 */
#define          EVB_PORT_ID_MAC1 0x2000001
/* enum: External network port 2 */
#define          EVB_PORT_ID_MAC2 0x2000002
/* enum: External network port 3 */
#define          EVB_PORT_ID_MAC3 0x2000003
#define       EVB_PORT_ID_PORT_ID_LBN 0
#define       EVB_PORT_ID_PORT_ID_WIDTH 32

/* EVB_VLAN_TAG structuredef */
#define    EVB_VLAN_TAG_LEN 2
/* The VLAN tag value */
#define       EVB_VLAN_TAG_VLAN_ID_LBN 0
#define       EVB_VLAN_TAG_VLAN_ID_WIDTH 12
#define       EVB_VLAN_TAG_MODE_LBN 12
#define       EVB_VLAN_TAG_MODE_WIDTH 4
/* enum: Insert the VLAN. */
#define          EVB_VLAN_TAG_INSERT 0x0
/* enum: Replace the VLAN if already present. */
#define          EVB_VLAN_TAG_REPLACE 0x1

/* BUFTBL_ENTRY structuredef */
#define    BUFTBL_ENTRY_LEN 12
/* the owner ID */
#define       BUFTBL_ENTRY_OID_OFST 0
#define       BUFTBL_ENTRY_OID_LEN 2
#define       BUFTBL_ENTRY_OID_LBN 0
#define       BUFTBL_ENTRY_OID_WIDTH 16
/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */
#define       BUFTBL_ENTRY_PGSZ_OFST 2
#define       BUFTBL_ENTRY_PGSZ_LEN 2
#define       BUFTBL_ENTRY_PGSZ_LBN 16
#define       BUFTBL_ENTRY_PGSZ_WIDTH 16
/* the raw 64-bit address field from the SMC, not adjusted for page size */
#define       BUFTBL_ENTRY_RAWADDR_OFST 4
#define       BUFTBL_ENTRY_RAWADDR_LEN 8
#define       BUFTBL_ENTRY_RAWADDR_LO_OFST 4
#define       BUFTBL_ENTRY_RAWADDR_LO_LEN 4
#define       BUFTBL_ENTRY_RAWADDR_LO_LBN 32
#define       BUFTBL_ENTRY_RAWADDR_LO_WIDTH 32
#define       BUFTBL_ENTRY_RAWADDR_HI_OFST 8
#define       BUFTBL_ENTRY_RAWADDR_HI_LEN 4
#define       BUFTBL_ENTRY_RAWADDR_HI_LBN 64
#define       BUFTBL_ENTRY_RAWADDR_HI_WIDTH 32
#define       BUFTBL_ENTRY_RAWADDR_LBN 32
#define       BUFTBL_ENTRY_RAWADDR_WIDTH 64

/* NVRAM_PARTITION_TYPE structuredef */
#define    NVRAM_PARTITION_TYPE_LEN 2
#define       NVRAM_PARTITION_TYPE_ID_OFST 0
#define       NVRAM_PARTITION_TYPE_ID_LEN 2
/* enum: Primary MC firmware partition */
#define          NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
/* enum: NMC firmware partition (this is intentionally an alias of MC_FIRMWARE)
 */
#define          NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100
/* enum: Secondary MC firmware partition */
#define          NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
/* enum: Expansion ROM partition */
#define          NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
/* enum: Static configuration TLV partition */
#define          NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
/* enum: Factory configuration TLV partition (this is intentionally an alias of
 * STATIC_CONFIG)
 */
#define          NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400
/* enum: Dynamic configuration TLV partition */
#define          NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
/* enum: User configuration TLV partition (this is intentionally an alias of
 * DYNAMIC_CONFIG)
 */
#define          NVRAM_PARTITION_TYPE_USER_CONFIG 0x500
/* enum: Expansion ROM configuration data for port 0 */
#define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
#define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
/* enum: Expansion ROM configuration data for port 1 */
#define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
/* enum: Expansion ROM configuration data for port 2 */
#define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
/* enum: Expansion ROM configuration data for port 3 */
#define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
/* enum: Non-volatile log output partition */
#define          NVRAM_PARTITION_TYPE_LOG 0x700
/* enum: Non-volatile log output partition for NMC firmware (this is
 * intentionally an alias of LOG)
 */
#define          NVRAM_PARTITION_TYPE_NMC_LOG 0x700
/* enum: Non-volatile log output of second core on dual-core device */
#define          NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
/* enum: Device state dump output partition */
#define          NVRAM_PARTITION_TYPE_DUMP 0x800
/* enum: Crash log partition for NMC firmware */
#define          NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801
/* enum: Application license key storage partition */
#define          NVRAM_PARTITION_TYPE_LICENSE 0x900
/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
#define          NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
#define          NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
/* enum: Primary FPGA partition */
#define          NVRAM_PARTITION_TYPE_FPGA 0xb00
/* enum: Secondary FPGA partition */
#define          NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
/* enum: FC firmware partition */
#define          NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
/* enum: FC License partition */
#define          NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
/* enum: Non-volatile log output partition for FC */
#define          NVRAM_PARTITION_TYPE_FC_LOG 0xb04
/* enum: FPGA Stage 1 bitstream */
#define          NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05
/* enum: FPGA Stage 2 bitstream */
#define          NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06
/* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */
#define          NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07
/* enum: FPGA User XCLBIN (this is intentionally an alias of FPGA_REGION0) */
#define          NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07
/* enum: FPGA jump instruction (a.k.a. boot) partition to select Stage1
 * bitstream
 */
#define          NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08
/* enum: FPGA Validate XCLBIN */
#define          NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09
/* enum: FPGA XOCL Configuration information */
#define          NVRAM_PARTITION_TYPE_FPGA_XOCL_CONFIG 0xb0a
/* enum: MUM firmware partition */
#define          NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
/* enum: SUC firmware partition (this is intentionally an alias of
 * MUM_FIRMWARE)
 */
#define          NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
/* enum: MUM Non-volatile log output partition. */
#define          NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
/* enum: SUC Non-volatile log output partition (this is intentionally an alias
 * of MUM_LOG).
 */
#define          NVRAM_PARTITION_TYPE_SUC_LOG 0xc01
/* enum: MUM Application table partition. */
#define          NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
/* enum: MUM boot rom partition. */
#define          NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
/* enum: MUM production signatures & calibration rom partition. */
#define          NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
/* enum: MUM user signatures & calibration rom partition. */
#define          NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
/* enum: MUM fuses and lockbits partition. */
#define          NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
/* enum: UEFI expansion ROM if separate from PXE */
#define          NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
/* enum: Used by the expansion ROM for logging */
#define          NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
/* enum: Non-volatile log output partition for Expansion ROM (this is
 * intentionally an alias of PXE_LOG).
 */
#define          NVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000
/* enum: Used for XIP code of shmbooted images */
#define          NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
/* enum: Spare partition 2 */
#define          NVRAM_PARTITION_TYPE_SPARE_2 0x1200
/* enum: Manufacturing partition. Used during manufacture to pass information
 * between XJTAG and Manftest.
 */
#define          NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
/* enum: Deployment configuration TLV partition (this is intentionally an alias
 * of MANUFACTURING)
 */
#define          NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300
/* enum: Spare partition 4 */
#define          NVRAM_PARTITION_TYPE_SPARE_4 0x1400
/* enum: Spare partition 5 */
#define          NVRAM_PARTITION_TYPE_SPARE_5 0x1500
/* enum: Partition for reporting MC status. See mc_flash_layout.h
 * medford_mc_status_hdr_t for layout on Medford.
 */
#define          NVRAM_PARTITION_TYPE_STATUS 0x1600
/* enum: Spare partition 13 */
#define          NVRAM_PARTITION_TYPE_SPARE_13 0x1700
/* enum: Spare partition 14 */
#define          NVRAM_PARTITION_TYPE_SPARE_14 0x1800
/* enum: Spare partition 15 */
#define          NVRAM_PARTITION_TYPE_SPARE_15 0x1900
/* enum: Spare partition 16 */
#define          NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
/* enum: Factory defaults for dynamic configuration */
#define          NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
/* enum: Factory defaults for expansion ROM configuration */
#define          NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
/* enum: Field Replaceable Unit inventory information for use on IPMI
 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
 * subset of the information stored in this partition.
 */
#define          NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
/* enum: Bundle image partition */
#define          NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
/* enum: Bundle metadata partition that holds additional information related to
 * a bundle update in TLV format
 */
#define          NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
/* enum: Bundle update non-volatile log output partition */
#define          NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */
#define          NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
/* enum: Partition to store ASN.1 format Bundle Signature for checking. */
#define          NVRAM_PARTITION_TYPE_BUNDLE_SIGNATURE 0x1e04
/* enum: Test partition on SmartNIC system microcontroller (SUC) */
#define          NVRAM_PARTITION_TYPE_SUC_TEST 0x1f00
/* enum: System microcontroller access to primary FPGA flash. */
#define          NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01
/* enum: System microcontroller access to secondary FPGA flash (if present) */
#define          NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02
/* enum: System microcontroller access to primary System-on-Chip flash */
#define          NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03
/* enum: System microcontroller access to secondary System-on-Chip flash (if
 * present)
 */
#define          NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04
/* enum: System microcontroller critical failure logs. Contains structured
 * details of sensors leading up to a critical failure (where the board is shut
 * down).
 */
#define          NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05
/* enum: System-on-Chip configuration information (see XN-200467-PS). */
#define          NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07
/* enum: System-on-Chip update information. */
#define          NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003
/* enum: Start of reserved value range (firmware may use for any purpose) */
#define          NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
/* enum: End of reserved value range (firmware may use for any purpose) */
#define          NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
/* enum: Recovery partition map (provided if real map is missing or corrupt) */
#define          NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
/* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is
 * intentionally an alias of RECOVERY_MAP)
 */
#define          NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe
/* enum: Partition map (real map as stored in flash) */
#define          NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
/* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an
 * alias of PARTITION_MAP)
 */
#define          NVRAM_PARTITION_TYPE_FPT 0xffff
#define       NVRAM_PARTITION_TYPE_ID_LBN 0
#define       NVRAM_PARTITION_TYPE_ID_WIDTH 16

/* LICENSED_APP_ID structuredef */
#define    LICENSED_APP_ID_LEN 4
#define       LICENSED_APP_ID_ID_OFST 0
#define       LICENSED_APP_ID_ID_LEN 4
/* enum: OpenOnload */
#define          LICENSED_APP_ID_ONLOAD 0x1
/* enum: PTP timestamping */
#define          LICENSED_APP_ID_PTP 0x2
/* enum: SolarCapture Pro */
#define          LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
/* enum: SolarSecure filter engine */
#define          LICENSED_APP_ID_SOLARSECURE 0x8
/* enum: Performance monitor */
#define          LICENSED_APP_ID_PERF_MONITOR 0x10
/* enum: SolarCapture Live */
#define          LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
/* enum: Capture SolarSystem */
#define          LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
/* enum: Network Access Control */
#define          LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
/* enum: TCP Direct */
#define          LICENSED_APP_ID_TCP_DIRECT 0x100
/* enum: Low Latency */
#define          LICENSED_APP_ID_LOW_LATENCY 0x200
/* enum: SolarCapture Tap */
#define          LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
/* enum: Capture SolarSystem 40G */
#define          LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
/* enum: Capture SolarSystem 1G */
#define          LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
/* enum: ScaleOut Onload */
#define          LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
/* enum: SCS Network Analytics Dashboard */
#define          LICENSED_APP_ID_DSHBRD 0x4000
/* enum: SolarCapture Trading Analytics */
#define          LICENSED_APP_ID_SCATRD 0x8000
#define       LICENSED_APP_ID_ID_LBN 0
#define       LICENSED_APP_ID_ID_WIDTH 32

/* LICENSED_FEATURES structuredef */
#define    LICENSED_FEATURES_LEN 8
/* Bitmask of licensed firmware features */
#define       LICENSED_FEATURES_MASK_OFST 0
#define       LICENSED_FEATURES_MASK_LEN 8
#define       LICENSED_FEATURES_MASK_LO_OFST 0
#define       LICENSED_FEATURES_MASK_LO_LEN 4
#define       LICENSED_FEATURES_MASK_LO_LBN 0
#define       LICENSED_FEATURES_MASK_LO_WIDTH 32
#define       LICENSED_FEATURES_MASK_HI_OFST 4
#define       LICENSED_FEATURES_MASK_HI_LEN 4
#define       LICENSED_FEATURES_MASK_HI_LBN 32
#define       LICENSED_FEATURES_MASK_HI_WIDTH 32
#define        LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
#define        LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
#define        LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
#define        LICENSED_FEATURES_PIO_OFST 0
#define        LICENSED_FEATURES_PIO_LBN 1
#define        LICENSED_FEATURES_PIO_WIDTH 1
#define        LICENSED_FEATURES_EVQ_TIMER_OFST 0
#define        LICENSED_FEATURES_EVQ_TIMER_LBN 2
#define        LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
#define        LICENSED_FEATURES_CLOCK_OFST 0
#define        LICENSED_FEATURES_CLOCK_LBN 3
#define        LICENSED_FEATURES_CLOCK_WIDTH 1
#define        LICENSED_FEATURES_RX_TIMESTAMPS_OFST 0
#define        LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
#define        LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
#define        LICENSED_FEATURES_TX_TIMESTAMPS_OFST 0
#define        LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5
#define        LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
#define        LICENSED_FEATURES_RX_SNIFF_OFST 0
#define        LICENSED_FEATURES_RX_SNIFF_LBN 6
#define        LICENSED_FEATURES_RX_SNIFF_WIDTH 1
#define        LICENSED_FEATURES_TX_SNIFF_OFST 0
#define        LICENSED_FEATURES_TX_SNIFF_LBN 7
#define        LICENSED_FEATURES_TX_SNIFF_WIDTH 1
#define        LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0
#define        LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8
#define        LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
#define        LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0
#define        LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9
#define        LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
#define       LICENSED_FEATURES_MASK_LBN 0
#define       LICENSED_FEATURES_MASK_WIDTH 64

/* LICENSED_V3_APPS structuredef */
#define    LICENSED_V3_APPS_LEN 8
/* Bitmask of licensed applications */
#define       LICENSED_V3_APPS_MASK_OFST 0
#define       LICENSED_V3_APPS_MASK_LEN 8
#define       LICENSED_V3_APPS_MASK_LO_OFST 0
#define       LICENSED_V3_APPS_MASK_LO_LEN 4
#define       LICENSED_V3_APPS_MASK_LO_LBN 0
#define       LICENSED_V3_APPS_MASK_LO_WIDTH 32
#define       LICENSED_V3_APPS_MASK_HI_OFST 4
#define       LICENSED_V3_APPS_MASK_HI_LEN 4
#define       LICENSED_V3_APPS_MASK_HI_LBN 32
#define       LICENSED_V3_APPS_MASK_HI_WIDTH 32
#define        LICENSED_V3_APPS_ONLOAD_OFST 0
#define        LICENSED_V3_APPS_ONLOAD_LBN 0
#define        LICENSED_V3_APPS_ONLOAD_WIDTH 1
#define        LICENSED_V3_APPS_PTP_OFST 0
#define        LICENSED_V3_APPS_PTP_LBN 1
#define        LICENSED_V3_APPS_PTP_WIDTH 1
#define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0
#define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2
#define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
#define        LICENSED_V3_APPS_SOLARSECURE_OFST 0
#define        LICENSED_V3_APPS_SOLARSECURE_LBN 3
#define        LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
#define        LICENSED_V3_APPS_PERF_MONITOR_OFST 0
#define        LICENSED_V3_APPS_PERF_MONITOR_LBN 4
#define        LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
#define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0
#define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5
#define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0
#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6
#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
#define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0
#define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7
#define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
#define        LICENSED_V3_APPS_TCP_DIRECT_OFST 0
#define        LICENSED_V3_APPS_TCP_DIRECT_LBN 8
#define        LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
#define        LICENSED_V3_APPS_LOW_LATENCY_OFST 0
#define        LICENSED_V3_APPS_LOW_LATENCY_LBN 9
#define        LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
#define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0
#define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10
#define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0
#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11
#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1
#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0
#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12
#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1
#define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0
#define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13
#define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1
#define        LICENSED_V3_APPS_DSHBRD_OFST 0
#define        LICENSED_V3_APPS_DSHBRD_LBN 14
#define        LICENSED_V3_APPS_DSHBRD_WIDTH 1
#define        LICENSED_V3_APPS_SCATRD_OFST 0
#define        LICENSED_V3_APPS_SCATRD_LBN 15
#define        LICENSED_V3_APPS_SCATRD_WIDTH 1
#define       LICENSED_V3_APPS_MASK_LBN 0
#define       LICENSED_V3_APPS_MASK_WIDTH 64

/* LICENSED_V3_FEATURES structuredef */
#define    LICENSED_V3_FEATURES_LEN 8
/* Bitmask of licensed firmware features */
#define       LICENSED_V3_FEATURES_MASK_OFST 0
#define       LICENSED_V3_FEATURES_MASK_LEN 8
#define       LICENSED_V3_FEATURES_MASK_LO_OFST 0
#define       LICENSED_V3_FEATURES_MASK_LO_LEN 4
#define       LICENSED_V3_FEATURES_MASK_LO_LBN 0
#define       LICENSED_V3_FEATURES_MASK_LO_WIDTH 32
#define       LICENSED_V3_FEATURES_MASK_HI_OFST 4
#define       LICENSED_V3_FEATURES_MASK_HI_LEN 4
#define       LICENSED_V3_FEATURES_MASK_HI_LBN 32
#define       LICENSED_V3_FEATURES_MASK_HI_WIDTH 32
#define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
#define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
#define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
#define        LICENSED_V3_FEATURES_PIO_OFST 0
#define        LICENSED_V3_FEATURES_PIO_LBN 1
#define        LICENSED_V3_FEATURES_PIO_WIDTH 1
#define        LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0
#define        LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2
#define        LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
#define        LICENSED_V3_FEATURES_CLOCK_OFST 0
#define        LICENSED_V3_FEATURES_CLOCK_LBN 3
#define        LICENSED_V3_FEATURES_CLOCK_WIDTH 1
#define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0
#define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
#define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
#define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0
#define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5
#define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
#define        LICENSED_V3_FEATURES_RX_SNIFF_OFST 0
#define        LICENSED_V3_FEATURES_RX_SNIFF_LBN 6
#define        LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
#define        LICENSED_V3_FEATURES_TX_SNIFF_OFST 0
#define        LICENSED_V3_FEATURES_TX_SNIFF_LBN 7
#define        LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
#define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0
#define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8
#define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
#define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0
#define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9
#define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
#define       LICENSED_V3_FEATURES_MASK_LBN 0
#define       LICENSED_V3_FEATURES_MASK_WIDTH 64

/* TX_TIMESTAMP_EVENT structuredef */
#define    TX_TIMESTAMP_EVENT_LEN 6
/* lower 16 bits of timestamp data */
#define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
#define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2
#define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
#define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16
/* Type of TX event, ordinary TX completion, low or high part of TX timestamp
 */
#define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3
#define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
/* enum: This is a TX completion event, not a timestamp */
#define          TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
/* enum: This is a TX completion event for a CTPIO transmit. The event format
 * is the same as for TX_EV_COMPLETION.
 */
#define          TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
/* enum: This is the low part of a TX timestamp for a CTPIO transmission. The
 * event format is the same as for TX_EV_TSTAMP_LO
 */
#define          TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
/* enum: This is the high part of a TX timestamp for a CTPIO transmission. The
 * event format is the same as for TX_EV_TSTAMP_HI
 */
#define          TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
/* enum: This is the low part of a TX timestamp event */
#define          TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
/* enum: This is the high part of a TX timestamp event */
#define          TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
#define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24
#define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8
/* upper 16 bits of timestamp data */
#define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
#define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2
#define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32
#define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16

/* RSS_MODE structuredef */
#define    RSS_MODE_LEN 1
/* The RSS mode for a particular packet type is a value from 0 - 15 which can
 * be considered as 4 bits selecting which fields are included in the hash. (A
 * value 0 effectively disables RSS spreading for the packet type.) The YAML
 * generation tools require this structure to be a whole number of bytes wide,
 * but only 4 bits are relevant.
 */
#define       RSS_MODE_HASH_SELECTOR_OFST 0
#define       RSS_MODE_HASH_SELECTOR_LEN 1
#define        RSS_MODE_HASH_SRC_ADDR_OFST 0
#define        RSS_MODE_HASH_SRC_ADDR_LBN 0
#define        RSS_MODE_HASH_SRC_ADDR_WIDTH 1
#define        RSS_MODE_HASH_DST_ADDR_OFST 0
#define        RSS_MODE_HASH_DST_ADDR_LBN 1
#define        RSS_MODE_HASH_DST_ADDR_WIDTH 1
#define        RSS_MODE_HASH_SRC_PORT_OFST 0
#define        RSS_MODE_HASH_SRC_PORT_LBN 2
#define        RSS_MODE_HASH_SRC_PORT_WIDTH 1
#define        RSS_MODE_HASH_DST_PORT_OFST 0
#define        RSS_MODE_HASH_DST_PORT_LBN 3
#define        RSS_MODE_HASH_DST_PORT_WIDTH 1
#define       RSS_MODE_HASH_SELECTOR_LBN 0
#define       RSS_MODE_HASH_SELECTOR_WIDTH 8

/* CTPIO_STATS_MAP structuredef */
#define    CTPIO_STATS_MAP_LEN 4
/* The (function relative) VI number */
#define       CTPIO_STATS_MAP_VI_OFST 0
#define       CTPIO_STATS_MAP_VI_LEN 2
#define       CTPIO_STATS_MAP_VI_LBN 0
#define       CTPIO_STATS_MAP_VI_WIDTH 16
/* The target bucket for the VI */
#define       CTPIO_STATS_MAP_BUCKET_OFST 2
#define       CTPIO_STATS_MAP_BUCKET_LEN 2
#define       CTPIO_STATS_MAP_BUCKET_LBN 16
#define       CTPIO_STATS_MAP_BUCKET_WIDTH 16


/***********************************/
/* MC_CMD_READ_REGS
 * Get a dump of the MCPU registers
 */
#define