#ifndef ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_
#define ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_
#define mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ 0x5418100
#define mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK 0x5418104
#define mmNIC0_QM_ARC_AUX0_RST_VEC_ADDR 0x5418108
#define mmNIC0_QM_ARC_AUX0_DBG_MODE 0x541810C
#define mmNIC0_QM_ARC_AUX0_CLUSTER_NUM 0x5418110
#define mmNIC0_QM_ARC_AUX0_ARC_NUM 0x5418114
#define mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT 0x5418118
#define mmNIC0_QM_ARC_AUX0_DCCM_SYS_ADDR_BASE 0x541811C
#define mmNIC0_QM_ARC_AUX0_CTI_AP_STS 0x5418120
#define mmNIC0_QM_ARC_AUX0_CTI_CFG_MUX_SEL 0x5418124
#define mmNIC0_QM_ARC_AUX0_ARC_RST 0x5418128
#define mmNIC0_QM_ARC_AUX0_ARC_RST_REQ 0x541812C
#define mmNIC0_QM_ARC_AUX0_SRAM_LSB_ADDR 0x5418130
#define mmNIC0_QM_ARC_AUX0_SRAM_MSB_ADDR 0x5418134
#define mmNIC0_QM_ARC_AUX0_PCIE_LSB_ADDR 0x5418138
#define mmNIC0_QM_ARC_AUX0_PCIE_MSB_ADDR 0x541813C
#define mmNIC0_QM_ARC_AUX0_CFG_LSB_ADDR 0x5418140
#define mmNIC0_QM_ARC_AUX0_CFG_MSB_ADDR 0x5418144
#define mmNIC0_QM_ARC_AUX0_HBM0_LSB_ADDR 0x5418150
#define mmNIC0_QM_ARC_AUX0_HBM0_MSB_ADDR 0x5418154
#define mmNIC0_QM_ARC_AUX0_HBM1_LSB_ADDR 0x5418158
#define mmNIC0_QM_ARC_AUX0_HBM1_MSB_ADDR 0x541815C
#define mmNIC0_QM_ARC_AUX0_HBM2_LSB_ADDR 0x5418160
#define mmNIC0_QM_ARC_AUX0_HBM2_MSB_ADDR 0x5418164
#define mmNIC0_QM_ARC_AUX0_HBM3_LSB_ADDR 0x5418168
#define mmNIC0_QM_ARC_AUX0_HBM3_MSB_ADDR 0x541816C
#define mmNIC0_QM_ARC_AUX0_HBM0_OFFSET 0x5418170
#define mmNIC0_QM_ARC_AUX0_HBM1_OFFSET 0x5418174
#define mmNIC0_QM_ARC_AUX0_HBM2_OFFSET 0x5418178
#define mmNIC0_QM_ARC_AUX0_HBM3_OFFSET 0x541817C
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_0 0x5418180
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_1 0x5418184
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_2 0x5418188
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_3 0x541818C
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_4 0x5418190
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_5 0x5418194
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_6 0x5418198
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_0 0x541819C
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_1 0x54181A0
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_2 0x54181A4
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_3 0x54181A8
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_4 0x54181AC
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_5 0x54181B0
#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_6 0x54181B4
#define mmNIC0_QM_ARC_AUX0_ARC_CBU_AWCACHE_OVR 0x54181B8
#define mmNIC0_QM_ARC_AUX0_ARC_LBU_AWCACHE_OVR 0x54181BC
#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_0 0x54181C0
#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_1 0x54181C4
#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_2 0x54181C8
#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_3 0x54181CC
#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_4 0x54181D0
#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_5 0x54181D4
#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_6 0x54181D8
#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_7 0x54181DC
#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_0 0x54181E0
#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_1 0x54181E4
#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_2 0x54181E8
#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_3 0x54181EC
#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_4 0x54181F0
#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_5 0x54181F4
#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_6 0x54181F8
#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_7 0x54181FC
#define mmNIC0_QM_ARC_AUX0_SW_INTR_0 0x5418200
#define mmNIC0_QM_ARC_AUX0_SW_INTR_1 0x5418204
#define mmNIC0_QM_ARC_AUX0_SW_INTR_2 0x5418208
#define mmNIC0_QM_ARC_AUX0_SW_INTR_3 0x541820C
#define mmNIC0_QM_ARC_AUX0_SW_INTR_4 0x5418210
#define mmNIC0_QM_ARC_AUX0_SW_INTR_5 0x5418214
#define mmNIC0_QM_ARC_AUX0_SW_INTR_6 0x5418218
#define mmNIC0_QM_ARC_AUX0_SW_INTR_7 0x541821C
#define mmNIC0_QM_ARC_AUX0_SW_INTR_8 0x5418220
#define mmNIC0_QM_ARC_AUX0_SW_INTR_9 0x5418224
#define mmNIC0_QM_ARC_AUX0_SW_INTR_10 0x5418228
#define mmNIC0_QM_ARC_AUX0_SW_INTR_11 0x541822C
#define mmNIC0_QM_ARC_AUX0_SW_INTR_12 0x5418230
#define mmNIC0_QM_ARC_AUX0_SW_INTR_13 0x5418234
#define mmNIC0_QM_ARC_AUX0_SW_INTR_14 0x5418238
#define mmNIC0_QM_ARC_AUX0_SW_INTR_15 0x541823C
#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_0 0x5418280
#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_1 0x5418284
#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_STS 0x5418290
#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_CLR 0x5418294
#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_MASK 0x5418298
#define mmNIC0_QM_ARC_AUX0_ARC_EXCPTN_CAUSE 0x541829C
#define mmNIC0_QM_ARC_AUX0_SEI_INTR_HALT_EN 0x54182A0
#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_HALT_MASK 0x54182A4
#define mmNIC0_QM_ARC_AUX0_QMAN_SEI_INTR_HALT_MASK 0x54182A8
#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_STS 0x54182B0
#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_CLR 0x54182B4
#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_MASK 0x54182B8
#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_ERR_ADDR 0x54182BC
#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_SYNDROME 0x54182C0
#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_ERR_ADDR 0x54182C4
#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_SYNDROME 0x54182C8
#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_ERR_ADDR 0x54182CC
#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_SYNDROME 0x54182D0
#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_AWADDR_ERR 0x54182E0
#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_ARADDR_ERR 0x54182E4
#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_BRESP 0x54182E8
#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_RRESP 0x54182EC
#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXLEN 0x54182F0
#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXSIZE 0x54182F4
#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0 0x5418300
#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_1 0x5418304
#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_2 0x5418308
#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_3 0x541830C
#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_4 0x5418310
#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_5 0x5418314
#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_6 0x5418318
#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_7 0x541831C
#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_WR_CNT 0x5418320
#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_WR_CNT 0x5418324
#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_RD_CNT 0x5418328
#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_RD_CNT 0x541832C
#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_WR_CNT 0x5418330
#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_WR_CNT 0x5418334
#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_RD_CNT 0x5418338
#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT 0x541833C
#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR 0x5418350
#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR_EN 0x5418354
#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR 0x5418358
#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR_EN 0x541835C
#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR 0x5418360
#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR_EN 0x5418364
#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR 0x5418368
#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR_EN 0x541836C
#define mmNIC0_QM_ARC_AUX0_CBU_AXCACHE_OVR 0x5418370
#define mmNIC0_QM_ARC_AUX0_CBU_LOCK_OVR 0x5418374
#define mmNIC0_QM_ARC_AUX0_CBU_PROT_OVR 0x5418378
#define mmNIC0_QM_ARC_AUX0_CBU_MAX_OUTSTANDING 0x541837C
#define mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN 0x5418380
#define mmNIC0_QM_ARC_AUX0_CBU_FORCE_RSP_OK 0x5418384
#define mmNIC0_QM_ARC_AUX0_CBU_NO_WR_INFLIGHT 0x541838C
#define mmNIC0_QM_ARC_AUX0_CBU_SEI_INTR_ID 0x5418390
#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR 0x5418400
#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR_EN 0x5418404
#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR 0x5418408
#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR_EN 0x541840C
#define mmNIC0_QM_ARC_AUX0_LBU_AXCACHE_OVR 0x5418420
#define mmNIC0_QM_ARC_AUX0_LBU_LOCK_OVR 0x5418424
#define mmNIC0_QM_ARC_AUX0_LBU_PROT_OVR 0x5418428
#define mmNIC0_QM_ARC_AUX0_LBU_MAX_OUTSTANDING 0x541842C
#define mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN 0x5418430
#define mmNIC0_QM_ARC_AUX0_LBU_FORCE_RSP_OK 0x5418434
#define mmNIC0_QM_ARC_AUX0_LBU_NO_WR_INFLIGHT 0x541843C
#define mmNIC0_QM_ARC_AUX0_LBU_SEI_INTR_ID 0x5418440
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0 0x5418500
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_1 0x5418504
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_2 0x5418508
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_3 0x541850C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_4 0x5418510
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_5 0x5418514
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_6 0x5418518
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_7 0x541851C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_0 0x5418520
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_1 0x5418524
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_2 0x5418528
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_3 0x541852C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_4 0x5418530
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_5 0x5418534
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_6 0x5418538
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_7 0x541853C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_0 0x5418540
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_1 0x5418544
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_2 0x5418548
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_3 0x541854C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_4 0x5418550
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_5 0x5418554
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_6 0x5418558
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_7 0x541855C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_0 0x5418560
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_1 0x5418564
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_2 0x5418568
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_3 0x541856C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_4 0x5418570
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_5 0x5418574
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_6 0x5418578
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_7 0x541857C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_0 0x5418580
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_1 0x5418584
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_2 0x5418588
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_3 0x541858C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_4 0x5418590
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_5 0x5418594
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_6 0x5418598
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_7 0x541859C
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_0 0x54185A0
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_1 0x54185A4
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_2 0x54185A8
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_3 0x54185AC
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_4 0x54185B0
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_5 0x54185B4
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_6 0x54185B8
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_7 0x54185BC
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_0 0x54185C0
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_1 0x54185C4
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_2 0x54185C8
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_3 0x54185CC
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_4 0x54185D0
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_5 0x54185D4
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_6 0x54185D8
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_7 0x54185DC
#define mmNIC0_QM_ARC_AUX0_GENERAL_Q_VLD_ENTRY_MASK 0x54185E0
#define mmNIC0_QM_ARC_AUX0_NIC_Q_VLD_ENTRY_MASK 0x54185E4
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_DROP_EN 0x5418620
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_WARN_MSG 0x5418624
#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG 0x5418628
#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWPROT 0x5418630
#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWUSER 0x5418634
#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWBURST 0x5418638
#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWLOCK 0x541863C
#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWCACHE 0x5418640
#define mmNIC0_QM_ARC_AUX0_DCCM_WRR_ARB_WEIGHT 0x5418644
#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_FULL_CFG 0x5418648
#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT 0x541864C
#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_IFIFO_SHADOW_CI 0x5418650
#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x5418654
#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_SHADOW_CI 0x5418658
#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI 0x541865C
#define mmNIC0_QM_ARC_AUX0_AUX2APB_PROT 0x5418700
#define mmNIC0_QM_ARC_AUX0_LBW_FORK_WIN_EN 0x5418704
#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR0 0x5418708
#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK0 0x541870C
#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR1 0x5418710
#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK1 0x5418714
#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR0 0x5418718
#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK0 0x541871C
#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR1 0x5418720
#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK1 0x5418724
#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR0 0x5418728
#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR1 0x541872C
#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_LBW_FORK_MASK 0x5418730
#define mmNIC0_QM_ARC_AUX0_ARC_DUP_ENG_LBW_FORK_ADDR 0x5418734
#define mmNIC0_QM_ARC_AUX0_ARC_ACP_ENG_LBW_FORK_ADDR 0x5418738
#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_VIRTUAL_ADDR 0x541873C
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_WIN_EN 0x5418740
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_LSB 0x5418750
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_MSB 0x5418754
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_LSB 0x5418758
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_MSB 0x541875C
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_LSB 0x5418760
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_MSB 0x5418764
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_LSB 0x5418768
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_MSB 0x541876C
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_LSB 0x5418770
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_MSB 0x5418774
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_LSB 0x5418778
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_MSB 0x541877C
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_LSB 0x5418780
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_MSB 0x5418784
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_LSB 0x5418788
#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_MSB 0x541878C
#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_LSB 0x5418790
#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_MSB 0x5418794
#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_BRESP 0x5418798
#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_RRESP 0x541879C
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_0 0x5418800
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_1 0x5418804
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_2 0x5418808
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_3 0x541880C
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_4 0x5418810
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_5 0x5418814
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_6 0x5418818
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_7 0x541881C
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_8 0x5418820
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_9 0x5418824
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_10 0x5418828
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_11 0x541882C
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_12 0x5418830
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_13 0x5418834
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_14 0x5418838
#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_15 0x541883C
#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_AWADDR_ERR 0x5418840
#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_ARADDR_ERR 0x5418844
#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_BRESP 0x5418848
#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_RRESP 0x541884C
#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_EN 0x5418850
#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_SECURE_REGION 0x5418854
#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT 0x5418900
#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_CTL 0x5418904
#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR_MSK 0x5418908
#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR 0x541890C
#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_BUSER 0x5418910
#define mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN 0x5418920
#endif /* ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_ */