#ifndef ASIC_REG_DCORE0_TPC0_QM_REGS_H_
#define ASIC_REG_DCORE0_TPC0_QM_REGS_H_
#define mmDCORE0_TPC0_QM_GLBL_CFG0 0x400A000
#define mmDCORE0_TPC0_QM_GLBL_CFG1 0x400A004
#define mmDCORE0_TPC0_QM_GLBL_CFG2 0x400A008
#define mmDCORE0_TPC0_QM_GLBL_ERR_CFG 0x400A00C
#define mmDCORE0_TPC0_QM_GLBL_ERR_CFG1 0x400A010
#define mmDCORE0_TPC0_QM_GLBL_ERR_ARC_HALT_EN 0x400A014
#define mmDCORE0_TPC0_QM_GLBL_AXCACHE 0x400A018
#define mmDCORE0_TPC0_QM_GLBL_STS0 0x400A01C
#define mmDCORE0_TPC0_QM_GLBL_STS1 0x400A020
#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_0 0x400A024
#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_1 0x400A028
#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_2 0x400A02C
#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_3 0x400A030
#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_4 0x400A034
#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_0 0x400A038
#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_1 0x400A03C
#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_2 0x400A040
#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_3 0x400A044
#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_4 0x400A048
#define mmDCORE0_TPC0_QM_GLBL_PROT 0x400A04C
#define mmDCORE0_TPC0_QM_PQ_BASE_LO_0 0x400A050
#define mmDCORE0_TPC0_QM_PQ_BASE_LO_1 0x400A054
#define mmDCORE0_TPC0_QM_PQ_BASE_LO_2 0x400A058
#define mmDCORE0_TPC0_QM_PQ_BASE_LO_3 0x400A05C
#define mmDCORE0_TPC0_QM_PQ_BASE_HI_0 0x400A060
#define mmDCORE0_TPC0_QM_PQ_BASE_HI_1 0x400A064
#define mmDCORE0_TPC0_QM_PQ_BASE_HI_2 0x400A068
#define mmDCORE0_TPC0_QM_PQ_BASE_HI_3 0x400A06C
#define mmDCORE0_TPC0_QM_PQ_SIZE_0 0x400A070
#define mmDCORE0_TPC0_QM_PQ_SIZE_1 0x400A074
#define mmDCORE0_TPC0_QM_PQ_SIZE_2 0x400A078
#define mmDCORE0_TPC0_QM_PQ_SIZE_3 0x400A07C
#define mmDCORE0_TPC0_QM_PQ_PI_0 0x400A080
#define mmDCORE0_TPC0_QM_PQ_PI_1 0x400A084
#define mmDCORE0_TPC0_QM_PQ_PI_2 0x400A088
#define mmDCORE0_TPC0_QM_PQ_PI_3 0x400A08C
#define mmDCORE0_TPC0_QM_PQ_CI_0 0x400A090
#define mmDCORE0_TPC0_QM_PQ_CI_1 0x400A094
#define mmDCORE0_TPC0_QM_PQ_CI_2 0x400A098
#define mmDCORE0_TPC0_QM_PQ_CI_3 0x400A09C
#define mmDCORE0_TPC0_QM_PQ_CFG0_0 0x400A0A0
#define mmDCORE0_TPC0_QM_PQ_CFG0_1 0x400A0A4
#define mmDCORE0_TPC0_QM_PQ_CFG0_2 0x400A0A8
#define mmDCORE0_TPC0_QM_PQ_CFG0_3 0x400A0AC
#define mmDCORE0_TPC0_QM_PQ_CFG1_0 0x400A0B0
#define mmDCORE0_TPC0_QM_PQ_CFG1_1 0x400A0B4
#define mmDCORE0_TPC0_QM_PQ_CFG1_2 0x400A0B8
#define mmDCORE0_TPC0_QM_PQ_CFG1_3 0x400A0BC
#define mmDCORE0_TPC0_QM_PQ_STS0_0 0x400A0C0
#define mmDCORE0_TPC0_QM_PQ_STS0_1 0x400A0C4
#define mmDCORE0_TPC0_QM_PQ_STS0_2 0x400A0C8
#define mmDCORE0_TPC0_QM_PQ_STS0_3 0x400A0CC
#define mmDCORE0_TPC0_QM_PQ_STS1_0 0x400A0D0
#define mmDCORE0_TPC0_QM_PQ_STS1_1 0x400A0D4
#define mmDCORE0_TPC0_QM_PQ_STS1_2 0x400A0D8
#define mmDCORE0_TPC0_QM_PQ_STS1_3 0x400A0DC
#define mmDCORE0_TPC0_QM_CQ_CFG0_0 0x400A0E0
#define mmDCORE0_TPC0_QM_CQ_CFG0_1 0x400A0E4
#define mmDCORE0_TPC0_QM_CQ_CFG0_2 0x400A0E8
#define mmDCORE0_TPC0_QM_CQ_CFG0_3 0x400A0EC
#define mmDCORE0_TPC0_QM_CQ_CFG0_4 0x400A0F0
#define mmDCORE0_TPC0_QM_CQ_STS0_0 0x400A0F4
#define mmDCORE0_TPC0_QM_CQ_STS0_1 0x400A0F8
#define mmDCORE0_TPC0_QM_CQ_STS0_2 0x400A0FC
#define mmDCORE0_TPC0_QM_CQ_STS0_3 0x400A100
#define mmDCORE0_TPC0_QM_CQ_STS0_4 0x400A104
#define mmDCORE0_TPC0_QM_CQ_CFG1_0 0x400A108
#define mmDCORE0_TPC0_QM_CQ_CFG1_1 0x400A10C
#define mmDCORE0_TPC0_QM_CQ_CFG1_2 0x400A110
#define mmDCORE0_TPC0_QM_CQ_CFG1_3 0x400A114
#define mmDCORE0_TPC0_QM_CQ_CFG1_4 0x400A118
#define mmDCORE0_TPC0_QM_CQ_STS1_0 0x400A11C
#define mmDCORE0_TPC0_QM_CQ_STS1_1 0x400A120
#define mmDCORE0_TPC0_QM_CQ_STS1_2 0x400A124
#define mmDCORE0_TPC0_QM_CQ_STS1_3 0x400A128
#define mmDCORE0_TPC0_QM_CQ_STS1_4 0x400A12C
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_0 0x400A150
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_0 0x400A154
#define mmDCORE0_TPC0_QM_CQ_TSIZE_0 0x400A158
#define mmDCORE0_TPC0_QM_CQ_CTL_0 0x400A15C
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_1 0x400A160
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_1 0x400A164
#define mmDCORE0_TPC0_QM_CQ_TSIZE_1 0x400A168
#define mmDCORE0_TPC0_QM_CQ_CTL_1 0x400A16C
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_2 0x400A170
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_2 0x400A174
#define mmDCORE0_TPC0_QM_CQ_TSIZE_2 0x400A178
#define mmDCORE0_TPC0_QM_CQ_CTL_2 0x400A17C
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_3 0x400A180
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_3 0x400A184
#define mmDCORE0_TPC0_QM_CQ_TSIZE_3 0x400A188
#define mmDCORE0_TPC0_QM_CQ_CTL_3 0x400A18C
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_4 0x400A190
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_4 0x400A194
#define mmDCORE0_TPC0_QM_CQ_TSIZE_4 0x400A198
#define mmDCORE0_TPC0_QM_CQ_CTL_4 0x400A19C
#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_0 0x400A1A0
#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_1 0x400A1A4
#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_2 0x400A1A8
#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_3 0x400A1AC
#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_4 0x400A1B0
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_0 0x400A1B4
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_1 0x400A1B8
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_2 0x400A1BC
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_3 0x400A1C0
#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_4 0x400A1C4
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_0 0x400A1C8
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_1 0x400A1CC
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_2 0x400A1D0
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_3 0x400A1D4
#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_4 0x400A1D8
#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_0 0x400A1DC
#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_1 0x400A1E0
#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_2 0x400A1E4
#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_3 0x400A1E8
#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_4 0x400A1EC
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0x400A1F0
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0x400A1F4
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0x400A1F8
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0x400A1FC
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0x400A200
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0x400A204
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0x400A208
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0x400A20C
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0x400A210
#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0x400A214
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0x400A218
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0x400A21C
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0x400A220
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0x400A224
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0x400A228
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0x400A22C
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0x400A230
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0x400A234
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0x400A238
#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0x400A23C
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0x400A240
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0x400A244
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0x400A248
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0x400A24C
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0x400A250
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0x400A254
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0x400A258
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0x400A25C
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0x400A260
#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0x400A264
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0x400A268
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0x400A26C
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0x400A270
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0x400A274
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0x400A278
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0x400A27C
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0x400A280
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0x400A284
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0x400A288
#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0x400A28C
#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0 0x400A290
#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1 0x400A294
#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2 0x400A298
#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3 0x400A29C
#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4 0x400A2A0
#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0 0x400A2A4
#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1 0x400A2A8
#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2 0x400A2AC
#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3 0x400A2B0
#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4 0x400A2B4
#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0 0x400A2B8
#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1 0x400A2BC
#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2 0x400A2C0
#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3 0x400A2C4
#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4 0x400A2C8
#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0 0x400A2CC
#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1 0x400A2D0
#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2 0x400A2D4
#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3 0x400A2D8
#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4 0x400A2DC
#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0 0x400A2E0
#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1 0x400A2E4
#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2 0x400A2E8
#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3 0x400A2EC
#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4 0x400A2F0
#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0 0x400A2F4
#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1 0x400A2F8
#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2 0x400A2FC
#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3 0x400A300
#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4 0x400A304
#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0 0x400A308
#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1 0x400A30C
#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2 0x400A310
#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3 0x400A314
#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4 0x400A318
#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0 0x400A31C
#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1 0x400A320
#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2 0x400A324
#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3 0x400A328
#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4 0x400A32C
#define mmDCORE0_TPC0_QM_CP_BARRIER_CFG 0x400A330
#define mmDCORE0_TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x400A334
#define mmDCORE0_TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x400A338
#define mmDCORE0_TPC0_QM_CP_LDMA_TSIZE_OFFSET 0x400A33C
#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_0 0x400A340
#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_1 0x400A344
#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_2 0x400A348
#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_3 0x400A34C
#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_4 0x400A350
#define mmDCORE0_TPC0_QM_CP_STS_0 0x400A368
#define mmDCORE0_TPC0_QM_CP_STS_1 0x400A36C
#define mmDCORE0_TPC0_QM_CP_STS_2 0x400A370
#define mmDCORE0_TPC0_QM_CP_STS_3 0x400A374
#define mmDCORE0_TPC0_QM_CP_STS_4 0x400A378
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_0 0x400A37C
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_1 0x400A380
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_2 0x400A384
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_3 0x400A388
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_4 0x400A38C
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_0 0x400A390
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_1 0x400A394
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_2 0x400A398
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_3 0x400A39C
#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_4 0x400A3A0
#define mmDCORE0_TPC0_QM_CP_PRED_0 0x400A3A4
#define mmDCORE0_TPC0_QM_CP_PRED_1 0x400A3A8
#define mmDCORE0_TPC0_QM_CP_PRED_2 0x400A3AC
#define mmDCORE0_TPC0_QM_CP_PRED_3 0x400A3B0
#define mmDCORE0_TPC0_QM_CP_PRED_4 0x400A3B4
#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_0 0x400A3B8
#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_1 0x400A3BC
#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_2 0x400A3C0
#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_3 0x400A3C4
#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_4 0x400A3C8
#define mmDCORE0_TPC0_QM_CP_DBG_0_0 0x400A3CC
#define mmDCORE0_TPC0_QM_CP_DBG_0_1 0x400A3D0
#define mmDCORE0_TPC0_QM_CP_DBG_0_2 0x400A3D4
#define mmDCORE0_TPC0_QM_CP_DBG_0_3 0x400A3D8
#define mmDCORE0_TPC0_QM_CP_DBG_0_4 0x400A3DC
#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_0 0x400A3E0
#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_1 0x400A3E4
#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_2 0x400A3E8
#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_3 0x400A3EC
#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_4 0x400A3F0
#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_0 0x400A3F4
#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_1 0x400A3F8
#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_2 0x400A3FC
#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_3 0x400A400
#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_4 0x400A404
#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_0 0x400A408
#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_1 0x400A40C
#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_2 0x400A410
#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_3 0x400A414
#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_4 0x400A418
#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_0 0x400A41C
#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_1 0x400A420
#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_2 0x400A424
#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_3 0x400A428
#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_0 0x400A42C
#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_1 0x400A430
#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_2 0x400A434
#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_3 0x400A438
#define mmDCORE0_TPC0_QM_PQC_SIZE_0 0x400A43C
#define mmDCORE0_TPC0_QM_PQC_SIZE_1 0x400A440
#define mmDCORE0_TPC0_QM_PQC_SIZE_2 0x400A444
#define mmDCORE0_TPC0_QM_PQC_SIZE_3 0x400A448
#define mmDCORE0_TPC0_QM_PQC_PI_0 0x400A44C
#define mmDCORE0_TPC0_QM_PQC_PI_1 0x400A450
#define mmDCORE0_TPC0_QM_PQC_PI_2 0x400A454
#define mmDCORE0_TPC0_QM_PQC_PI_3 0x400A458
#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_0 0x400A45C
#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_1 0x400A460
#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_2 0x400A464
#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_3 0x400A468
#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_0 0x400A46C
#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_1 0x400A470
#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_2 0x400A474
#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_3 0x400A478
#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_0 0x400A47C
#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_1 0x400A480
#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_2 0x400A484
#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_3 0x400A488
#define mmDCORE0_TPC0_QM_PQC_CFG 0x400A48C
#define mmDCORE0_TPC0_QM_PQC_SECURE_PUSH_IND 0x400A490
#define mmDCORE0_TPC0_QM_ARB_MASK 0x400A4A0
#define mmDCORE0_TPC0_QM_ARB_CFG_0 0x400A4A4
#define mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH 0x400A4A8
#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0 0x400A4AC
#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1 0x400A4B0
#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2 0x400A4B4
#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3 0x400A4B8
#define mmDCORE0_TPC0_QM_ARB_CFG_1 0x400A4BC
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_0 0x400A4C0
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_1 0x400A4C4
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_2 0x400A4C8
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_3 0x400A4CC
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_4 0x400A4D0
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_5 0x400A4D4
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_6 0x400A4D8
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_7 0x400A4DC
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_8 0x400A4E0
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_9 0x400A4E4
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_10 0x400A4E8
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_11 0x400A4EC
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_12 0x400A4F0
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_13 0x400A4F4
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_14 0x400A4F8
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_15 0x400A4FC
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_16 0x400A500
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_17 0x400A504
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_18 0x400A508
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_19 0x400A50C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_20 0x400A510
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_21 0x400A514
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_22 0x400A518
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_23 0x400A51C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_24 0x400A520
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_25 0x400A524
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_26 0x400A528
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_27 0x400A52C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_28 0x400A530
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_29 0x400A534
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_30 0x400A538
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_31 0x400A53C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_32 0x400A540
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_33 0x400A544
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_34 0x400A548
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_35 0x400A54C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_36 0x400A550
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_37 0x400A554
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_38 0x400A558
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_39 0x400A55C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_40 0x400A560
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_41 0x400A564
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_42 0x400A568
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_43 0x400A56C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_44 0x400A570
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_45 0x400A574
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_46 0x400A578
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_47 0x400A57C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_48 0x400A580
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_49 0x400A584
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_50 0x400A588
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_51 0x400A58C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_52 0x400A590
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_53 0x400A594
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_54 0x400A598
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_55 0x400A59C
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_56 0x400A5A0
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_57 0x400A5A4
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_58 0x400A5A8
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_59 0x400A5AC
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_60 0x400A5B0
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_61 0x400A5B4
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_62 0x400A5B8
#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_63 0x400A5BC
#define mmDCORE0_TPC0_QM_ARB_MST_CRED_INC 0x400A5E0
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x400A5E4
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x400A5E8
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x400A5EC
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x400A5F0
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x400A5F4
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x400A5F8
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x400A5FC
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x400A600
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x400A604
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x400A608
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x400A60C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x400A610
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x400A614
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x400A618
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x400A61C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x400A620
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x400A624
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x400A628
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x400A62C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x400A630
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x400A634
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x400A638
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x400A63C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x400A640
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x400A644
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x400A648
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x400A64C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x400A650
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x400A654
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x400A658
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x400A65C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x400A660
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x400A664
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x400A668
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x400A66C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x400A670
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x400A674
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x400A678
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x400A67C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x400A680
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x400A684
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x400A688
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x400A68C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x400A690
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x400A694
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x400A698
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x400A69C
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x400A6A0
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x400A6A4
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x400A6A8
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x400A6AC
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x400A6B0
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x400A6B4
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x400A6B8
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x400A6BC
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x400A6C0
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x400A6C4
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x400A6C8
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x400A6CC
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x400A6D0
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x400A6D4
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x400A6D8
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x400A6DC
#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x400A6E0
#define mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x400A704
#define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN 0x400A708
#define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1 0x400A70C
#define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_WDT 0x400A710
#define mmDCORE0_TPC0_QM_ARB_SLV_ID 0x400A714
#define mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER 0x400A718
#define mmDCORE0_TPC0_QM_ARB_MSG_MAX_INFLIGHT 0x400A744
#define mmDCORE0_TPC0_QM_ARB_BASE_LO 0x400A754
#define mmDCORE0_TPC0_QM_ARB_BASE_HI 0x400A758
#define mmDCORE0_TPC0_QM_ARB_STATE_STS 0x400A780
#define mmDCORE0_TPC0_QM_ARB_CHOICE_FULLNESS_STS 0x400A784
#define mmDCORE0_TPC0_QM_ARB_MSG_STS 0x400A788
#define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_Q_HEAD 0x400A78C
#define mmDCORE0_TPC0_QM_ARB_ERR_CAUSE 0x400A79C
#define mmDCORE0_TPC0_QM_ARB_ERR_MSG_EN 0x400A7A0
#define mmDCORE0_TPC0_QM_ARB_ERR_STS_DRP 0x400A7A8
#define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS 0x400A7B0
#define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS_1 0x400A7B4
#define mmDCORE0_TPC0_QM_CSMR_STRICT_PRIO_CFG 0x400A7FC
#define mmDCORE0_TPC0_QM_ARC_CQ_CFG0 0x400A800
#define mmDCORE0_TPC0_QM_ARC_CQ_CFG1 0x400A804
#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO 0x400A808
#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI 0x400A80C
#define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE 0x400A810
#define mmDCORE0_TPC0_QM_ARC_CQ_CTL 0x400A814
#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_STS 0x400A81C
#define mmDCORE0_TPC0_QM_ARC_CQ_STS0 0x400A820
#define mmDCORE0_TPC0_QM_ARC_CQ_STS1 0x400A824
#define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE_STS 0x400A828
#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS 0x400A82C
#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS 0x400A830
#define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_HI 0x400A834
#define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_LO 0x400A838
#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x400A83C
#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x400A840
#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x400A844
#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x400A848
#define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_HI 0x400A84C
#define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO 0x400A850
#define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_HI 0x400A854
#define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO 0x400A858
#define mmDCORE0_TPC0_QM_ADDR_OVRD 0x400A85C
#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0 0x400A860
#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1 0x400A864
#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2 0x400A868
#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3 0x400A86C
#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4 0x400A870
#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI 0x400A874
#define mmDCORE0_TPC0_QM_CQ_CTL_CI_0 0x400A878
#define mmDCORE0_TPC0_QM_CQ_CTL_CI_1 0x400A87C
#define mmDCORE0_TPC0_QM_CQ_CTL_CI_2 0x400A880
#define mmDCORE0_TPC0_QM_CQ_CTL_CI_3 0x400A884
#define mmDCORE0_TPC0_QM_CQ_CTL_CI_4 0x400A888
#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI 0x400A88C
#define mmDCORE0_TPC0_QM_CP_CFG 0x400A890
#define mmDCORE0_TPC0_QM_CP_EXT_SWITCH 0x400A894
#define mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET 0x400A898
#define mmDCORE0_TPC0_QM_CP_SWITCH_WD 0x400A89C
#define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_LO 0x400A8A4
#define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_HI 0x400A8A8
#define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_HI 0x400A8AC
#define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_LO 0x400A8B0
#define mmDCORE0_TPC0_QM_ENGINE_ADDR_RANGE_SIZE 0x400A8B4
#define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x400A8B8
#define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x400A8BC
#define mmDCORE0_TPC0_QM_QM_BASE_ADDR_HI 0x400A8C0
#define mmDCORE0_TPC0_QM_QM_BASE_ADDR_LO 0x400A8C4
#define mmDCORE0_TPC0_QM_ARC_PQC_SECURE_PUSH_IND 0x400A8C8
#define mmDCORE0_TPC0_QM_PQC_STS_0_0 0x400A8D0
#define mmDCORE0_TPC0_QM_PQC_STS_0_1 0x400A8D4
#define mmDCORE0_TPC0_QM_PQC_STS_0_2 0x400A8D8
#define mmDCORE0_TPC0_QM_PQC_STS_0_3 0x400A8DC
#define mmDCORE0_TPC0_QM_PQC_STS_1_0 0x400A8E0
#define mmDCORE0_TPC0_QM_PQC_STS_1_1 0x400A8E4
#define mmDCORE0_TPC0_QM_PQC_STS_1_2 0x400A8E8
#define mmDCORE0_TPC0_QM_PQC_STS_1_3 0x400A8EC
#define mmDCORE0_TPC0_QM_SEI_STATUS 0x400A8F0
#define mmDCORE0_TPC0_QM_SEI_MASK 0x400A8F4
#define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_LO 0x400AD00
#define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_HI 0x400AD04
#define mmDCORE0_TPC0_QM_GLBL_ERR_WDATA 0x400AD08
#define mmDCORE0_TPC0_QM_L2H_MASK_LO 0x400AD14
#define mmDCORE0_TPC0_QM_L2H_MASK_HI 0x400AD18
#define mmDCORE0_TPC0_QM_L2H_CMPR_LO 0x400AD1C
#define mmDCORE0_TPC0_QM_L2H_CMPR_HI 0x400AD20
#define mmDCORE0_TPC0_QM_LOCAL_RANGE_BASE 0x400AD24
#define mmDCORE0_TPC0_QM_LOCAL_RANGE_SIZE 0x400AD28
#define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_1 0x400AD30
#define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_0 0x400AD34
#define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_1 0x400AD38
#define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_0 0x400AD3C
#define mmDCORE0_TPC0_QM_IND_GW_APB_CFG 0x400AD40
#define mmDCORE0_TPC0_QM_IND_GW_APB_WDATA 0x400AD44
#define mmDCORE0_TPC0_QM_IND_GW_APB_RDATA 0x400AD48
#define mmDCORE0_TPC0_QM_IND_GW_APB_STATUS 0x400AD4C
#define mmDCORE0_TPC0_QM_PERF_CNT_FREE_LO 0x400AD60
#define mmDCORE0_TPC0_QM_PERF_CNT_FREE_HI 0x400AD64
#define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_LO 0x400AD68
#define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_HI 0x400AD6C
#define mmDCORE0_TPC0_QM_PERF_CNT_CFG 0x400AD70
#endif /* ASIC_REG_DCORE0_TPC0_QM_REGS_H_ */