// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (C) 2021 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>

/ {
	backlight: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_backlight>;
		enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;
		pwms = <&pwm2 0 20000 0>;
		brightness-levels = <0 255>;
		num-interpolated-steps = <17>;
		default-brightness-level = <8>;
		power-supply = <&reg_24v0>;
	};

	display {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "fsl,imx-parallel-display";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu1>;

		port@0 {
			reg = <0>;

			display0_in: endpoint {
				remote-endpoint = <&ipu1_di0_disp0>;
			};
		};

		port@1 {
			reg = <1>;

			display0_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};
	};

	panel {
		compatible = "logictechno,lttd800480070-l2rt";
		backlight = <&backlight>;
		power-supply = <&reg_3v3>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&display0_out>;
			};
		};
	};
};

&ipu1_di0_disp0 {
	remote-endpoint = <&display0_in>;
};

&iomuxc {
	pinctrl_backlight: backlightgrp {
		fsl,pins = <
			MX6QDL_PAD_RGMII_TD3__GPIO6_IO23		0x58
		>;
	};

	pinctrl_ipu1: ipu1grp {
		fsl,pins = <
			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x10
			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x10
			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x10
			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x10
			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x10
			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x10
			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x10
			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x10
			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x10
			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x10
			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x10
			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x10
			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x10
			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x10
			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x10
			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x10
			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x10
			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x10
			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x10
			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x10
			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x10
			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x10
			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x10
			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x10
			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x10
			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x10
			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x10
			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x10
		>;
	};
};