// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Gateway 7001 AP based on IXP422
 * Derived from boardfiles written by Imre Kaloz
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Gateway 7001 AP";
	compatible = "gateway,7001", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 32 MB SDRAM */
		device_type = "memory";
		reg = <0x00000000 0x2000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
		stdout-path = "uart1:115200n8";
	};

	aliases {
		/* second UART is the primary console */
		serial0 = &uart1;
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * 8 MB of flash
				 */
				reg = <0 0x00000000 0x800000>;

				/* Configure expansion bus to allow writes */
				intel,ixp4xx-eb-write-enable = <1>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x7e0000 */
					fis-index-block = <0x3f>;
				};
			};
		};

		pci@c0000000 {
			status = "okay";

			/*
			 * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c)
			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ
			 * each handling all IRQs.
			 */
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			<0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */
			<0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */
			<0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
			<0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */
			<0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */
			<0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */
		};

		ethernet@c8009000 {
			status = "okay";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy1: ethernet-phy@1 {
					reg = <1>;
				};
			};
		};

		ethernet@c800a000 {
			status = "okay";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy2>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy2: ethernet-phy@2 {
					reg = <2>;
				};
			};
		};
	};
};