# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra124 SoC External Memory Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The EMC interfaces with the off-chip SDRAM to service the request stream
sent from the memory controller.
properties:
compatible:
const: nvidia,tegra124-emc
reg:
maxItems: 1
clocks:
items:
- description: external memory clock
clock-names:
items:
- const: emc
"#interconnect-cells":
const: 0
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the memory controller node
power-domains:
maxItems: 1
description:
Phandle of the SoC "core" power domain.
operating-points-v2:
description:
Should contain freqs and voltages and opp-supported-hw property, which
is a bitfield indicating SoC speedo ID mask.
patternProperties:
"^emc-timings-[0-9]+$":
type: object
additionalProperties: false
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
this timing set is used for
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
external memory clock rate in Hz
minimum: 1000000
maximum: 1000000000
nvidia,emc-auto-cal-config:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_AUTO_CAL_CONFIG register for this set of
timings
nvidia,emc-auto-cal-config2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_AUTO_CAL_CONFIG2 register for this set of
timings
nvidia,emc-auto-cal-config3:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_AUTO_CAL_CONFIG3 register for this set of
timings
nvidia,emc-auto-cal-interval:
description:
pad calibration interval in microseconds
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 2097151
nvidia,emc-bgbias-ctl0:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_BGBIAS_CTL0 register for this set of timings
nvidia,emc-cfg:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_CFG register for this set of timings
nvidia,emc-cfg-2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_CFG_2 register for this set of timings
nvidia,emc-ctt-term-ctrl:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_CTT_TERM_CTRL register for this set of timings
nvidia,emc-mode-1:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_MRW register for this set of timings
nvidia,emc-mode-2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_MRW2 register for this set of timings
nvidia,emc-mode-4:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_MRW4 register for this set of timings
nvidia,emc-mode-reset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
reset value of the EMC_MRS register for this set of timings
nvidia,emc-mrs-wait-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMR_MRS_WAIT_CNT register for this set of timings
nvidia,emc-sel-dpd-ctrl:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_SEL_DPD_CTRL register for this set of timings
nvidia,emc-xm2dqspadctrl2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_XM2DQSPADCTRL2 register for this set of timings
nvidia,emc-zcal-cnt-long:
description:
number of EMC clocks to wait before issuing any commands after
clock change
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1023
nvidia,emc-zcal-interval:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_ZCAL_INTERVAL register for this set of timings
nvidia,emc-configuration:
description:
EMC timing characterization data. These are the registers (see
section "15.6.2 EMC Registers" in the TRM) whose values need to
be specified, according to the board documentation.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: EMC_RC
- description: EMC_RFC
- description: EMC_RFC_SLR
- description: EMC_RAS
- description: EMC_RP
- description: EMC_R2W
- description: EMC_W2R
- description: EMC_R2P
- description: EMC_W2P
- description: EMC_RD_RCD
- description: EMC_WR_RCD
- description: EMC_RRD
- description: EMC_REXT
- description: EMC_WEXT
- description: EMC_WDV
- description: EMC_WDV_MASK
- description: EMC_QUSE
- description: EMC_QUSE_WIDTH
- description: EMC_IBDLY
- description: EMC_EINPUT
- description: EMC_EINPUT_DURATION
- description: EMC_PUTERM_EXTRA
- description: EMC_PUTERM_WIDTH
- description: EMC_PUTERM_ADJ
- description: EMC_CDB_CNTL_1
- description: EMC_CDB_CNTL_2
- description: EMC_CDB_CNTL_3
- description: EMC_QRST
- description: EMC_QSAFE
- description: EMC_RDV
- description: EMC_RDV_MASK
- description: EMC_REFRESH
- description: EMC_BURST_REFRESH_NUM
- description: EMC_PRE_REFRESH_REQ_CNT
- description: EMC_PDEX2WR
- description: EMC_PDEX2RD
- description: EMC_PCHG2PDEN
- description: EMC_ACT2PDEN
- description: EMC_AR2PDEN
- description: EMC_RW2PDEN
- description: EMC_TXSR
- description: EMC_TXSRDLL
- description: EMC_TCKE
- description: EMC_TCKESR
- description: EMC_TPD
- description: EMC_TFAW
- description: EMC_TRPAB
- description: EMC_TCLKSTABLE
- description: EMC_TCLKSTOP
- description: EMC_TREFBW
- description: EMC_FBIO_CFG6
- description: EMC_ODT_WRITE
- description: EMC_ODT_READ
- description: EMC_FBIO_CFG5
- description: EMC_CFG_DIG_DLL
- description: EMC_CFG_DIG_DLL_PERIOD
- description: EMC_DLL_XFORM_DQS0
- description: EMC_DLL_XFORM_DQS1
- description: EMC_DLL_XFORM_DQS2
- description: EMC_DLL_XFORM_DQS3
- description: EMC_DLL_XFORM_DQS4
- description: EMC_DLL_XFORM_DQS5
- description: EMC_DLL_XFORM_DQS6
- description: EMC_DLL_XFORM_DQS7
- description: EMC_DLL_XFORM_DQS8
- description: EMC_DLL_XFORM_DQS9
- description: EMC_DLL_XFORM_DQS10
- description: EMC_DLL_XFORM_DQS11
- description: EMC_DLL_XFORM_DQS12
- description: EMC_DLL_XFORM_DQS13
- description: EMC_DLL_XFORM_DQS14
- description: EMC_DLL_XFORM_DQS15
- description: EMC_DLL_XFORM_QUSE0
- description: EMC_DLL_XFORM_QUSE1
- description: EMC_DLL_XFORM_QUSE2
- description: EMC_DLL_XFORM_QUSE3
- description: EMC_DLL_XFORM_QUSE4
- description: EMC_DLL_XFORM_QUSE5
- description: EMC_DLL_XFORM_QUSE6
- description: EMC_DLL_XFORM_QUSE7
- description: EMC_DLL_XFORM_ADDR0
- description: EMC_DLL_XFORM_ADDR1
- description: EMC_DLL_XFORM_ADDR2
- description: EMC_DLL_XFORM_ADDR3
- description: EMC_DLL_XFORM_ADDR4
- description: EMC_DLL_XFORM_ADDR5
- description: EMC_DLL_XFORM_QUSE8
- description: EMC_DLL_XFORM_QUSE9
- description: EMC_DLL_XFORM_QUSE10
- description: EMC_DLL_XFORM_QUSE11
- description: EMC_DLL_XFORM_QUSE12
- description: EMC_DLL_XFORM_QUSE13
- description: EMC_DLL_XFORM_QUSE14
- description: EMC_DLL_XFORM_QUSE15
- description: EMC_DLI_TRIM_TXDQS0
- description: EMC_DLI_TRIM_TXDQS1
- description: EMC_DLI_TRIM_TXDQS2
- description: EMC_DLI_TRIM_TXDQS3
- description: EMC_DLI_TRIM_TXDQS4
- description: EMC_DLI_TRIM_TXDQS5
- description: EMC_DLI_TRIM_TXDQS6
- description: EMC_DLI_TRIM_TXDQS7
- description: EMC_DLI_TRIM_TXDQS8
- description: EMC_DLI_TRIM_TXDQS9
- description: EMC_DLI_TRIM_TXDQS10
- description: EMC_DLI_TRIM_TXDQS11
- description: EMC_DLI_TRIM_TXDQS12
- description: EMC_DLI_TRIM_TXDQS13
- description: EMC_DLI_TRIM_TXDQS14
- description: EMC_DLI_TRIM_TXDQS15
- description: EMC_DLL_XFORM_DQ0
- description: EMC_DLL_XFORM_DQ1
- description: EMC_DLL_XFORM_DQ2
- description: EMC_DLL_XFORM_DQ3
- description: EMC_DLL_XFORM_DQ4
- description: EMC_DLL_XFORM_DQ5
- description: EMC_DLL_XFORM_DQ6
- description: EMC_DLL_XFORM_DQ7
- description: EMC_XM2CMDPADCTRL
- description: EMC_XM2CMDPADCTRL4
- description: EMC_XM2CMDPADCTRL5
- description: EMC_XM2DQPADCTRL2
- description: EMC_XM2DQPADCTRL3
- description: EMC_XM2CLKPADCTRL
- description: EMC_XM2CLKPADCTRL2
- description: EMC_XM2COMPPADCTRL
- description: EMC_XM2VTTGENPADCTRL
- description: EMC_XM2VTTGENPADCTRL2
- description: EMC_XM2VTTGENPADCTRL3
- description: EMC_XM2DQSPADCTRL3
- description: EMC_XM2DQSPADCTRL4
- description: EMC_XM2DQSPADCTRL5
- description: EMC_XM2DQSPADCTRL6
- description: EMC_DSR_VTTGEN_DRV
- description: EMC_TXDSRVTTGEN
- description: EMC_FBIO_SPARE
- description: EMC_ZCAL_WAIT_CNT
- description: EMC_MRS_WAIT_CNT2
- description: EMC_CTT
- description: EMC_CTT_DURATION
- description: EMC_CFG_PIPE
- description: EMC_DYN_SELF_REF_CONTROL
- description: EMC_QPOP
required:
- clock-frequency
- nvidia,emc-auto-cal-config
- nvidia,emc-auto-cal-config2
- nvidia,emc-auto-cal-config3
- nvidia,emc-auto-cal-interval
- nvidia,emc-bgbias-ctl0
- nvidia,emc-cfg
- nvidia,emc-cfg-2
- nvidia,emc-ctt-term-ctrl
- nvidia,emc-mode-1
- nvidia,emc-mode-2
- nvidia,emc-mode-4
- nvidia,emc-mode-reset
- nvidia,emc-mrs-wait-cnt
- nvidia,emc-sel-dpd-ctrl
- nvidia,emc-xm2dqspadctrl2
- nvidia,emc-zcal-cnt-long
- nvidia,emc-zcal-interval
- nvidia,emc-configuration
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- nvidia,memory-controller
- "#interconnect-cells"
- operating-points-v2
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mc: memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x70019000 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
};
external-memory-controller@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x7001b000 0x1000>;
clocks = <&car TEGRA124_CLK_EMC>;
clock-names = "emc";
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
#interconnect-cells = <0>;
emc-timings-0 {
nvidia,ram-code = <3>;
timing-0 {
clock-frequency = <12750000>;
nvidia,emc-auto-cal-config = <0xa1430000>;
nvidia,emc-auto-cal-config2 = <0x00000000>;
nvidia,emc-auto-cal-config3 = <0x00000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-bgbias-ctl0 = <0x00000008>;
nvidia,emc-cfg = <0x73240000>;
nvidia,emc-cfg-2 = <0x000008c5>;
nvidia,emc-ctt-term-ctrl = <0x00000802>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-4 = <0x00000000>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-mrs-wait-cnt = <0x000e000e>;
nvidia,emc-sel-dpd-ctrl = <0x00040128>;
nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
nvidia,emc-zcal-cnt-long = <0x00000042>;
nvidia,emc-zcal-interval = <0x00000000>;
nvidia,emc-configuration = <
0x00000000 /* EMC_RC */
0x00000003 /* EMC_RFC */
0x00000000 /* EMC_RFC_SLR */
0x00000000 /* EMC_RAS */
0x00000000 /* EMC_RP */
0x00000004 /* EMC_R2W */
0x0000000a /* EMC_W2R */
0x00000003 /* EMC_R2P */
0x0000000b /* EMC_W2P */
0x00000000 /* EMC_RD_RCD */
0x00000000 /* EMC_WR_RCD */
0x00000003 /* EMC_RRD */
0x00000003 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000006 /* EMC_WDV */
0x00000006 /* EMC_WDV_MASK */
0x00000006 /* EMC_QUSE */
0x00000002 /* EMC_QUSE_WIDTH */
0x00000000 /* EMC_IBDLY */
0x00000005 /* EMC_EINPUT */
0x00000005 /* EMC_EINPUT_DURATION */
0x00010000 /* EMC_PUTERM_EXTRA */
0x00000003 /* EMC_PUTERM_WIDTH */
0x00000000 /* EMC_PUTERM_ADJ */
0x00000000 /* EMC_CDB_CNTL_1 */
0x00000000 /* EMC_CDB_CNTL_2 */
0x00000000 /* EMC_CDB_CNTL_3 */
0x00000004 /* EMC_QRST */
0x0000000c /* EMC_QSAFE */
0x0000000d /* EMC_RDV */
0x0000000f /* EMC_RDV_MASK */
0x00000060 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002 /* EMC_PDEX2WR */
0x00000002 /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x00000007 /* EMC_AR2PDEN */
0x0000000f /* EMC_RW2PDEN */
0x00000005 /* EMC_TXSR */
0x00000005 /* EMC_TXSRDLL */
0x00000004 /* EMC_TCKE */
0x00000005 /* EMC_TCKESR */
0x00000004 /* EMC_TPD */
0x00000000 /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000005 /* EMC_TCLKSTABLE */
0x00000005 /* EMC_TCLKSTOP */
0x00000064 /* EMC_TREFBW */
0x00000000 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x106aa298 /* EMC_FBIO_CFG5 */
0x002c00a0 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x00064000 /* EMC_DLL_XFORM_DQS0 */
0x00064000 /* EMC_DLL_XFORM_DQS1 */
0x00064000 /* EMC_DLL_XFORM_DQS2 */
0x00064000 /* EMC_DLL_XFORM_DQS3 */
0x00064000 /* EMC_DLL_XFORM_DQS4 */
0x00064000 /* EMC_DLL_XFORM_DQS5 */
0x00064000 /* EMC_DLL_XFORM_DQS6 */
0x00064000 /* EMC_DLL_XFORM_DQS7 */
0x00064000 /* EMC_DLL_XFORM_DQS8 */
0x00064000 /* EMC_DLL_XFORM_DQS9 */
0x00064000 /* EMC_DLL_XFORM_DQS10 */
0x00064000 /* EMC_DLL_XFORM_DQS11 */
0x00064000 /* EMC_DLL_XFORM_DQS12 */
0x00064000 /* EMC_DLL_XFORM_DQS13 */
0x00064000 /* EMC_DLL_XFORM_DQS14 */
0x00064000 /* EMC_DLL_XFORM_DQS15 */
0x00000000 /* EMC_DLL_XFORM_QUSE0 */
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLL_XFORM_ADDR0 */
0x00000000 /* EMC_DLL_XFORM_ADDR1 */
0x00000000 /* EMC_DLL_XFORM_ADDR2 */
0x00000000 /* EMC_DLL_XFORM_ADDR3 */
0x00000000 /* EMC_DLL_XFORM_ADDR4 */
0x00000000 /* EMC_DLL_XFORM_ADDR5 */
0x00000000 /* EMC_DLL_XFORM_QUSE8 */
0x00000000 /* EMC_DLL_XFORM_QUSE9 */
0x00000000 /* EMC_DLL_XFORM_QUSE10 */
0x00000000 /* EMC_DLL_XFORM_QUSE11 */
0x00000000 /* EMC_DLL_XFORM_QUSE12 */
0x00000000 /* EMC_DLL_XFORM_QUSE13 */
0x00000000 /* EMC_DLL_XFORM_QUSE14 */
0x00000000 /* EMC_DLL_XFORM_QUSE15 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
0x000fc000 /* EMC_DLL_XFORM_DQ0 */
0x000fc000 /* EMC_DLL_XFORM_DQ1 */
0x000fc000 /* EMC_DLL_XFORM_DQ2 */
0x000fc000 /* EMC_DLL_XFORM_DQ3 */
0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
0x10000280 /* EMC_XM2CMDPADCTRL */
0x00000000 /* EMC_XM2CMDPADCTRL4 */
0x00111111 /* EMC_XM2CMDPADCTRL5 */
0x00000000 /* EMC_XM2DQPADCTRL2 */
0x00000000 /* EMC_XM2DQPADCTRL3 */
0x77ffc081 /* EMC_XM2CLKPADCTRL */
0x00000e0e /* EMC_XM2CLKPADCTRL2 */
0x81f1f108 /* EMC_XM2COMPPADCTRL */
0x07070004 /* EMC_XM2VTTGENPADCTRL */
0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
0x51451400 /* EMC_XM2DQSPADCTRL3 */
0x00514514 /* EMC_XM2DQSPADCTRL4 */
0x00514514 /* EMC_XM2DQSPADCTRL5 */
0x51451400 /* EMC_XM2DQSPADCTRL6 */
0x0000003f /* EMC_DSR_VTTGEN_DRV */
0x00000007 /* EMC_TXDSRVTTGEN */
0x00000000 /* EMC_FBIO_SPARE */
0x00000042 /* EMC_ZCAL_WAIT_CNT */
0x000e000e /* EMC_MRS_WAIT_CNT2 */
0x00000000 /* EMC_CTT */
0x00000003 /* EMC_CTT_DURATION */
0x0000f2f3 /* EMC_CFG_PIPE */
0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a /* EMC_QPOP */
>;
};
};
};