# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek HDMI Encoder maintainers: - CK Hu <ck.hu@mediatek.com> - Jitao shi <jitao.shi@mediatek.com> description: | The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from its parallel input. properties: compatible: enum: - mediatek,mt2701-hdmi - mediatek,mt7623-hdmi - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi reg: maxItems: 1 interrupts: maxItems: 1 clocks: items: - description: Pixel Clock - description: HDMI PLL - description: Bit Clock - description: S/PDIF Clock clock-names: items: - const: pixel - const: pll - const: bclk - const: spdif phys: maxItems: 1 phy-names: items: - const: hdmi mediatek,syscon-hdmi: $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle to system configuration registers - description: register offset in the system configuration registers description: | phandle link and register offset to the system configuration registers. ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: | Input port node. This port should be connected to a DPI output port. port@1: $ref: /schemas/graph.yaml#/properties/port description: | Output port node. This port should be connected to the input port of a connector node that contains a ddc-i2c-bus property, or to the input port of an attached bridge chip, such as a SlimPort transmitter. required: - port@0 - port@1 required: - compatible - reg - interrupts - clocks - clock-names - phys - phy-names - mediatek,syscon-hdmi - ports additionalProperties: false examples: - | #include <dt-bindings/clock/mt8173-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> hdmi0: hdmi@14025000 { compatible = "mediatek,mt8173-hdmi"; reg = <0x14025000 0x400>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; clocks = <&mmsys CLK_MM_HDMI_PIXEL>, <&mmsys CLK_MM_HDMI_PLLCK>, <&mmsys CLK_MM_HDMI_AUDIO>, <&mmsys CLK_MM_HDMI_SPDIF>; clock-names = "pixel", "pll", "bclk", "spdif"; pinctrl-names = "default"; pinctrl-0 = <&hdmi_pin>; phys = <&hdmi_phy>; phy-names = "hdmi"; mediatek,syscon-hdmi = <&mmsys 0x900>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hdmi0_in: endpoint { remote-endpoint = <&dpi0_out>; }; }; port@1 { reg = <1>; hdmi0_out: endpoint { remote-endpoint = <&hdmi_con_in>; }; }; }; }; ...