// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Goramo MultiLink Router
* There are two variants:
* - MultiLink Basic (a box)
* - MultiLink Max (19" rack mount)
* This device tree supports MultiLink Basic.
* This machine is based on IXP425.
* This is one of the few devices supporting the IXP4xx High-Speed Serial
* (HSS) link for a V.35 WAN interface.
* The hardware originates in Poland.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Goramo MultiLink Router";
compatible = "goramo,multilink-router", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/*
* 64 MB of RAM according to the manual. The MultiLink
* Max has 128 MB.
*/
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
/*
* 74HC4094 which is used as a rudimentary GPIO expander
* FIXME:
* - Create device tree bindings for this as GPIO expander
* - Write a pure DT GPIO driver using these bindings
* - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
*/
gpio_74: gpio-74hc4094 {
compatible = "nxp,74hc4094";
cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
/* oe-gpios is optional */
gpio-controller;
#gpio-cells = <2>;
/* We are not cascaded */
registers-number = <1>;
gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
"CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET",
"CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N";
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
};
pci@c0000000 {
status = "okay";
/*
* The device has 4 slots (IDSEL) with one dedicated IRQ per slot.
* The slots have Ethernet, Ethernet, NEC and MPCI.
* The IDSELs are 11, 12, 13, 14.
*/
interrupt-map =
/* IDSEL 11 - Ethernet A */
<0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
<0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */
<0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */
<0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */
/* IDSEL 12 - Ethernet B */
<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
/* IDSEL 13 - MPCI */
<0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */
<0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */
<0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */
<0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */
/* IDSEL 14 - NEC */
<0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */
<0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */
<0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */
<0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */
};
/* HSS links */
npe@c8006000 {
hss@0 {
status = "okay";
intel,queue-chl-rxtrig = <&qmgr 12>;
intel,queue-chl-txready = <&qmgr 34>;
intel,queue-pkt-rx = <&qmgr 13>;
intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
intel,queue-pkt-txdone = <&qmgr 22>;
/* The Goramo GPIO-based clock etc control */
cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
};
hss@1 {
status = "okay";
intel,queue-chl-rxtrig = <&qmgr 10>;
intel,queue-chl-txready = <&qmgr 35>;
intel,queue-pkt-rx = <&qmgr 0>;
intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>;
intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>;
intel,queue-pkt-txdone = <&qmgr 9>;
/* The Goramo GPIO-based clock etc control */
cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>;
clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>;
};
};
/* EthB */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 32>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 33>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
};