// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board * * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries * * Author: Horatiu Vultur <horatiu.vultur@microchip.com> */ /dts-v1/; #include "lan966x.dtsi" #include "dt-bindings/phy/phy-lan966x-serdes.h" / { model = "Microchip EVB LAN9668"; compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966"; gpio-restart { compatible = "gpio-restart"; gpios = <&gpio 56 GPIO_ACTIVE_LOW>; priority = <200>; }; }; &aes { status = "disabled"; /* Reserved by secure OS */ }; &gpio { miim_a_pins: mdio-pins { /* MDC, MDIO */ pins = "GPIO_28", "GPIO_29"; function = "miim_a"; }; pps_out_pins: pps-out-pins { /* 1pps output */ pins = "GPIO_38"; function = "ptpsync_3"; }; ptp_ext_pins: ptp-ext-pins { /* 1pps input */ pins = "GPIO_35"; function = "ptpsync_0"; }; udc_pins: ucd-pins { /* VBUS_DET B */ pins = "GPIO_8"; function = "usb_slave_b"; }; }; &mdio0 { pinctrl-0 = <&miim_a_pins>; pinctrl-names = "default"; status = "okay"; ext_phy0: ethernet-phy@7 { reg = <7>; interrupts = <24 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy1: ethernet-phy@8 { reg = <8>; interrupts = <24 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy2: ethernet-phy@9 { reg = <9>; interrupts = <24 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy3: ethernet-phy@10 { reg = <10>; interrupts = <24 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy4: ethernet-phy@15 { reg = <15>; interrupts = <24 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy5: ethernet-phy@16 { reg = <16>; interrupts = <24 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy6: ethernet-phy@17 { reg = <17>; interrupts = <24 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy7: ethernet-phy@18 { reg = <18>; interrupts = <24 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; }; &port0 { reg = <2>; phy-handle = <&ext_phy2>; phy-mode = "qsgmii"; phys = <&serdes 0 SERDES6G(1)>; status = "okay"; }; &port1 { reg = <3>; phy-handle = <&ext_phy3>; phy-mode = "qsgmii"; phys = <&serdes 1 SERDES6G(1)>; status = "okay"; }; &port2 { reg = <0>; phy-handle = <&ext_phy0>; phy-mode = "qsgmii"; phys = <&serdes 2 SERDES6G(1)>; status = "okay"; }; &port3 { reg = <1>; phy-handle = <&ext_phy1>; phy-mode = "qsgmii"; phys = <&serdes 3 SERDES6G(1)>; status = "okay"; }; &port4 { reg = <6>; phy-handle = <&ext_phy6>; phy-mode = "qsgmii"; phys = <&serdes 4 SERDES6G(2)>; status = "okay"; }; &port5 { reg = <7>; phy-handle = <&ext_phy7>; phy-mode = "qsgmii"; phys = <&serdes 5 SERDES6G(2)>; status = "okay"; }; &port6 { reg = <4>; phy-handle = <&ext_phy4>; phy-mode = "qsgmii"; phys = <&serdes 6 SERDES6G(2)>; status = "okay"; }; &port7 { reg = <5>; phy-handle = <&ext_phy5>; phy-mode = "qsgmii"; phys = <&serdes 7 SERDES6G(2)>; status = "okay"; }; &serdes { status = "okay"; }; &switch { pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>; pinctrl-names = "default"; status = "okay"; }; &udc { pinctrl-0 = <&udc_pins>; pinctrl-names = "default"; atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; status = "okay"; };