#ifndef ASIC_REG_MMU_REGS_H_
#define ASIC_REG_MMU_REGS_H_
#define mmMMU_INPUT_FIFO_THRESHOLD 0x480000
#define mmMMU_MMU_ENABLE 0x48000C
#define mmMMU_FORCE_ORDERING 0x480010
#define mmMMU_FEATURE_ENABLE 0x480014
#define mmMMU_VA_ORDERING_MASK_31_7 0x480018
#define mmMMU_VA_ORDERING_MASK_49_32 0x48001C
#define mmMMU_LOG2_DDR_SIZE 0x480020
#define mmMMU_SCRAMBLER 0x480024
#define mmMMU_MEM_INIT_BUSY 0x480028
#define mmMMU_SPI_MASK 0x48002C
#define mmMMU_SPI_CAUSE 0x480030
#define mmMMU_PAGE_ERROR_CAPTURE 0x480034
#define mmMMU_PAGE_ERROR_CAPTURE_VA 0x480038
#define mmMMU_ACCESS_ERROR_CAPTURE 0x48003C
#define mmMMU_ACCESS_ERROR_CAPTURE_VA 0x480040
#endif /* ASIC_REG_MMU_REGS_H_ */