// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada 388 Reference Design board * (RD-88F6820-AP) * * Copyright (C) 2014 Marvell * * Gregory CLEMENT <gregory.clement@free-electrons.com> * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */ /dts-v1/; #include "armada-388.dtsi" / { model = "Marvell Armada 385 Reference Design"; compatible = "marvell,a385-rd", "marvell,armada388", "marvell,armada385","marvell,armada380"; chosen { stdout-path = "serial0:115200n8"; }; memory { device_type = "memory"; reg = <0x00000000 0x10000000>; /* 256 MB */ }; soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; internal-regs { i2c@11000 { status = "okay"; clock-frequency = <100000>; }; sdhci@d8000 { pinctrl-names = "default"; pinctrl-0 = <&sdhci_pins>; broken-cd; no-1-8-v; wp-inverted; bus-width = <8>; status = "okay"; }; serial@12000 { status = "okay"; }; ethernet@30000 { status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@70000 { status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; }; mdio@72004 { phy0: ethernet-phy@0 { reg = <0>; }; phy1: ethernet-phy@1 { reg = <1>; }; }; usb3@f0000 { status = "okay"; }; }; pcie { status = "okay"; /* * One PCIe units is accessible through * standard PCIe slot on the board. */ pcie@1,0 { /* Port 0, Lane 0 */ status = "okay"; }; }; }; }; &spi0 { status = "okay"; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <108000000>; }; };