#ifndef ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_
#define ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_
#define mmPDMA0_QM_AXUSER_SECURED_HB_ASID 0x4C8AB00
#define mmPDMA0_QM_AXUSER_SECURED_HB_MMU_BP 0x4C8AB04
#define mmPDMA0_QM_AXUSER_SECURED_HB_STRONG_ORDER 0x4C8AB08
#define mmPDMA0_QM_AXUSER_SECURED_HB_NO_SNOOP 0x4C8AB0C
#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_REDUCTION 0x4C8AB10
#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_ATOMIC 0x4C8AB14
#define mmPDMA0_QM_AXUSER_SECURED_HB_QOS 0x4C8AB18
#define mmPDMA0_QM_AXUSER_SECURED_HB_RSVD 0x4C8AB1C
#define mmPDMA0_QM_AXUSER_SECURED_HB_EMEM_CPAGE 0x4C8AB20
#define mmPDMA0_QM_AXUSER_SECURED_HB_CORE 0x4C8AB24
#define mmPDMA0_QM_AXUSER_SECURED_E2E_COORD 0x4C8AB28
#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_LO 0x4C8AB30
#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_HI 0x4C8AB34
#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_LO 0x4C8AB38
#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_HI 0x4C8AB3C
#define mmPDMA0_QM_AXUSER_SECURED_LB_COORD 0x4C8AB40
#define mmPDMA0_QM_AXUSER_SECURED_LB_LOCK 0x4C8AB44
#define mmPDMA0_QM_AXUSER_SECURED_LB_RSVD 0x4C8AB48
#define mmPDMA0_QM_AXUSER_SECURED_LB_OVRD 0x4C8AB4C
#endif /* ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_ */