#ifndef ASIC_REG_PSOC_RESET_CONF_MASKS_H_
#define ASIC_REG_PSOC_RESET_CONF_MASKS_H_
#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_MASK 0xFFFFFFFF
#define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_MASK 0xFFFFFFFF
#define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_MASK 0xFFFFFFFF
#define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_MASK 0xFFFFFFFF
#define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_MASK 0xFFFFFFFF
#define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_MASK 0xFFFFFFFF
#define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_MASK 0xFFFFFFFF
#define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_MASK 0xFFFFFFFF
#define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_MASK 0x1FFFFFF
#define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_MASK 0x1FFFFFF
#define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_MASK 0x1FFFFFF
#define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_MASK 0x1FFFFFF
#define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_MASK 0x1FFFFFF
#define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_MASK 0x1FFFFFF
#define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_MASK 0x1FFFFFF
#define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_MASK 0x1FFFFFF
#define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_MASK 0xFF
#define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_MASK 0x1
#define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_MASK 0x1F
#define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_MASK 0x3
#define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_MASK 0xF
#define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_MASK 0x3FF
#define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_MASK 0x3FF
#define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_MASK 0x3FF
#define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_MASK 0x3FF
#define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_MASK 0x3FF
#define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_MASK 0x3FF
#define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_MASK 0x3FF
#define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_MASK 0x3FF
#define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_MASK 0x3F
#define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_MASK 0x7
#define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_MASK 0x7
#define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_MASK 0x7
#define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_MASK 0x7
#define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_MASK 0x7
#define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_MASK 0x7
#define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_MASK 0x7
#define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_MASK 0x7
#define PSOC_RESET_CONF_SOFT_RST_IND_SHIFT 0
#define PSOC_RESET_CONF_SOFT_RST_IND_MASK 0x1
#define PSOC_RESET_CONF_SW_ALL_RST_IND_SHIFT 0
#define PSOC_RESET_CONF_SW_ALL_RST_IND_MASK 0x1
#define PSOC_RESET_CONF_UNIT_RST_N_IND_SHIFT 0
#define PSOC_RESET_CONF_UNIT_RST_N_IND_MASK 0x1
#define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_MASK 0x1
#define PSOC_RESET_CONF_CPU_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_UNIT_RST_EN_MASK 0x1
#define PSOC_RESET_CONF_ARC_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_UNIT_RST_EN_MASK 0x3
#define PSOC_RESET_CONF_SIF_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_SIF_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_MASK 0x1
#define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_MASK 0x1
#define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_MASK 0x1F
#define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_MASK 0x3F
#define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_MASK 0x1
#define PSOC_RESET_CONF_PM_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_PM_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_MASK 0xFFFFFFFF
#define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_MASK 0x3
#define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_TPC_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_TPC_UNIT_RST_EN_MASK 0x1FFFFFF
#define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_MASK 0xFF
#define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_MASK 0x1
#define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_MASK 0x3
#define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_MASK 0x1F
#define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_MASK 0x3
#define PSOC_RESET_CONF_SM_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_SM_UNIT_RST_EN_MASK 0xF
#define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_MASK 0x3FF
#define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_MASK 0x3F
#define PSOC_RESET_CONF_NIC_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_UNIT_RST_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_MASK 0xFFF
#define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_MASK 0x7
#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
#endif /* ASIC_REG_PSOC_RESET_CONF_MASKS_H_ */