# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display DPU on SC7280 maintainers: - Krishna Manikandan <quic_mkrishn@quicinc.com> $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: const: qcom,sc7280-dpu reg: items: - description: Address offset and size for mdp register set - description: Address offset and size for vbif register set reg-names: items: - const: mdp - const: vbif clocks: items: - description: Display hf axi clock - description: Display sf axi clock - description: Display ahb clock - description: Display lut clock - description: Display core clock - description: Display vsync clock clock-names: items: - const: bus - const: nrt_bus - const: iface - const: lut - const: core - const: vsync required: - compatible - reg - reg-names - clocks - clock-names unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,dispcc-sc7280.h> #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/power/qcom-rpmpd.h> display-controller@ae01000 { compatible = "qcom,sc7280-dpu"; reg = <0x0ae01000 0x8f000>, <0x0aeb0000 0x2008>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "nrt_bus", "iface", "lut", "core", "vsync"; interrupt-parent = <&mdss>; interrupts = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&mdp_opp_table>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; endpoint { remote-endpoint = <&dsi0_in>; }; }; port@1 { reg = <1>; endpoint { remote-endpoint = <&edp_in>; }; }; }; }; ...