// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017-2018 MediaTek Inc. * Author: Sean Wang <sean.wang@mediatek.com> * */ /dts-v1/; #include <dt-bindings/power/mt7623a-power.h> #include "mt7623.dtsi" &afe { power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; }; &crypto { power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; }; &gmac0 { status = "okay"; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; &gmac1 { status = "okay"; phy-mode = "rgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; ð { status = "okay"; power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; mdio: mdio-bus { #address-cells = <1>; #size-cells = <0>; switch0: switch@1f { compatible = "mediatek,mt7530"; reg = <0x1f>; mediatek,mcm; resets = <ðsys MT2701_ETHSYS_MCM_RST>; reset-names = "mcm"; core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { status = "disabled"; reg = <0>; label = "swp0"; }; port@1 { status = "disabled"; reg = <1>; label = "swp1"; }; port@2 { status = "disabled"; reg = <2>; label = "swp2"; }; port@3 { status = "disabled"; reg = <3>; label = "swp3"; }; port@4 { status = "disabled"; reg = <4>; label = "swp4"; }; port@5 { reg = <5>; label = "cpu"; ethernet = <&gmac1>; phy-mode = "rgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; }; }; }; }; &nandc { power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; }; &pcie { power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; }; &scpsys { compatible = "mediatek,mt7623a-scpsys"; clocks = <&topckgen CLK_TOP_ETHIF_SEL>; clock-names = "ethif"; }; &usb0 { power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; }; &usb1 { power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; }; &usb2 { power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; };