#ifndef ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_
#define ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_ASID 0x400AB80
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x400AB84
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x400AB88
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x400AB8C
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x400AB90
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x400AB94
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_QOS 0x400AB98
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RSVD 0x400AB9C
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x400ABA0
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_CORE 0x400ABA4
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_E2E_COORD 0x400ABA8
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x400ABB0
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x400ABB4
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x400ABB8
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x400ABBC
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_COORD 0x400ABC0
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_LOCK 0x400ABC4
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_RSVD 0x400ABC8
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_OVRD 0x400ABCC
#endif /* ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_ */