# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra HDMI Output Encoder maintainers: - Thierry Reding <thierry.reding@gmail.com> - Jon Hunter <jonathanh@nvidia.com> properties: $nodename: pattern: "^hdmi@[0-9a-f]+$" compatible: oneOf: - enum: - nvidia,tegra20-hdmi - nvidia,tegra30-hdmi - nvidia,tegra114-hdmi - nvidia,tegra124-hdmi - items: - const: nvidia,tegra132-hdmi - const: nvidia,tegra124-hdmi reg: maxItems: 1 interrupts: maxItems: 1 clocks: items: - description: module clock - description: parent clock clock-names: items: - const: hdmi - const: parent resets: items: - description: module reset reset-names: items: - const: hdmi operating-points-v2: true power-domains: items: - description: phandle to the core power domain hdmi-supply: description: supply for the +5V HDMI connector pin vdd-supply: description: regulator for supply voltage pll-supply: description: regulator for PLL nvidia,ddc-i2c-bus: description: phandle of an I2C controller used for DDC EDID probing $ref: /schemas/types.yaml#/definitions/phandle nvidia,hpd-gpio: description: specifies a GPIO used for hotplug detection maxItems: 1 nvidia,edid: description: supplies a binary EDID blob $ref: /schemas/types.yaml#/definitions/uint8-array nvidia,panel: description: phandle of a display panel $ref: /schemas/types.yaml#/definitions/phandle "#sound-dai-cells": const: 0 additionalProperties: false required: - compatible - reg - interrupts - clocks - clock-names - resets - reset-names - pll-supply - vdd-supply - nvidia,ddc-i2c-bus - nvidia,hpd-gpio examples: - | #include <dt-bindings/clock/tegra124-car.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/tegra-gpio.h> hdmi@54280000 { compatible = "nvidia,tegra124-hdmi"; reg = <0x54280000 0x00040000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_HDMI>, <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; hdmi-supply = <&vdd_5v0_hdmi>; pll-supply = <&vdd_hdmi_pll>; vdd-supply = <&vdd_3v3_hdmi>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; };