// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple T6002 "M1 Ultra" SoC
*
* Other names: H13J, "Jade 2C"
*
* Copyright The Asahi Linux Contributors
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
#include "multi-die-cpp.h"
#include "t600x-common.dtsi"
/ {
compatible = "apple,t6002", "apple,arm-platform";
#address-cells = <2>;
#size-cells = <2>;
cpus {
cpu-map {
cluster3 {
core0 {
cpu = <&cpu_e10>;
};
core1 {
cpu = <&cpu_e11>;
};
};
cluster4 {
core0 {
cpu = <&cpu_p20>;
};
core1 {
cpu = <&cpu_p21>;
};
core2 {
cpu = <&cpu_p22>;
};
core3 {
cpu = <&cpu_p23>;
};
};
cluster5 {
core0 {
cpu = <&cpu_p30>;
};
core1 {
cpu = <&cpu_p31>;
};
core2 {
cpu = <&cpu_p32>;
};
core3 {
cpu = <&cpu_p33>;
};
};
};
cpu_e10: cpu@800 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x800>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_3>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
operating-points-v2 = <&icestorm_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e_die1>;
};
cpu_e11: cpu@801 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x801>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_3>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
operating-points-v2 = <&icestorm_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e_die1>;
};
cpu_p20: cpu@10900 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10900>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_4>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&firestorm_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p0_die1>;
};
cpu_p21: cpu@10901 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10901>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_4>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&firestorm_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p0_die1>;
};
cpu_p22: cpu@10902 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10902>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_4>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&firestorm_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p0_die1>;
};
cpu_p23: cpu@10903 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10903>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_4>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&firestorm_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p0_die1>;
};
cpu_p30: cpu@10a00 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10a00>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_5>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&firestorm_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p1_die1>;
};
cpu_p31: cpu@10a01 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10a01>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_5>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&firestorm_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p1_die1>;
};
cpu_p32: cpu@10a02 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10a02>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_5>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&firestorm_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p1_die1>;
};
cpu_p33: cpu@10a03 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10a03>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
next-level-cache = <&l2_cache_5>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
operating-points-v2 = <&firestorm_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p1_die1>;
};
l2_cache_3: l2-cache-3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x400000>;
};
l2_cache_4: l2-cache-4 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0xc00000>;
};
l2_cache_5: l2-cache-5 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0xc00000>;
};
};
die0: soc@200000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x2 0x0 0x2 0x0 0x4 0x0>,
<0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>,
<0x7 0x0 0x7 0x0 0xf 0x80000000>;
nonposted-mmio;
// filled via templated includes at the end of the file
};
die1: soc@2200000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x2 0x0 0x22 0x0 0x4 0x0>,
<0x7 0x0 0x27 0x0 0xf 0x80000000>;
nonposted-mmio;
// filled via templated includes at the end of the file
};
};
#define DIE
#define DIE_NO 0
&die0 {
#include "t600x-die0.dtsi"
#include "t600x-dieX.dtsi"
};
#include "t600x-pmgr.dtsi"
#include "t600x-gpio-pins.dtsi"
#undef DIE
#undef DIE_NO
#define DIE _die1
#define DIE_NO 1
&die1 {
#include "t600x-dieX.dtsi"
#include "t600x-nvme.dtsi"
};
#include "t600x-pmgr.dtsi"
#undef DIE
#undef DIE_NO
&aic {
affinities {
e-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_E>;
cpus = <&cpu_e00 &cpu_e01
&cpu_e10 &cpu_e11>;
};
p-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_P>;
cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
&cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13
&cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23
&cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>;
};
};
};
&ps_gfx {
// On t6002, the die0 GPU power domain needs both AFR power domains
power-domains = <&ps_afr>, <&ps_afr_die1>;
};