// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017 - 2022, Xilinx, Inc. * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ /dts-v1/; #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> #include <dt-bindings/phy/phy.h> / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; /* Another 4GB connected to PL */ }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &dcc { status = "okay"; }; &fpd_dma_chan1 { status = "okay"; }; &fpd_dma_chan2 { status = "okay"; }; &fpd_dma_chan3 { status = "okay"; }; &fpd_dma_chan4 { status = "okay"; }; &fpd_dma_chan5 { status = "okay"; }; &fpd_dma_chan6 { status = "okay"; }; &fpd_dma_chan7 { status = "okay"; }; &fpd_dma_chan8 { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &gpu { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = <IO_STANDARD_LVCMOS18>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = <SLEW_RATE_FAST>; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = <SLEW_RATE_SLOW>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &psgtr { status = "okay"; /* nc, dp, usb3, sata */ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &rtc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; xlnx,mio-bank = <1>; }; &uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; &zynqmp_dpdma { status = "okay"; }; &zynqmp_dpsub { status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 1>, <&psgtr 0 PHY_TYPE_DP 1 1>; };