#ifndef ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_
#define ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_ASID 0x40CAB00
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_MMU_BP 0x40CAB04
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_STRONG_ORDER 0x40CAB08
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_NO_SNOOP 0x40CAB0C
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_REDUCTION 0x40CAB10
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_ATOMIC 0x40CAB14
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_QOS 0x40CAB18
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RSVD 0x40CAB1C
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_EMEM_CPAGE 0x40CAB20
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_CORE 0x40CAB24
#define mmDCORE0_MME_QM_AXUSER_SECURED_E2E_COORD 0x40CAB28
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_OVRD_LO 0x40CAB30
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_OVRD_HI 0x40CAB34
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_OVRD_LO 0x40CAB38
#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_OVRD_HI 0x40CAB3C
#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_COORD 0x40CAB40
#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_LOCK 0x40CAB44
#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_RSVD 0x40CAB48
#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_OVRD 0x40CAB4C
#endif /* ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_ */