# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip PX30 Clock and Reset Unit (CRU) maintainers: - Elaine Zhang <zhangqing@rock-chips.com> - Heiko Stuebner <heiko@sntech.de> description: | The PX30 clock controller generates and supplies clocks to various controllers within the SoC and also implements a reset controller for SoC peripherals. Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be used in device tree sources. Similar macros exist for the reset sources in these files. There are several clocks that are generated outside the SoC. It is expected that they are defined using standard clock bindings with following clock-output-names: - "xin24m" - crystal input - required - "xin32k" - rtc clock - optional - "i2sx_clkin" - external I2S clock - optional - "gmac_clkin" - external GMAC clock - optional properties: compatible: enum: - rockchip,px30-cru - rockchip,px30-pmucru reg: maxItems: 1 "#clock-cells": const: 1 "#reset-cells": const: 1 clocks: minItems: 1 items: - description: Clock for both PMUCRU and CRU - description: Clock for CRU (sourced from PMUCRU) clock-names: minItems: 1 items: - const: xin24m - const: gpll rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the syscon managing the "general register files" (GRF), if missing pll rates are not changeable, due to the missing pll lock status. required: - compatible - reg - clocks - clock-names - "#clock-cells" - "#reset-cells" allOf: - if: properties: compatible: contains: const: rockchip,px30-cru then: properties: clocks: minItems: 2 clock-names: minItems: 2 else: properties: clocks: maxItems: 1 clock-names: maxItems: 1 additionalProperties: false examples: - | #include <dt-bindings/clock/px30-cru.h> pmucru: clock-controller@ff2bc000 { compatible = "rockchip,px30-pmucru"; reg = <0xff2bc000 0x1000>; clocks = <&xin24m>; clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; }; cru: clock-controller@ff2b0000 { compatible = "rockchip,px30-cru"; reg = <0xff2b0000 0x1000>; clocks = <&xin24m>, <&pmucru PLL_GPLL>; clock-names = "xin24m", "gpll"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; };