# SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip specific extensions to the Analogix Display Port maintainers: - Sandy Huang <hjc@rock-chips.com> - Heiko Stuebner <heiko@sntech.de> properties: compatible: enum: - rockchip,rk3288-dp - rockchip,rk3399-edp clocks: minItems: 2 maxItems: 3 clock-names: minItems: 2 items: - const: dp - const: pclk - const: grf power-domains: maxItems: 1 resets: maxItems: 1 reset-names: const: dp rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: This SoC makes use of GRF regs. required: - compatible - clocks - clock-names - resets - reset-names - rockchip,grf allOf: - $ref: /schemas/display/bridge/analogix,dp.yaml# unevaluatedProperties: false examples: - | #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> dp@ff970000 { compatible = "rockchip,rk3288-dp"; reg = <0xff970000 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; phys = <&dp_phy>; phy-names = "dp"; resets = <&cru 111>; reset-names = "dp"; rockchip,grf = <&grf>; pinctrl-0 = <&edp_hpd>; pinctrl-names = "default"; ports { #address-cells = <1>; #size-cells = <0>; edp_in: port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; edp_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_edp>; }; edp_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_edp>; }; }; edp_out: port@1 { reg = <1>; edp_out_panel: endpoint { remote-endpoint = <&panel_in_edp>; }; }; }; };