#ifndef ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_
#define ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID 0x411FA80
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP 0x411FA84
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x411FA88
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP 0x411FA8C
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x411FA90
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x411FA94
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS 0x411FA98
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD 0x411FA9C
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x411FAA0
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE 0x411FAA4
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD 0x411FAA8
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x411FAB0
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x411FAB4
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x411FAB8
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x411FABC
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD 0x411FAC0
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK 0x411FAC4
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD 0x411FAC8
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD 0x411FACC
#endif /* ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_ */