// SPDX-License-Identifier: ISC /* * Device Tree file for the Gateworks Avila GW2348 board. * This machine is based on IXP425. */ /dts-v1/; #include "intel-ixp42x.dtsi" #include <dt-bindings/input/input.h> / { model = "Gateworks Avila GW2348"; compatible = "gateworks,gw2348", "intel,ixp42x"; #address-cells = <1>; #size-cells = <1>; memory@0 { device_type = "memory"; reg = <0x00000000 0x4000000>; }; chosen { bootargs = "console=ttyS0,115200n8"; stdout-path = "uart0:115200n8"; }; aliases { serial0 = &uart0; }; leds { compatible = "gpio-leds"; led-user { label = "gw2348:green:user"; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; default-state = "on"; linux,default-trigger = "heartbeat"; }; }; i2c { compatible = "i2c-gpio"; sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; hwmon@28 { compatible = "adi,ad7418"; reg = <0x28>; }; rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; eeprom@51 { compatible = "atmel,24c08"; reg = <0x51>; pagesize = <16>; size = <1024>; read-only; }; }; soc { bus@c4000000 { flash@0,0 { compatible = "intel,ixp4xx-flash", "cfi-flash"; bank-width = <2>; /* Enable writes on the expansion bus */ intel,ixp4xx-eb-write-enable = <1>; /* 16 MB of Flash mapped in at CS0 */ reg = <0 0x00000000 0x1000000>; partitions { compatible = "redboot-fis"; /* Eraseblock at 0x0fe0000 */ fis-index-block = <0x7f>; }; }; ide@1,0 { compatible = "intel,ixp4xx-compact-flash"; /* * Set up expansion bus config to a really slow timing. * The CF driver will dynamically reconfigure these timings * depending on selected PIO mode (0-4). */ intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type intel,ixp4xx-eb-byte-access-on-halfword = <1>; intel,ixp4xx-eb-mux-address-and-data = <0>; intel,ixp4xx-eb-ahb-split-transfers = <0>; intel,ixp4xx-eb-write-enable = <1>; intel,ixp4xx-eb-byte-access = <1>; /* First register set is CMD second is CTL (notice it uses CS2) */ reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>; interrupt-parent = <&gpio0>; interrupts = <12 IRQ_TYPE_EDGE_RISING>; }; /* * FIXME: Latch LEDs or extra UARTs at CS4 */ }; pci@c0000000 { status = "okay"; /* * Taken from Avila PCI boardfile. * * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. */ #interrupt-cells = <1>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = /* IDSEL 1 */ <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ /* IDSEL 2 */ <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ /* IDSEL 3 */ <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ /* IDSEL 4 */ <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ }; /* EthB */ ethernet@c8009000 { status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { reg = <0>; }; phy1: ethernet-phy@1 { reg = <1>; }; }; }; /* EthC */ ethernet@c800a000 { status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; phy-handle = <&phy1>; }; }; };