#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_
#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0 0x40CB268
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1 0x40CB26C
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2 0x40CB270
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3 0x40CB274
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4 0x40CB278
#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_ */